CN102473683B - 具有背侧散热的绝缘体上半导体 - Google Patents

具有背侧散热的绝缘体上半导体 Download PDF

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Publication number
CN102473683B
CN102473683B CN201080031811.8A CN201080031811A CN102473683B CN 102473683 B CN102473683 B CN 102473683B CN 201080031811 A CN201080031811 A CN 201080031811A CN 102473683 B CN102473683 B CN 102473683B
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China
Prior art keywords
layer
heat dissipating
dissipating layer
insulating regions
dug
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Expired - Fee Related
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CN201080031811.8A
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CN102473683A (zh
Inventor
P.A.尼加德
S.B.莫林
M.A.斯图伯
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Qualcomm Inc
Qualcomm Switch Corp
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IO Semiconductor Inc
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Priority to CN201510430892.3A priority Critical patent/CN105097712A/zh
Publication of CN102473683A publication Critical patent/CN102473683A/zh
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Abstract

本发明实施例实现了对绝缘体上半导体(SOI)结构的散热。在一个实施例中，公开了一种制造集成电路的方法。在第一步骤中，在绝缘体上半导体晶圆的有源层中形成有源电路。在第二步骤中，从布置在所述绝缘体上半导体晶圆背侧的基板层去除基板材料。在第三步骤中，从所述绝缘体上半导体绝缘的所述背侧去除绝缘材料以形成挖掉的绝缘区域。在第四步骤中，在所述挖掉的绝缘区域中沉积散热层。所述散热层是导热的并且是电绝缘的。

Description

具有背侧散热的绝缘体上半导体
相关申请的交叉引用
本申请要求2009年7月15日提交的美国临时专利No.61/225,914的权益。通过引用将美国临时专利No.61/225,914并入本文。
技术领域
所描述的本发明总体上涉及绝缘体上半导体器件及处理，更具体地涉及绝缘体上半导体器件中的散热。
背景技术
绝缘体上半导体（SOI）技术最早在20世纪90年代后期被商业化。SOI技术的特色特征在于其中形成了电路的半导体区域通过电绝缘层与主体基板隔开。该绝缘层通常是二氧化硅。选择二氧化硅的原因是，可以通过使晶圆氧化而在硅晶圆上形成二氧化硅，由此适合于进行有效制造。SOI技术的有利方面直接源于绝缘层将有源层与主体基板进行电子隔离的能力。当在此处以及所附权利要求中使用时，SOI结构上的形成有信号处理电路的区域指的是SOI结构的有源层。
SOI技术由于引入对SOI结构中的有源器件进行隔离（这改进了有源器件的电特性）的绝缘层而表现出对传统主体基板技术的改进。例如，希望晶体管的阈值电压统一，并且大体上由晶体管栅极下的半导体材料的特性设定晶体管的阈值。如果该材料区域是隔离的，则进一步的处理将影响该区域并改变器件阈值电压的可能性很小。由于SOI结构的使用而得到的其它电特性改进包括：更小的短沟道效益、针对更高速度的降低的电容、以及器件作为开关时的更低的插入损耗。此外，绝缘层可用来对有源器件与有害辐射进行屏蔽。这对于用于地球大气之外的有害离子辐射盛行的空间中的集成电路是特别重要的。
图1示出了一个SOI晶圆100。晶圆包括基板层101、绝缘层102以及有源层103。基板通常是诸如硅之类的半导体材料。绝缘层102是介电的，并且通常是通过对基板层101进行氧化而形成的二氧化硅。有源层103包括在已经在其中形成了电路104之后出现的掺杂物、电介质、多晶硅、金属层、钝化物以及其它层的组合。电路104可包括：金属布线，诸如电阻器、电容器和电感器之类的无源器件，以及诸如晶体管之类的有源器件。当在此处以及所附权利要求中使用时，SOI晶圆100的“顶部”指的是顶部表面105，而SOI晶圆100的“底部”指的是底部表面106。定位方案不考虑SOI晶圆100相对于其它参考系的相对定位、以及从SOI晶圆100去除层或向SOI晶圆100添加层。因此，有源层103总是处于绝缘层102“上方”。此外，从有源层103中央起始并向底部表面106延伸的矢量总是指向SOI结构的“背侧”方向，而不考虑SOI晶圆100相对于其它参考系的相对定位、以及从SOI晶圆100去除层或向SOI晶圆100添加层。
如上所述，SOI器件具有提高并保持其有源器件的点特性的能力。但是，绝缘层的引入造成了器件散热能力方面的严重问题。由于集成电路中的器件的不断小型化，必须将更多数量的生热器件压缩在越来越小的区域中。在现代集成电路中，电路104的热产生密度可能很偏激。绝缘层102的引入使得这一问题变得严重，这是因为绝缘层102的热导率一般远远小于标准主体基板的热导率。如上所述，在现代SOI技术中，二氧化硅是普遍存在的绝缘层。在300度的开氏温度（K）下，二氧化硅具有大约1.4瓦特每米每开（W/m·K）的热导率。同样温度下的主体硅基板具有大约130W/m·K的热导率。SOI技术出现的散热性能的将近100倍的下降是很成问题的。集成电路中的高程度的热量会将其器件的电特性转移至期望范围之外，从而造成致命的设计失效。如果不经检测，则器件中的过热将导致器件电路中材料歪曲或材料熔化的形式的永远的致命失效。
已经利用各种解决方案来解决SOI器件中的散热问题。一种方案包括布置从绝缘层102向上通过有源层103的热传送柱。在一些情况下，这些热传送柱由金属形成，这是因为金属与二氧化硅相比总体具有远远更高的热导率。在一些方案中，这些柱由多晶硅形成，从而使得它们不会干扰电路的电特性，而同时它们提供了向上到达并离开绝缘层102的热路径。在其它方案中，在绝缘层102中切孔，并且将热传送柱布置在这些孔中。该结构的结果是提供了从有源层103通过绝缘层102中的孔向下到达基板101的散热通道。随后通过基板101散热。
SOI器件中的散热问题另一解决方案包括从背侧操作晶圆。图1B图示了SOI晶圆100是如何能够接合至由操纵基板108和操纵绝缘层109组成的操纵晶圆107上的。虽然这是操纵的通用类型，但是绝缘层109不是必须是绝缘材料，一些现代工艺采用以半导体材料或导电材料来代替绝缘层109的操纵晶圆。在接合至操纵晶圆之后，所得到的结构随后上下翻面以形成图1B所示的结构。在该方案下，随后选择性地从SOI晶圆100背面去除基板101和绝缘层102。去除基板101以及选择性去除绝缘层102之后，金属层110沉积在经刻蚀的区域，以实现通过绝缘层102的更高程度的热导率。该金属通常在集成电路工作时次要地用作有源层103中的器件的接地线或信息信号线。虽然得到的结构显示了优于没有背部散热的SOI结构的散热能力，但是直接在有源基板下去除绝缘层的事实削弱了SOI结构在保持及提高有源器件的电性能方面的优势。
发明内容
在本发明的一个实施例中，公开了一种绝缘体上半导体。该集成电路包括：散热层；位于所述散热层上方的有源层；以及位于所述有源层上方的操纵晶圆。所述散热层具有高热导率并且电绝缘。
在本发明的另一个实施例中，公开了一种从绝缘体上半导体器件散热的方法。在第一步骤中，横向跨越绝缘层的顶部表面将热量传导通过有源层。在第二步骤中，将来自所述绝缘层的热量散发通过散热层。所述有源层位于所述散热层上方。此外，所述绝缘层位于所述有源层上方，所述绝缘层至少部分地与所述散热层共同垂直延伸，并且所述绝缘层包括挖掉的绝缘区域。而且，所述散热层具有高热导率并电绝缘，并且所述散热层位于所述挖掉的绝缘区域中。
在本发明的另一个实施例中，公开了一种制造集成电路的方法。在一个步骤中，在绝缘体上半导体晶圆的有源层中形成有源电路。在第另一个步骤中，从布置在所述绝缘体上半导体晶圆背侧的基板层去除基板材料。在另一个步骤中，从所述绝缘体上半导体绝缘的所述背侧去除绝缘材料以形成挖掉的绝缘区域。在另一个步骤中，在所述挖掉的绝缘区域中沉积散热层。所述散热层是电绝缘的。
附图说明
图1A和图1B图示了根据现有技术的用于SOI结构的散热的处理和设备的框图。
图2图示了根据本发明的具有散热层的SOI结构的框图。
图3图示了根据本发明的具有散热层和图案化的绝缘层的SOI结构的框图。
图4图示了具有散热层、图案化的绝缘层以及背侧金属接触的SOI结构的框图。
图5图示了根据本发明的具有附接的背侧散热操纵晶圆的SOI结构的框图。
图6图示了根据本发明的具有附接的背侧散热操纵晶圆和图案化的绝缘层的SOI结构的框图。
图7图示了根据本发明的制造具有散热层的集成电路的方法的流程图。
图8图示了根据本发明的利用临时操纵晶圆制造具有散热层的集成电路的方法的流程图。
图9图示了根据本发明的具有图案化的应变层的SOI结构的框图。
图10图示了根据本发明的可使用的各种应变层图案的框图。
图11图示了根据本发明的具有图案化的应变层以及应变引入层的SOI结构的框图。
图12图示了根据本发明的制造具有应变引入层的集成电路的方法的流程图。
具体实施方式
现在详细参考所公开的发明的实施例，附图中图示了这些实施例的一个或多个示例。以解释本发明技术的方式提供各个示例，各个示例不用于限制本发明技术。实际上，对于本领域技术人员而言明显的是，可在不脱离本发明精神和范围的情况下对本发明技术做出修改和变化。例如，作为一个实施例的一部分而图示及描述的特征可与另一实施例一起使用，从而得到又一个其它实施例。因此，本发明主题覆盖所附权利要求及其等价形式的范围内的这些修改和变化。
本发明的实施例实现了具有改进的散热性能同时保持SOI结构所伴随有的有益器件电特性的SOI器件的制造。此外，可根据本发明通过对半导体行业最常用的制造工艺进行非常小的修改来制造具有前述优点的器件。这给出了与现有制造工艺兼容的巨大优势，从而避免了需要进行新型半导体方案所面临的几乎不可避免的固定生产成本投资。本发明实施例通过利用背侧处理、去除SOI掩埋绝缘层的部分、以及在SOI结构的背侧上沉积各种结构的散热层来实现这些结果。
可参考图2来描述根据本发明的SOI结构。如图2所示，有源层103布置在操纵晶圆107上。根据之前讨论的惯例，操纵晶圆107在有源层103上方。此外，有源层103在散热层200上方。散热层200是导热的并且是电绝缘的。可用来形成散热层200的材料包括：金刚石、类金刚石碳素、碳化硅、氧化铝、氮化铝、氧化铍、氮化铍、石墨烯（Graphene）、或类似碳纳米管的某种碳构成物。
为散热层200选择即电绝缘又导热的材料保留了SOI技术提供的有益电性能并极大地缓解了采用二氧化硅绝缘层的传统SOI器件所面临的散热问题。例如，300K下的纯人造金刚石的热导率大约为3300W/m·K，而氧化铍的热导率大约为260W/m·K。可与传统SOI结构中的不导热的二氧化硅层（如上所述，其热导率为1.4W/m·K）进行比较。当在此处以及所附权利要求中使用时，如果材料层的热导率大于50W/m·K，则该材料层具有高热导率。金刚石和氧化铍都提供了相对于传统SOI结构在散热方面超过100倍的改进。在本发明的具体实施例中，至少部分地去除绝缘层102，并且在沉积导热材料以形成导热层200之前沉积另一非常薄的绝缘层。极其薄的绝缘层提高了结构将热量从有源层103散发至导热材料层的能力。例如，所沉积的绝缘层可包括与原本的绝缘层材料相同的薄层。通过保持有源层103中的有源器件的电特性而不受传统SOI结构的不良散热特性的限制，实现了导热但不导电的材料的优点。
利用背侧处理制造图2所示的结构。由于SOI结构是从背侧操作的—不同于典型的SOI处理方法—无需针对其为有源层103提供稳定性或作为有源层103中的电路制造的适当基板的能力来选择用作散热层200的材料。这是因为，在制造电路的同时将原本的绝缘层—绝缘层102—作为基本层，并且操纵晶圆107在背侧处理期间提供了支撑。绝缘层102的去除通常是不期望的，这是因为绝缘层102和基板101为有源层103提供了机械支撑。没有处于适当位置的这些层的情况下对有源层103的进一步处理对于电路104来说是破坏性的。但是，该阶段添加操纵晶圆107实现了集成电路的附加处理。下文将详细描述用于背侧处理的方法。
背侧处理的另一优势是允许在半导体处理的后续阶段加入散热层200，继而允许使用原本不会采用的散热层200的材料。与传统方案不同，背侧处理允许在完成有源层103的半导体处理之后添加散热层200。半导体制造工艺的某些阶段要求超过1000℃的温度。某些材料不能承受这些温度，因此一般被认为不适合用作位于散热层200处的热扩散层。但是，背侧处理的使用允许为散热层200使用更脆弱的材料。
可参考图3来描述根据本发明的集成电路。在图3中，如SOI结构中常见的那样，在绝缘层102上布置有源层103。但是，已经在某些部分中挖掉了绝缘层102以形成由挖掉的绝缘区域300定义的图案。挖掉的绝缘区域不是必须是连续的，实际上，可以以各种方式图案化绝缘层102以暴露有源层103的不同部分。在图3中，已经将散热层200放置在集成电路的整个背部表面上，包括挖掉的绝缘区域300中。在本发明的具体实施例中，仅仅在挖掉的绝缘区域300中布置散热层200。在本发明的具体实施例中，图案化散热层200，并且仅仅在挖掉的绝缘区域300的一部分中布置散热层200。在图3中，通过完全去除挖掉的区域中的绝缘材料来显示挖掉的绝缘区域300。但是，在本发明的具体实施例中，挖掉的绝缘区域300可由残留的薄绝缘层组成。绝缘层的初始厚度通常处于100纳米（nm）到1000nm的范围内。薄绝缘层可处于5nm到100nm的范围内。但是，任何程度的减薄都将得到薄绝缘层。数量级为1nm的残留绝缘材料单层就能满足要求，尽管利用传统方法很难实现。任意减薄程度都构成在散热能力方面对原本的结构的改进。图3所示的结构可保持有源层103中的隔离器件所提供的改进的电性能，同时由于热量可横向地流过有源层103并通过较薄或去除了绝缘体处的散热层200散发出去而提供改进的散热。
去除绝缘层102的优点和缺点可通过挖掉的绝缘区域300的具体图案的形成来平衡。例如，挖掉的绝缘区域300可与有源层103中的金属布线的最底层共同延伸。如图3所示，挖掉的绝缘区域300与最低金属层301横向地共同延伸。在本发明的具体实施例中，挖掉的绝缘区域300暴露了最低金属层的特定部分。在本发明的具体实施例中，挖掉的绝缘区域300暴露整个最低金属层301。在本发明的具体实施例中，最低金属层301是用于有源层103中形成的电路的布线的最底层。该结构从平衡角度来说是非常有利的，即，金属线如果未布置在绝缘体上则总体上不会出现改变的电特性。此外，金属高度导热，并且金属布线通常链接至有源器件，从而使得这些金属线成为散热的高效通道。虽然有源层103中产生的极大量的热量是由有源器件产生的，但是热量将从这些有源器件散发至金属线中，并随后经由散热层200通过SOI结构的背面散发出去。该方案总体上优于通过金属线将热量向上引导并从SOI结构顶部引导出去，这是因为现代的电路具有大量金属线，从而背侧路径变成更加直接的出口通道。
可参考图4来描述根据本发明的另一绝缘体上半导体结构。图4所示的集成电路可用来描述挖掉的绝缘区域300的另一组图案，该图案为SOI结构提供了有利的散热能力。在图4中，具有晶体管栅极401的晶体管的沟道区域400处于绝缘层102的横向范围内。但是，由于挖掉的绝缘区域300与晶体管漏极402以及晶体管源极403共同横向延伸，所以挖掉的绝缘区域300暴露了晶体管漏极402以及晶体管源极403。在挖掉的绝缘区域300的暴露了晶体管漏极402以及晶体管源极403的多个部分中沉积了散热层200。挖掉的绝缘区域300的另一部分中暴露了金属接触404。在本发明的具体实施例中，金属接触404在电方面不是有效，而是用于提供散热通道。在本发明的具体实施例中，金属接触404可用作有源层103中的电路的电接触。例如，金属接触404可以是信号线路，用于将信息信号带出有源层103中电路，以便另一系统使用。在另一示例中，金属接触404可以是有源层103中的电路的接地线或电源线。在本发明的具体实施例中，凸块金属处理将凸块金属沉积在图4所示的SOI结构上，从而金属接触404成为用于SOI结构的凸块金属连接器。在金属接触404在电方面不是有效的上述实施例中，金属接触404并非必须是金属，而是可以是具有良好导热性的任何材料。在本发明的具体实施例中，这些金属接触是金属柱接触。金属柱接触可以由金或铜构成。这些材料相对于焊锡凸块表现更好，这是因为与焊锡相比它们是更好的热传导器。在本发明的具体实施例中，金属接触404实现了对电路板的附接。在本发明的具体实施例中，金属接触实现了对低温共烧陶瓷基板、模块板、集成电路、凸块金属、金凸块金属、铜柱、金柱、以及任意金属连接的附接。
在本发明的具体实施例中，挖掉的绝缘区域300可与有源层103中的有源器件的部分共同横向延伸。如图4所示，这些实施例包括晶体管漏极402以及晶体管源极403的暴露，同时保持晶体管沟道400被绝缘层102覆盖。这种实施例展现出了具有隔离的沟道区域同时允许高度靠近的散热通道的有利方面。由于沟道400仍被绝缘层102覆盖，所以晶体管的电特性得到保持。晶体管将展现小的泄漏电流和基本电容、以及更受控的阈值电压。并且，由于晶体管的源极和漏极直接邻接着晶体管沟道，所以存在到达散热层200的直接通道。在本发明的其它实施例中，挖掉的绝缘区域300仅仅暴露SOI结构中的有源器件的一个子集。在本发明的其它实施例中，挖掉的绝缘区域300将暴露SOI结构中的分开的有源器件的区域的其它子集。
在本发明的具体实施例中，金属接触404布置在挖掉的绝缘区域300的第一部分中。此外，散热层200布置在挖掉的绝缘区域300的第二部分中，并且布置在金属接触404的一侧。图4可以看出这种结构。热量将能过金属接触404直接从有源层103散发出去。此外，热量将能够横向流过散热层200并通过金属接触404流出。虽然图4显示了该实施例与其中挖掉的绝缘区域300被图案化成对应于有源层103的区域的实施例的结合，但是这些实施例可单独地发挥功能。
上述参考使用挖掉的绝缘区域300来进行图案化散热层200与有源层103部分的对齐而讨论的任意实施例可单独使用或组合使用。此外，绝缘材料的图案去除以形成挖掉的绝缘区域300可与散热层200的图案化沉积组合。例如，散热层200可布置在SOI结构的整个背侧上，仅仅沉积在挖掉的绝缘区域300中，或沉积在挖掉的绝缘区域300的一部分中。下面将讨论形成散热层200的图案的方法。
其中挖掉的绝缘区域300单独地或与散热层200一起被图案化的本发明的实施例展现了有利特征。虽然散热层200是电绝缘的，但是存在由于将原本的绝缘材料放在某些区域后面而得到的某些优势。例如，散热层200可包括相比原本的氧化物不那么电绝缘的材料。可选择材料来使成本最小以及热导率最大（以其电绝缘能力为代价）。在有源层103的导电性很重要的部分中，可留下绝缘体而将挖掉的绝缘区域300放在别处。这样，图案化实现了为散热层200选择最佳材料方面的另一自由度。
图案化挖掉的绝缘区域300提供的另一优点在于限制了有源层103中界面状态的产生。即使散热层200是良好的电绝缘体，原本的绝缘体总体上更好地与有源层103进行物理接触，这是因为原本的绝缘体的去除导致了将在涂覆散热层200时重新连接的自由键的产生。这导致了可对有源层103中的电路造成问题的界面状态的产生。图案化挖掉的绝缘区域300可通过允许原本的绝缘体保持与有源层103中的关键区域的接触有利地限制有源层103中的这些关键区域中的这些界面状态的产生。
可参考图5来描述根据本发明的另一SOI结构。根据之前讨论的惯例，图5图示了操作晶圆107下的有源层103。如参考本发明其它实施例讨论的那样，已经通过背侧处理从有源层103底部去除了绝缘层102和基板101。在本发明的具体实施例中，操作晶圆107通过临时接合而接合至有源层103。这意味着可在半导体处理的后续阶段很容易地解除该接合。在本发明的具体实施例中，永久的第二操纵晶圆—示出为永久操纵散热层500和永久操纵基板层501—在背侧处理期间直接接合至有源层103。在本发明的具体实施例中，永久操纵基板层501由与永久操纵散热层500相同的材料构成。该结构可实现与之前提到的实施例的散热能力相当的散热能力水平，但是还有利地允许利用传统技术来顶侧接合至有源层103中的电路。由于操纵晶圆107是通过临时接合而接合的，所以可以在不再需要其在背侧处理期间所提供的支撑之后去除该操纵晶圆。此后，有源层103的顶侧曝光以实现顶侧接合以及各种其它应用。
可参考图6来描述根据本发明的另一SOI结构。图6图示了本发明的一个具体实施例，其组合了图案化的绝缘层以及参考图5描述的背侧永久操纵。在本发明的具体实施例中，在提供了散热层200之后，将永久操纵基板层501和永久操纵散热层500布置在SOI结构的背侧。在本发明的具体实施例中，用作永久操纵散热层500的材料可与用作散热层200的材料相同。可通过溅射和其它方法涂覆散热层200和500。如之前所述的那样，散热层200布置在通过绝缘层102的图案化形成的挖掉的氧化区域中。与之前描述的本发明具体实施例一样，图6所示的具体实施例显示了绝缘层102被图案化成暴露最低金属层301。实际上，上述所有图案化以及散热层变化可与参考图5描述的永久操纵组合，从而产生本发明的有利的散热特性和电特性的另一实施例。这些实施例具有能够前侧接合至有源层103中的电路的附加有益特征。
可参考图7来描述根据本发明的制造集成电路的方法。在本发明的具体实施例中，制造集成电路的方法在步骤700中以用于处理的SOI晶圆的制备开始。该步骤可包括对由二氧化硅绝缘体上的有源硅层组成的SOI晶片的实际制造，例如利用SIMOX或注入和切割方法制造。该步骤还可包括购买预先制造的SOI晶圆及其用于进一步处理的准备。
在本发明的具体实施例中，步骤700中SOI晶圆的制备之后是在步骤701中形成SOI晶圆的有源层中的有源电路。在该步骤及该层中形成的电路可包括但不限于诸如CMOS、BiCMOS、SiGe、GaAs、InGaAs以及GaN之类的技术。电路可包括：诸如二极管和晶体管之类的各种有源器件，诸如电阻器、电容器和电感器之类的无源器件，以及诸如金属线路和通孔之类的路径电路。可执行各种平版印刷的和化学的沉积步骤以形成该电路。
在本发明的具体实施例中，步骤701中形成有源电路之后是SOI晶圆的背侧处理。在本发明的具体实施例中，背侧处理开始于在步骤702中将第二操纵晶圆附接或永远接合至有源层上的SOI晶圆。用于引入对操纵晶圆的永久接合的处理包括：永久的有机或无机粘合剂、氧化物烧结接合、流电接合（galvanic bonding）、融合分子接合、任何形式的电磁接合、以及其它产生永久晶圆接合的其它已知方法。
在操纵晶圆永久接合至SOI结构之后，可在步骤703中去除SOI晶圆基板。独立地或者组合地利用机械和化学手段去除基板。例如，机械研磨可用来将基板材料从大约800微米（μm）的原始厚度减薄成大约20μm。如果基板是硅，则可利用诸如KOH或TMAH之类的湿法刻蚀来去除基板材料的最后厚度。还可利用干法等离子体刻蚀来去除基板材料的最后厚度。可以以高精度或高刻蚀速率比去除基板。刻蚀速率比指的是从晶圆背面去除的期望基板材料的速度与本来不应该去除却被去除的其它材料的速度之比。在本发明的具体实施例中，绝缘层是起到刻蚀停止作用的掩埋的氧化物，这是因为对于到掩埋的氧化物为止的所有基板的去除，刻蚀速率比可能极其高。
在本发明的具体实施例中，在步骤703中去除SOI晶圆基板之后是可形成之前公开的任意结构的进一步的背侧处理。在本发明的具体实施例中，去除SOI晶圆基板之后是在步骤704中去除SOI绝缘层以形成挖掉的绝缘区域。如上所述，绝缘层可总体去除、仅仅整体减薄从而比原始厚度薄、或者以挖掉的绝缘层形成上述多个图案中的任意图案的方式去除。可利用标准的平版印刷技术或选择性化学气相沉积来形成这些图案。必须小心地减薄绝缘层以避免损坏有源层。虽然仅仅需要单层绝缘材料——1nm的数量级，但是减薄可能受限于原始绝缘体的均匀性。例如，如果原始层起始地具有大于5nm的偏差，则用于绝缘体去除的传统方法可能不能留下小于5nm的最终层。此外，这些图案可配置成获取屏蔽有源层中的电路的程度以及所得到SOI结构有效散热的程度的有利折中。
在本发明的具体实施例中，在步骤704中从SOI晶圆背侧去除SOI绝缘材料之后是在步骤705中在挖掉的绝缘区域中将散热层沉积在SOI晶圆背侧。该散热层的沉积可执行来产生之前描述的任意结构。否则，该步骤可直接跟在基板材料的去除之后。此外，该步骤可在金属接触的沉积过程中执行（其中例如在两个或者更多步骤中布置金属接触），或者在金属接触的沉积之后执行（如果之后在散热层中开凿开口以暴露用于电接触的金属接触）。可通过化学气相沉积、溅射、或其它方法实现步骤705中散热层的添加。此外，可通过利用标准的平版印刷技术或选择性化学气相沉积来实现根据之前公开的结构的散热层的图案化沉积。如上所述，在本发明的具体实施例中，该步骤中沉积的散热层是电绝缘的并导热。
在本发明的具体实施例中，步骤705中将散热层沉积在SOI晶圆背侧之后是钝化SOI晶圆的背面的界面状态。在其中步骤704中去除了整个绝缘层的实施例中，这可能是非常有利的，这是因为步骤705中沉积的散热层很可能具有高界面状态密度。沉积的薄膜可能具有高界面状态密度，除非它们在高于800℃的高温下退火。由于该温度高于有源电路已经显影之后标准晶圆可操纵的温度，该节处的高温退火不是种选择。但是，可利用低温退火来钝化界面状态。在本发明的具体实施例中，该低温退火在400-450℃的温度范围内进行并且在纯氢气或混合气体的含氢气氛中完成。混合气体是不爆炸的N2和H2的混合物。钝化步骤可产生比原本可实现的散热层薄的散热层。例如，利用传统化学气相沉积设备或溅射设备，该层可以是5nm至20nm厚，并且具有大约+/-5%的均匀度。因此，该步骤允许非常薄的绝缘层的沉积，因此是非常有效的对有源层的热导。在这些实施例中，散热层可包括有效布置的绝缘材料层，其提高了SOI结构的散热性能。在本发明的具体实施例中，高度导热的材料的层沉积在该绝缘材料薄层的背面，并且散热层包括该绝缘材料薄层以及导热材料层。
在本发明的具体实施例中，在步骤704中去除整个SOI绝缘层之后是沉积与步骤704中去除的材料相同的绝缘材料的薄层，随后进行如前一段所述的低温退火钝化步骤。例如，去除的绝缘材料可能是二氧化硅，并且低温退火的材料也可能是二氧化硅。二氧化硅是优选使用的材料，这是因为其具有低界面状态特征。二氧化硅可去除并随后沉积的原因是，沉积及低温退火的工艺可产生比通过利用上述公开的方法部分地回蚀原始层而实现的层更均匀且更薄的绝缘材料层。
在本发明的具体实施例中，步骤705中将散热层沉积在SOI晶圆背侧之后是去除选中区域中的散热层以允许在后续处理期间对有源层中的有源电路进行电接触。在一个实施例中，散热层的部分的挖掉可定位在表现为暴露用于金属接触的金属的最低金属层部分。可选地，可选择性地去除有源硅区域下的散热层，以允许对有源结构的直接接触。除了散热层之外，可能要求其它介电层来暴露用于电接触的各种连接器。可利用公知的平版印刷技术和利用化学剂的干法或湿法刻蚀方式选择性地完成散热层的去除。
在本发明的具体实施例中，从SOI晶圆背侧去除散热层区域之后是在步骤706中沉积金属接触。这些金属接触沉积在步骤704或步骤705中形成的挖掉的绝缘区域的第一部分中。这些金属接触能够快速地从有源电路散热。在本发明的具体实施例中，金属接触可提供用于从有源电路散热的热通道、以及用于通向外部装置的信号或电源连接的接触。金属接触可包括球焊、焊锡凸块、铜柱、或其它裸片接触材料。金属接触还可配置成附接至电路板、或低温共烧陶瓷基板。由此，该步骤产生的结构在结构底侧具有与SOI结构的有源层的接触，这与标准SOI是反向的。
可参考图8来描述根据本发明的制造集成电路的方法。在本发明的具体实施例中，制造集成电路的方法在步骤800中以用于处理的SOI晶圆的制备开始，并在步骤801中继续在SOI结构的有源层中形成电路。步骤800和步骤801可分别参考之前描述的步骤700和步骤701来执行。步骤802可包括将操纵晶圆接合至SOI结构的有源层的顶侧。操纵晶圆可暂时接合至有源层。用来引入暂时接合至操纵晶圆的工艺包括诸如Brewer Science公司的HT10.10、3M公司的WSS（晶圆支撑系统）、HD Micro聚酰亚胺以及TMAT之类的粘合剂。在这点上，因此，有源电路可夹在两个绝缘层之间。可选地，操纵晶圆可包括导电的或半导的材料。在步骤802中暂时接合操纵晶圆之后，可如之前在步骤703、步骤704和步骤705中描述的那样分别执行步骤803、步骤804和步骤805。
在本发明的具体实施例中，步骤805中沉积散热层之后是在，步骤806中将永久的第二操纵晶圆在有源层下方附接或永久接合至SOI结构。该背侧处理的效果是改变可对SOI结构的有源电路制造接触的方向。一旦该第二操纵晶圆永久地接合至SOI结构背侧，则由于原始的操纵晶圆是利用暂时的容易反转的工艺接合的，所以可在步骤807中很容易地去除原始的操纵晶圆。用于引入对顶侧操纵晶圆的永久接合的处理包括：永久的有机或无机粘合剂、氧化物烧结接合、流电接合、融合分子接合、任何形式的电磁接合、以及其它产生永久晶圆接合的其它已知方法。诸如融合分子接合之类的接合方法可能要求将被接合的两个表面的高度平坦性。如果选择性去除绝缘材料，则可能使晶圆表面产生不平坦，这就使得接合变得更加困难。在这种情况下，化学机械抛光可用来在接合步骤之前使得晶圆表面变得平坦，从而改进接合效力。
步骤806产生的结构使SOI结构的有源层在其顶侧暴露，并且进一步的处理实现了从顶侧直接连接有源电路。在步骤806接合的永久的第二操纵晶圆可完全由电绝缘但导热的材料构成。此外，第二操纵晶圆可由沉积在基板材料上的材料构成。第二结构可节省成本，这是因为基板材料将提供最终SOI结构的必要稳定性，而无需使用非常昂贵的导热材料那么多。的永久的第二操纵晶圆上的导热材料可由在步骤805中沉积以形成散热层的材料相同的材料构成。可选地，步骤806中接合的永久的操纵晶圆可由导电材料或半导材料构成，例如硅或者高阻硅。
背侧应变引入层
本发明实施例实现了SOI结构中的有源器件的产生，该SOI结构具有与其沟道接近的应变引入材料。本发明实施例允许在器件制造工艺的比涂覆应变引入层的通常阶段早的阶段引入应变引入材料。这实现了应变引入层的效率的提高，同时降低了间歇性制造阶段期间对SOI结构的损害。此外，可根据本发明通过对半导体行业最常用的制造工艺进行非常小的修改来制造具有前述优点的器件。这给出了与现有制造工艺兼容的巨大优势，从而避免了需要进行新型半导体方案所面临的几乎不可避免的固定生产成本投资。本发明实施例通过利用背侧处理、有可能去除SOI掩埋绝缘层的部分、以及在SOI结构的背侧上沉积各种结构的应变引入层来实现这些结果。
包括有源器件的沟道的材料中的机械的拉伸或压缩应变的引入增大了该有源器件中电荷载流子的移动性。总体上，引入拉伸应变增大了电子的移动性，引入压缩应变增大了空穴的移动性。因此，诸如n型金属氧化物半导体（NMOS）之类的n型有源器件在其沟道中引入了拉伸应变时将能够在更高的频率下工作，这是因为NMOS中的电荷载流子是电子。类似地，诸如p型金属氧化物半导体（PMOS）之类的p型有源器件在其沟道中引入了压缩应变时将能够在更高的频率下工作，这是因为NMOS中的电荷载流子是空穴。
可参考图9来描述根据本发明的SOI结构。图9图示了一种SOI结构，其中有源层103、绝缘层102以及基板的原始的SOI结构已经被附接至操纵晶圆107，并且已经经历了背侧处理以去除其基板。已经在有源层103中产生了电路，包括诸如NMOS900之类的n型有源器件以及诸如PMOS901之类的p型有源器件。此外，应变引入层902出现在绝缘层102的背面。
图9所示的结构相对于通常在半导体器件中引入应变的方案具有某些优势。器件中的应力可造成伴随其所产生的优点的诸如晶圆翘曲之类的问题，因此希望尽可能具体地限制及标的出半导体结构中所引入的应力的总量。由于应变引入层的效力随着将要应变的区域与应变区域之间的距离的减小而增大，所以在实现与通过将应变引入层尽可能靠近有源器件的沟道放置所实现的沟道应变相同的有益沟道应变的同时，限制在半导体中引入的总应变。从顶侧处理制造工艺来说这是有问题的，因为通常需要先沉积最底层。由此，应变引入层一般沉积在FET器件的栅极上，因此与沟道相距甚远。并且，栅极的图案化造成了应变引入层中的不平坦性，从而使得应变引入层的效果取决于诸如FET器件的长度和宽度之类的几何效果。此外，半导体器件在沉积应变层（涉及600-1050℃范围内的相当高的温度）之后经历进一步的处理步骤。这种必要性对半导体器件具有两种削弱效果。首先，应变引入层所引入的应变会在高温退火期间削弱，这与应变引入层的总体愿望是相反的。其次，应变引入层可造成有源层的塑性变形以及晶圆翘曲，这将造成诸如滑移和位错产生之类的硅晶缺陷，这些情况显著地降低了所得到的器件的电性能及成品率。相反，根据本发明利用背侧处理引入应变引入层允许在有源层已经完全处理完之后以紧密接触有源器件的沟道的方式沉积应变引入层，从而避免了与早期阶段引入的应力有关的问题。
在本发明的具体实施例中，可利用平版印刷工艺或能实现应变引入层的图案化沉积的其它制造方法（例如参考图11描述的那些方法）来提供应变引入层。图9图示了其中已经使应变引入层902形成图案从而包括拉伸应变层903和压缩应变层904的具体实施例。在本发明的具体实施例中，可利用会在有源层103上产生拉伸应力或压缩应力的不同材料来形成应变引入层902的这两个部分。可引入拉伸应变的材料包括氮化硅、以及氮化铝。可引入压缩应变的材料包括氮化硅、氮化铝以及类金刚石碳素。根据材料沉积的条件，相同的材料可引入压缩或者拉伸应变。在本发明的具体实施例中，可通过在不同条件下沉积相同材料来形成应变引入层902的这两个部分。可应用多种材料，其中通过调制沉积条件来控制材料的应变引入特性。例如，利用化学气相沉积在不同条件下沉积的氮化硅或氮化铝可产生拉伸的或压缩的应变。在本发明的具体实施例中，可在具有诸如NMOS900之类的n型有源器件的SOI结构上沉积拉伸应变层903，可在具有诸如PMOS901之类的p型有源器件的SOI结构上沉积拉压缩变层904。从而，两种器件的载流子移动性都有效地提高。
在本发明的具体实施例中，在背侧处理期间将均匀的应变引入层沉积在SOI结构的底部。这些实施例在具体载流子类型的有源器件在有源层103的电路中占主导地位的情况下特别有用。例如，如果有源层103中的有源器件主要是NMOS晶体管，则可在SOI结构的背侧提供均匀的拉伸应变层。从而，可改善NMOS晶体管，并且更多数量的NMOS晶体管的改进所提供优势胜过对任意PMOS晶体管中的载流子的移动性的潜在削弱变化。
在本发明的具体实施例中，一个或多个应变引入层可直接布置在有源层103的背侧。这可以通过在沉积应变引入层902之前去除绝缘层102的附加背侧处理步骤来实现。这些实施例共有允许在半导体器件处理序列的后期阶段沉积应变引入层的有益特征。但是，在一些实施例中，应变引入层更靠近有源层103。因此，需要更小的总体应力，这提高了所得到的半导体器件的电特性以及产率，同时提高了其有源器件的沟道中的电荷载流子的移动性。在本发明的具体实施例中，当应变引入层902直接沉积在有源层103上时，应变引入层902由电绝缘材料制成，从而保持SOI结构的有益电特性。引入应变并作为电绝缘体的材料包括氮化硅、氮化铝、碳化硅以及类金刚石。
在本发明的具体实施例中，提供不同图案来在有源层103中引入应变。这些图案可在与电荷载流子的流动平行或垂直的方向上产生二轴向应变或单轴向应变。可通过应用如上所述的多个至少部分地共同垂直延伸的应变引入层来形成这些图案。类似地，可通过应用如上所述的沉积在挖掉的绝缘区域中的应变引入层来形成这些图案。可参考图10来描述可引入拉伸或压缩应变的各种图案。栅极1000被应变引入层1001围绕。如果应变引入层1001是拉伸应力引入层，则该图案将在栅极1000下的沟道中产生二轴向拉伸应变。如果应变引入层1001是压缩应变引入层，则该图案将在栅极1000下的沟道中产生二轴向压缩应变。栅极1010被应变引入层1011围绕。栅极1010具有大的宽长比。这样，应变引入层1011的应用将降低栅极1010下的沟道中的占主导的与电荷载流子流经沟道的方向平行的拉伸或压缩的（取决于应变引入层1011对应于压缩还是拉伸）单轴向应变。栅极1020处于应变引入层1021上方。该图案将在栅极1020下的沟道中引入单轴向应变，该单轴向应变与电荷载流子流经沟道的方向垂直，并且根据应变引入层1021对应于压缩还是拉伸而相应地是压缩或拉伸的。最后，栅极1030被应变引入层1031围绕。该图案的效果是，如果为应变引入层1031和1011采用相同类型的材料，则产生与层1011所引入的应变相反的应变。例如，如果应变引入层1031是拉伸引入型的，则在栅极1030下的沟道中引入压缩应变。类似地，如果应变引入层1031是压缩型的，则在栅极1030下的沟道中引入拉伸应变。
可参考图11来描述根据本发明的SOI结构。图11图示了包括有源层103的SOI结构，其中已经根据特定图案去除了绝缘层102以形成挖掉的绝缘区域300，并且在有源层103中产生期望的应变力分布。在本发明的具体实施例中，可利用用于所有应变引入层902的相同的材料在有源层103中引入拉伸和压缩应变。如之前参考图10描述的那样，相同的材料可用于应变引入层1011和1031以在栅极1010和1030下的沟道中引入相反类型的应变。如图11所示，挖掉的绝缘区域300可暴露诸如NMOS900之类的n型有源器件的沟道，并且围绕诸如PMOS901之类的p型有源器件的沟道图案化。在这种情况下，应变引入层902可以是一个均匀的拉伸应变引入层，其可与挖掉的绝缘区域300合作来提高NMOS900中的带女子以及PMOS901中空穴的移动性。在本发明的具体实施例中，图案的极性以及所沉积的材料的应变类型与之前描述的实施例相比可交换，并且可得到同样的双重改进效果。
在本发明的具体实施例中，挖掉的绝缘区域300可形成为仅仅暴露有源层103中的有源器件的一个子集。例如，以仅仅暴露诸如NMOS900之类的n型有源器件的沟道的图案来去除挖掉的绝缘区域300，随后在SOI结构的背面沉积拉伸应变引入层。类似地，在本发明的具体实施例中，与之前描述的实施例相比，图案的极性以及所沉积的材料的应变类型可互换。在本发明的具体实施例中，剩余绝缘区域下的应变进入层可通过刻蚀处理去除。虽然在这些实施例中仅仅一种类型的器件会发生应变，但是这仍能产生有利性能，尤其是在更着重地取决于某种类型的半导体材料的性能的设计中。
在本发明的具体实施例中，与SOI结构背侧接触的在有源层中引入应变的材料还作为散热层。这样，本说明书的第一部分中的任何散热层可由额外地引入应变的层所代替。此外，该实施例与其中应变引入层被图案化来与诸如有源器件的沟道之类的热源接触的这些实施例的结合可产生有利结果。在具体实施例中，应变引入层将沉积在有源器件的沟道上，并且还以标准绝缘层对于SOI结构的方式隔离器件。可通过隔离、导热以及应变引入提供这些有利特征的材料包括：氮化铝、碳化硅、以及类金刚石碳素。在本发明的具体实施例中，绝缘层102可完全去除，并且由图案化的热传播层代替，该热传播层可在散热的同时提供参考图10时描述的用于应变引入层的图案。
可参考图12来描述根据本发明的制造集成电路的方法。在步骤1200，利用背侧处理从SOI结构的背面去除基本。在本发明的具体实施例中，SOI结构已经经历了大量处理从而几乎完成了SOI结构的有源层中的电路。用于在步骤1200中去除基板的方法与参考图7步骤703所描述的这些方法相同。在本发明的具体实施例中，步骤1200之后是在步骤1203中在SOI结构的背侧沉积应变引入层。所沉积的应变引入层可通过溅射、化学气相沉积或任意其它方法沉积在整个SOI结构背部表面。应变引入层可包括压缩或拉伸的应变。并且，可利用平版印刷或一些其它方法来图案化所沉积的层，从而在步骤1203沉积第一部分中的第一应变层，随后在步骤1205沉积另一应变层。在这种情况下，可形成可能具有拉伸引入部分和压缩引入部分的多部分的应变引入层。在本发明的具体实施例中，实际上可利用与步骤1203和1205相同的材料以及针对这两个步骤的不同处理条件来形成该多部分的应变引入层。如上所述，诸如氮化硅之类的材料根据涂覆它们时的条件而显示出拉伸或压缩的应力。
在本发明的具体实施例中，步骤1200中去除基板材料之后是在步骤1201中去除绝缘材料。该去除可包含参考图7的步骤704描述的任意方法。在本发明的具体实施例中，步骤1201之后可以是在步骤1202中沉积散热层。该沉积可包含参考图7的步骤705和706描述的任意方法。在本发明的具体实施例中，步骤1201之后可以由步骤1203中应变引入层的沉积代替。在本发明的其中应变引入层和散热层是同一个的具体实施例中，这两个步骤没有区别。在本发明的具体实施例中，步骤1201中的绝缘层去除可从SOI结构背面完全去除绝缘材料。如果该步骤之后是应变层1203的沉积，则所得到的SOI结构将包括直接沉积在有源层背面上的应变层。
在本发明的具体实施例中，步骤1201的绝缘层去除可如上所述的那样去除特定图案中的绝缘材料。其后可以是在步骤1203中沉积应变层，从而使得应变层沉积在步骤1201中形成的挖掉的绝缘区域中。例如，可仅仅去除电路的其上可能引入应变的部分下（例如仅仅n型器件下）的绝缘材料。在这种情况下，应变引入层可以是拉伸的，并且仅仅n型器件被有利地应变，而p型器件处于正常状态。作为另一示例，绝缘材料留在n型器件沟道下，并且在p型器件沟道下处于相应的负图案，从而单个应变引入层可在有源层上按需产生拉伸以及压缩应变。步骤1201中的绝缘材料的图案化去除之后还可以依次是步骤1203和1205，用于如上所述地在挖掉的绝缘区域的不同部分沉积不同类型的应变引入层。
在本发明的具体实施例中，步骤1203中在SOI结构的背侧沉积应变引入层之后是在步骤1204中的对所沉积的应变引入层的部分的图案化去除。该步骤将因此形成挖掉的应变层区域。在步骤1205中，在SOI结构背侧上沉积第二应变层。由此，该第二应变层将填充该挖掉的应变层区域。在步骤1206中，未填充挖掉的应变层区域的其它应变层可被去除以形成SOI结构的均匀背部背面。该方案与其它实施例相比具有一些有利方案，这是因为仅仅步骤1204中的应变层的去除需要图案化。步骤1206中的第二应变层的去除可包括机械研磨至均匀水平或者由第一和第二应变层的化学组合物中的不同所辅助的刻蚀。此外，应变引入层的实际沉积可在步骤1203和1205中统一。考虑到一些形式的沉积（例如化学气相沉积）并非总是适合具体的平版印刷图案化，所以该方案中以更有效的方式实现具体的图案化方面是有利的。
虽然已经参考本发明的具体实施例主要讨论了本发明的实施例，但是其它变化也是可行的。所描述的系统的各种结构可用来代替或添加至此处所呈现的结构。例如，虽然一般参考硅基板和氧化物绝缘层来讨论器件，但是对于任意形式的绝缘体上半导体晶圆、结构或器件，本发明也可以发挥效力。例如，本发明可与蓝宝石上硅（silicon-on-sapphire）结构组合使用。此外，本发明在电路采用诸如CMOS、二极管、BiCMOS、SiGe、Ga、As、InGaAs、GaN以及任意其它半导体技术或复合半导体技术的形式之类的技术形式时也可发挥效力或工作。如上所述，绝缘层无需完全去除。该绝缘层可原封不动，这样可在绝缘层的表面上布置散热层。此外，可对整个绝缘层进行减薄，而不是完全去除，或者可形成包括残留的减薄后的绝缘层的挖掉的绝缘区域。而且，本文提到的这些层之间可布置其它层或材料。半导体处理是非常复杂的领域，并且仅仅在明确地需要层来描述本发明以避免混淆时提及这些层。例如，有源层上可布置钝化层以防止电路与其环境反应。此外，词语“层”的使用（例如在描述有源层或绝缘层时）不排除该层由多种材料组成。例如，除了SOI结构的整个有源层下方的二氧化硅绝缘体之外，有源层中的金属线路下方可能存在玻璃层、或一些其它绝缘体。但是，术语绝缘层可覆盖整个玻璃结构以及二氧化硅绝缘体。
本领域技术人员可以理解的是，前述描述仅仅作为示例，而不是用于限制本发明。公开文本中的没有表示本发明限于需要具体形式的半导体处理或集成电路的系统。根据需要，可通过硬件或软件执行功能。总体上，所显示的示图仅仅用于表示一种可能的结构，多种变化是可行的。本领域技术人员可以理解的是，与本发明一致的方法和系统适合于在更宽范围的应用中使用，包括与电子或光电器件的散热相关的任何应用。
虽然已经参考本发明的具体实施例详细描述了说明书，但是本领域技术人员可以理解的是，在得到了上述理解之后，本领域技术人员可以很容易地构想出对这些实施例的替换、改变和等价形式。本领域技术人员可以在不脱离所附权利要求中更具体地阐述的本发明精神和范围的情况下实施对本发明的这些和其它修改和变化。

Claims (17)

1.一种绝缘体上半导体，包括：
散热层；
位于所述散热层上方的有源层；
位于所述有源层上方的操纵晶圆；以及
绝缘层，其至少部分地与所述散热层共同垂直延伸；
其中所述散热层具有高热导率并且电绝缘，
其中所述有源层沉积在所述绝缘层上；
其中所述绝缘层包括挖掉的绝缘区域；
其中所述散热层沉积在所述挖掉的绝缘区域中；
其中所述挖掉的绝缘区域的第一部分与所述有源区中的有源器件的一部分横向地共同延伸；以及
其中所述有源器件的沟道区域处于所述挖掉的绝缘区域的横向范围之外。
2.根据权利要求1所述的绝缘体上半导体，进一步包括：
位于所述散热层下方的第二操纵晶圆，所述第二操纵晶圆具有处于基板层上的第二散热层；
其中所述操纵晶圆通过暂时接合而接合至所述有源层。
3.根据权利要求1所述的绝缘体上半导体，进一步包括：
布置在所述挖掉的绝缘区域的第一部分中的金属接触；
其中所述散热层布置在所述挖掉的绝缘区域的第二部分中，并且所述散热层布置在所述金属接触的一侧；以及
其中所述金属接触被配置成作为用于所述有源层中的电路的电接触。
4.根据权利要求1所述的绝缘体上半导体，其中所述挖掉的绝缘区域与所述有源区中的最低金属布线层横向地共同延伸。
5.根据权利要求1所述的绝缘体上半导体，进一步包括：
布置在所述挖掉的绝缘区域的第二部分中的金属接触；
其中所述散热层布置在所述挖掉的绝缘区域的第一部分中，并且所述散热层布置在所述金属接触的一侧；以及
其中所述金属接触被配置成作为用于所述有源层中的电路的电接触。
6.根据权利要求5述的绝缘体上半导体，其中：
所述金属接触包括金属柱接触；以及
所述金属接触被配置成从所述电路向所附接的电路板传递信息信号。
7.一种从绝缘体上半导体器件散热的方法，包括步骤：
横向跨越绝缘层的顶部表面将热量传导通过有源层；以及
将来自所述绝缘层的热量散发通过散热层；
其中所述有源层位于所述散热层上方；
其中所述绝缘层位于所述有源层下方，所述绝缘层至少部分地与所述散热层共同垂直延伸，并且所述绝缘层包括挖掉的绝缘区域；以及
其中所述散热层具有高热导率并电绝缘，并且所述散热层位于所述挖掉的绝缘区域中，
其中：
所述挖掉的绝缘区域的第一部分与所述有源层中的有源器件的一部分共同横向延伸；以及
所述有源器件的沟道区域处于所述挖掉的绝缘区域的横向范围之外。
8.根据权利要求7所述的方法，进一步包括步骤：
将热量横向通过所述散热层引导至金属接触；以及
将来自所述散热层的热量通过所述金属接触散发；
其中所述金属接触布置在所述挖掉的绝缘区域的第二部分中，并且所述金属接触被配置成作为用于所述有源层中的电路的电接触；以及
其中所述散热层位于所述挖掉的绝缘区域的第一部分中，并且所述散热层位于所述金属接触的一侧。
9.一种制造集成电路的方法，包括步骤：
在绝缘体上半导体晶圆的有源层中形成有源电路；
从布置在所述绝缘体上半导体晶圆背侧的基板层去除基板材料；
从所述绝缘体上半导体绝缘的所述背侧去除绝缘材料以形成挖掉的绝缘区域；以及
在所述挖掉的绝缘区域中沉积散热层；
其中所述散热层是电绝缘的，
其中所述挖掉的绝缘区域的第一部分与所述有源区中的有源器件的一部分横向地共同延伸，
其中绝缘材料的剩余部分与所述有源器件的沟道区域横向地共同延伸。
10.根据权利要求9所述的方法，进一步包括步骤：
通过使用低温热退火钝化一种界面状态，所述界面状态组是在去除所述绝缘材料期间形成的；
其中所述散热层由所述绝缘材料层组成。
11.根据权利要求9所述的方法，其中所述散热层具有高热导率。
12.根据权利要求11所述的方法，其中所述挖掉的绝缘区域与所述绝缘体上硅晶圆的整个背部表面横向地共同延伸。
13.根据权利要求11所述的方法，进一步包括步骤：
在所述挖掉的绝缘区域的第一部分中沉积金属接触；
其中所述散热层布置在所述挖掉的绝缘区域的第二部分中，并且所述散热层布置在所述金属接触的一侧；以及
其中所述金属接触被配置成作为用于所述有源层中的电路的电接触。
14.根据权利要求11所述的方法，其中所述挖掉的绝缘区域与所述有源区中的最低金属布线层横向地共同延伸。
15.根据权利要求11所述的方法，进一步包括步骤：
将操纵晶圆临时接合至所述有源层的顶侧；以及
将第二操纵晶圆永久地接合至所述有源层下方的所述绝缘体上硅晶圆；
其中所述第二操纵晶圆具有基板层上方的第二散热层。
16.根据权利要求9所述的方法，进一步包括步骤：
在所述挖掉的绝缘区域的第二部分中沉积金属接触；
其中所述散热层布置在所述挖掉的绝缘区域的第一部分中，并且所述散热层布置在所述金属接触的一侧；以及
其中所述金属接触被配置成作为用于所述有源层中的电路的电接触。
17.根据权利要求16所述的方法，进一步包括步骤：
将所述集成电路配置成附接至电路板；
其中所述金属接触包括金属柱接触；以及
其中所述电接触被配置成从所述有源电路向所述电路板传递信息信号。
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