JP6328852B2 - 裏側ひずみトポロジーを有するセミコンダクタオンインシュレータ - Google Patents
裏側ひずみトポロジーを有するセミコンダクタオンインシュレータ Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7849—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being provided under the channel
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
本特許出願は、2014年11月13日に出願された米国特許出願第14/540,268号の優先権を主張するものであり、その内容が参照により本明細書に組み込まれる。
本発明の実施形態は、それらのチャネルに密着するひずみ誘起材料を有するSOI構造における能動デバイスの生産を提供する。本発明の実施形態は、ひずみ誘起層が適用される通常の段階よりもデバイス製作プロセスでの後の段階において、そのようなひずみ誘起材料の導入を可能にする。このことは、断続的な製造段階中にSOI構造への損傷のリスクを同時に減らしながら、ひずみ誘起層の有効性を高めることを可能にする。加えて、上述の利点を有するデバイスは、半導体産業において最も頻繁に使用される製造プロセスをほとんど修正することなく、本発明に従って製造され得る。既存の製造プロセスとの互換性が、新規の半導体ソリューションに直面し得るほぼ克服できない一定の生産コスト投資に対する必要性を回避することを想定すると、このことは非常に大きい利点である。本発明の実施形態は、裏側処理、SOI絶縁体層の部分の可能な除去、およびSOI構造の裏側での様々な構成におけるひずみ誘起層の堆積を利用することを通じて、この成果を達成する。
ひずみ層と活性層103の中のデバイスとの相対配置が、デバイス性能に影響を及ぼす。層転写の後にウエハの裏側にひずみ層を配置することが、ひずみ層が上側部から能動デバイスを覆って上に重ねられる手法にまさる著しい利点をもたらすように、ひずみ層の活性層への近接度とともにひずみ層の効力が増大することが前に言及された。しかしながら、ひずみ層、ひずみ層がその上に堆積されるパターン、および活性層の間の相互作用は、単なる活性層とひずみ層との近接度以外の数多くのファクタによって影響を及ぼされる。
101 基板層
102 絶縁体層
103 活性層
104 回路機構
107 ハンドルウエハ
108 ハンドル基板
109 ハンドル絶縁体層
110 金属の層
200 熱放散層
300 掘削絶縁体領域
301 最も下の金属層
400 チャネル領域
401 トランジスタゲート
402 トランジスタドレイン
403 トランジスタソース
404 金属接点
500 ハンドル熱放散層
501 ハンドル基板層
900 NMOS
901 PMOS
902 ひずみ誘起層
903 引張ひずみ層
904 圧縮ひずみ層
1000 ゲート
1001 ひずみ誘起層
1010 ゲート
1011 ひずみ誘起層
1020 ゲート
1021 ひずみ誘起層
1030 ゲート
1031 ひずみ誘起層
1300 半導体構造断面図
1301 活性層
1302 パターン層
1303 ひずみ層
1304 能動デバイス
1306 チャネル領域
Claims (13)
- セミコンダクタオンインシュレータ(SOI)構造であって、
絶縁材料から作られたパターン層であって、掘削領域およびパターン領域からなるパターン層と、
前記パターン層の第1の面に配置されたひずみ層であって、前記掘削領域の中および前記パターン領域の上に配置されたひずみ層と、
前記パターン層の前記第1の面に対向する前記パターン層の第2の面に配置された活性層と、
前記活性層の中に形成された電界効果トランジスタであって、横方向に並んで配置されたソース、ドレイン、およびチャネルを備える電界効果トランジスタと、
前記パターン層に面している前記活性層の面とは反対の前記活性層の面に配置されたハンドル層とを備え、
前記チャネルが、前記ソースと前記ドレインとの間にあり、
前記チャネルが、前記横方向において前記パターン領域の範囲内に完全に包含されており、
前記ソースおよび前記ドレインがそれぞれ、前記横方向において前記パターン領域の範囲と部分的に重複しており、
前記ひずみ層が、前記チャネルのキャリア移動度を変化させる、
セミコンダクタオンインシュレータ構造。 - 前記パターン領域が、前記掘削領域の深さに等しい高さを有し、
前記ひずみ層が、前記パターン層と接触する第1の面、および前記第1の面に対向する第2の面を有し、
前記ひずみ層が、前記ひずみ層の前記第1の面と前記第2の面との間の厚さを有し、
前記ひずみ層の前記厚さに対する前記パターン領域の前記高さの比が、0.75〜1.5の範囲内にある、
請求項1に記載のセミコンダクタオンインシュレータ構造。 - 前記パターン層と前記活性層の両方と接触している、前記セミコンダクタオンインシュレータ構造の埋込み絶縁体をさらに備え、
前記埋込み絶縁体は、厚さが1ミクロンよりも薄く、
前記埋込み絶縁体は、前記パターン層と前記活性層との間に位置している、
請求項2に記載のセミコンダクタオンインシュレータ構造。 - 前記電界効果トランジスタから離れて位置している別のパターン領域であって、前記掘削領域は前記パターン領域と前記別のパターン領域とによって画定されている、別のパターン領域をさらに備え、
前記チャネルの中心から前記別のパターン領域までの前記横方向における寸法は、前記チャネルの前記横方向における寸法よりも10倍大きい、
請求項1に記載のセミコンダクタオンインシュレータ構造。 - 前記電界効果トランジスタの前記チャネルの前記横方向における寸法は1ミクロンよりも短く、
前記チャネルの中心から前記別のパターン領域までの前記横方向における寸法は、10ミクロンよりも大きい、
請求項4に記載のセミコンダクタオンインシュレータ構造。 - 前記セミコンダクタオンインシュレータ構造の埋込み絶縁体が前記パターン層に対応している、
請求項1に記載のセミコンダクタオンインシュレータ構造。 - 前記ひずみ層に隣接して形成された逆ひずみ層をさらに備え、
前記逆ひずみ層が、前記ひずみ層のひずみ力とは反対である反対のひずみ力を前記活性層に加える、
請求項6に記載のセミコンダクタオンインシュレータ構造。 - 半導体構造であって、
ハンドル層にボンディングされた活性層であって、前記ハンドル層が、前記活性層の第1の面上にある、活性層と、
前記第1の面に対向する前記活性層の第2の面上の絶縁材料のパターン層であって、掘削領域およびパターン領域からなるパターン層と、
前記パターン領域の上および前記掘削領域の中に配置されたひずみ層であって、前記活性層の中のデバイスにおけるひずみを示すひずみ層とを備え、
前記デバイスが、横方向に並んで配置されたソース、ドレイン、およびチャネルを有する電界効果トランジスタであり、前記チャネルが、前記ソースと前記ドレインとの間にあり、
前記パターン領域が、前記チャネルを前記横方向において少なくとも完全に包含し、
前記ソースおよび前記ドレインがそれぞれ、前記横方向において前記パターン領域と部分的に重複している、
半導体構造。 - 前記パターン領域が、前記掘削領域の深さに等しい高さを有し、
前記ひずみ層が、前記パターン層と接触する第1の面、および前記第1の面に対向する第2の面を有し、
前記ひずみ層が、前記ひずみ層の前記第1の面と前記第2の面との間の厚さを有し、
前記ひずみ層の前記厚さに対する前記パターン領域の前記高さの比が、0.75〜1.5の範囲内にある、
請求項8に記載の半導体構造。 - 前記比が1である、請求項9に記載の半導体構造。
- 前記電界効果トランジスタから離れて位置している別のパターン領域であって、前記掘削領域は前記パターン領域と前記別のパターン領域とによって画定されている、別のパターン領域をさらに備え、
前記チャネルの中心から前記別のパターン領域までの前記横方向における寸法は、前記横方向における前記チャネルの寸法よりも10倍大きい、
請求項8に記載の半導体構造。 - 前記電界効果トランジスタの前記チャネルの前記横方向における寸法は1ミクロンよりも短く、
前記チャネルの中心から前記別のパターン領域までの前記横方向における寸法は、10ミクロンよりも大きい、
請求項11に記載の半導体構造。 - 前記パターン層は、埋込み絶縁体に対応している、請求項8に記載の半導体構造。
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