TW201633515A - 具背側散熱能力之絕緣體上半導體結構 - Google Patents

具背側散熱能力之絕緣體上半導體結構 Download PDF

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TW201633515A
TW201633515A TW105113127A TW105113127A TW201633515A TW 201633515 A TW201633515 A TW 201633515A TW 105113127 A TW105113127 A TW 105113127A TW 105113127 A TW105113127 A TW 105113127A TW 201633515 A TW201633515 A TW 201633515A
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layer
insulator
strain sensing
type channel
strain
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TW105113127A
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TWI619235B (zh
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尼加德保羅Ａ
摩林斯圖爾特Ｂ
斯圖柏麥可Ａ
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瑟藍納半導體美國股份有限公司
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Abstract

本發明之實施例是為了散逸來自絕緣體上半導體(SOI)結構之熱而預備。在一實施例，揭露一種製造積體電路之方法。在第一步驟中，在SOI晶圓之一主動層中形成主動電路。在第二步驟中，自設置在該SOI晶圓之一背側上的一基板層去除基板材料。在第三步驟中，自該SOI晶圓之該背側去除絕緣體材料以形成一挖空的絕緣體區域。在第四步驟中，將一散熱層沉積在該挖空的絕緣體區域上。該散熱層為導熱的且電氣絕緣的。

Description

具背側散熱能力之絕緣體上半導體結構 相關申請案之交互參照
本專利申請案基於2009年7月15日提出申請之美國臨時專利申請案第61/225,914號，主張優先權。美國臨時專利申請案第61/225,914號之內容係併入本文中以供參考。
發明領域
所描述之本發明大致上關於絕緣體上半導體元件及加工，且更特別的是關於絕緣體上半導體元件中的散熱。
發明背景
絕緣體上半導體(SOI)技術在1990年代晚期首度商業化。SOI技術界定的特徵為形成電路的半導體區域係藉由電絕緣層與整體基板分隔。此絕緣層一般為二氧化矽。選擇二氧化矽的原因在於其可藉由氧化晶圓而形成在矽的晶圓上，且因此可接受有效率的製程。SOI技術之有利方面直接源自於絕緣層使主動層與整體基板電氣絕緣的 能力。如本文及附帶之申請專利範圍中所使用者，在SOI結構上形成信號處理電路之區域係稱為整體基板之主動層。
SOI技術代表傳統整體基板技術的改良，因為絕緣層之引入以分隔SOI結構中的主動元件，其改良該等主動元件之結構特性。舉例而言，希望電晶體的臨界電壓均一化，且主要藉由位在電晶體之閘極下方的半導體材料特性來設定。若此材料區域被分隔，進一步加工將影響此區域及改變元件臨界電壓的機會較低。源自於SOI結構之使用的其他電氣特性改良包括極少的短通道效應，降低的高速電容，以及若元件作為開關的話，插入損失較低。此外，絕緣層可作用以降低有害輻射對主動元件的影響。此對於用於太空中接受普遍存在之地球大氣層外有害離子輻射的積體電路而言特別重要。
第1圖中顯示SOI晶圓100。此晶圓包括基板層101、絕緣體層102，及主動層103。基板一般為一半導體材，例如矽。絕緣體層102為介電質，其通常透過基板層101之氧化形成之二氧化矽。主動層103包括摻雜劑、介電質、多晶矽、金屬層、鈍化層，以及在電路104已形成於其中後存在的其他層。電路104可包括金屬布線；例如電阻器、電容器及導體之被動元件；以及例如電晶體 之主動元件。如本文及附帶之申請專利範圍中所使用者，SOI晶圓100之「頂部」意指頂表面105，而SOI晶圓100之「底部」意指底表面106。不管SOI晶圓100相對於其他座標系統的相對位向，自SOI晶圓100移除層，或增添層至SOI晶圓100，此位向架構固定不變。因此，主動層103總是位在絕緣體層102之「上方」。此外，不管SOI晶圓100相對於其他座標系統的相對位向，自SOI晶圓100移除層，或增添層至SOI晶圓100，以主動層103之中心為原點且朝向底表面106延伸的向量，將總是指在SOI結構之「背側」的方向。
SOI元件被灌輸增進及保存其等之如上述之主動元件的電氣特性之能力。然而，絕緣體層之引入產生一元件散熱能力方面的顯著問題。由於積體電路中元件之逐漸微型化，更大量的產熱元件必須塞入愈來愈小的面積內。在現代積體電路中，電路104之熱生成密度可能是極大的。因為絕緣體層102之導熱性遠低於標準整體基板的導熱性，絕緣體層102之引入使此問題加速惡化。如前文中所述，二氧化矽在現代SOI技術中為無所不在的絕緣體層。在絕對溫度300度(K)之溫度下，二氧化矽之導熱性為每公尺每度絕對溫度大約1.4瓦特(W/m * K)。在相同溫度下，整體矽基板的導熱性大約為130W/m * K。SOI技術呈現的散熱 效能降低大約100倍是有極大問題的。積體電路中高量的熱可使其元件的電氣特性遷移偏離預期範圍，造成決定性的設計失敗。元件中餘留之未受遏止、過量的熱，可導致元件電路中呈翹曲或熔化材料形式的永久且決定性的失敗。
SOI元件中散熱的問題已使用各種不同的解決方法來處理。一種途徑涉及自絕緣體層102向上通過主動層103之散熱通道柱沉積。在一些例子中，因為與二氧化矽相較，金屬一般具有較高導熱性，故散熱通道柱係由金屬形成。在一些途徑中，此等柱係由多晶矽形成，以致於其等不會干擾電路的電氣效能，而同時其等提供自絕緣體層102向上且遠離的傳熱路徑。在其他途徑中，穿過絕緣體層102切割一孔洞，且散熱通道柱係沉積在孔洞中。此構成的結果係提供自主動層103通過絕緣體層102中的孔洞向下至基板101的散熱通道。此熱接著經由基板101散熱。
解決SOI元件中散熱問題之另一途徑涉及自背側在晶圓上操作。第1B圖例示說明如何使SOI晶圓100接合至操作由操作基板108及操作絕緣體層109組成之操作晶圓107。雖然此為一普遍的操作型式，絕緣體層109非一定要如同某些現代方法一般為絕緣體材料，該等現代方法使用具有半導體材料的操作晶圓，或以導電材料取代絕 緣體層109。於接合至操作晶圓之後，所得的結構可接著上下顛倒地倒裝，以形成第1B圖中顯示之結構。在此途徑之下，接著選擇性地自SOI晶圓100之背側去除基板101及絕緣體層102。於去除基板101及選擇性地去除絕緣體層102之後，將一金屬層110沉積在經蝕刻區域上，以容許透過絕緣體層102之較大導熱程度。當積體電路在操作時，此金屬通常係次要地使用於作為主動層103中元件的接地線或資訊信號線。雖然所得的結構呈現優於不具有背側散熱功能之SOI結構的散熱能力，絕緣體層係自主動基板下直接去除，減少SOI結構在保存及增進主動元件之電氣特性方面能力的優點。
發明概要
在本發明之一實施例中，揭露一種具有散熱層之積體電路。該積體電路包含一散熱層，一位在該散熱層上之主動層，以及一位在該主動層上的操作絕緣體層。該散熱層具有高導熱性且為電氣絕緣的。
在本發明之另一實施例中，揭露一種散逸來自一絕緣體上半導體元件的熱之方法。在第一步驟，疏導熱經由一主動層橫越一絕緣層的一頂表面。在第二步驟，使熱自該主動層經由一散熱層 散逸。該主動層係位在該散熱層之上方。此外，該絕緣體層係位在該主動層上，該絕緣體層係至少部分垂直地與該散熱層共同擴展，且該絕緣體層包含一挖空的絕緣體區域。又，該散熱層具有高導熱性且為電氣絕緣的，且該散熱層係設置在該挖空的絕緣體區域中。
在本發明之另一實施例中，揭露一種製造一積體電路之方法。在一步驟中，主動電路係形成於絕緣體上半導體晶圓之主動層中。在另一步驟中，自設置在該絕緣體上半導體晶圓之背側上的基板層去除基板材料。在另一步驟中，自該絕緣體上半導體晶圓之背側上去除絕緣體材料以形成一挖空的絕緣體區域。在另一步驟中，一散熱層係沉積在該挖空的絕緣體區域上。該散熱層為電氣絕緣的。
100‧‧‧SOI晶圓
101‧‧‧基板層
102‧‧‧絕緣體層
103‧‧‧主動層
104‧‧‧電路
105‧‧‧頂表面
106‧‧‧底表面
107‧‧‧操作晶圓
108‧‧‧操作基板
109‧‧‧操作絕緣體層
110‧‧‧金屬層
200‧‧‧散熱層
300‧‧‧絕緣體區域
301‧‧‧最下層金屬層
400‧‧‧通道區域
401‧‧‧電晶體閘極
402‧‧‧電晶體汲極
403‧‧‧電晶體源極
404‧‧‧金屬接點
500‧‧‧永久操作散熱層
501‧‧‧永久操作基板層
700‧‧‧步驟
701‧‧‧步驟
702‧‧‧步驟
703‧‧‧步驟
704‧‧‧步驟
705‧‧‧步驟
706‧‧‧步驟
800‧‧‧步驟
801‧‧‧步驟
802‧‧‧步驟
803‧‧‧步驟
804‧‧‧步驟
805‧‧‧步驟
806‧‧‧步驟
900‧‧‧NMOS，n-型主動元件
901‧‧‧PMOS，p-型主動元件
902‧‧‧應變感應層
903‧‧‧拉伸應變層
904‧‧‧壓縮應變層
1000‧‧‧閘極
1001‧‧‧應變感應層
1010‧‧‧閘極
1011‧‧‧應變感應層
1020‧‧‧閘極
1021‧‧‧應變感應層
1030‧‧‧閘極
1031‧‧‧應變感應層
1200‧‧‧步驟
1201‧‧‧步驟
1202‧‧‧步驟
1203‧‧‧步驟
1204‧‧‧步驟
1205‧‧‧步驟
1206‧‧‧步驟
圖式簡單說明
第1A圖及第1B圖例示說明根據習知技術之SOI結構中散熱的方法及結構之結構圖。
第2圖例示說明根據本發明之具有一散熱層之一SOI結構的結構圖。
第3圖例示說明根據本發明之具有一散熱層及一形成圖案之絕緣體層之一SOI結構的結構圖。
第4圖例示說明具有一散熱層、形成圖案之絕緣體層及一背側金屬接點之一SOI結構的結構圖。
第5圖例示說明根據本發明之具有一附接背側散熱操作晶圓之一SOI結構的結構圖。
第6圖例示說明根據本發明之具有一附接背側散熱操作晶圓及一形成圖案之絕緣體層之一SOI結構的結構圖。
第7圖例示說明根據本發明之一製造具有一散熱層之積體電路之方法的製程流程圖。
第8圖例示說明根據本發明之一使用一暫時操作晶圓製造具有一散熱層之積體電路之方法的製程流程圖。
第9圖例示說明根據本發明之一具有一形成圖案之應變層之SOI結構的結構圖。
第10圖例示說明根據本發明可使用之各種不同應變層圖案的結構圖。
第11圖例示說明根據本發明之一具有形成圖案之絕緣體層及一應變感應層之SOI結構的結構圖。
第12圖例示說明根據本發明之一製造具有一應變感應層之積體電路之方法的製程流程圖。
較佳實施例之詳細說明
現將詳細提及所揭露發明之實施例，該等實施例中之一或多個例子係例示說明於附帶的圖式中。每一例子係藉由解釋說明本發明技術之方式來提供，而非作為本發明技術的限制。事實上，熟習該項技術者將明瞭，在未偏離本發明之精神與範疇之下，可對本發明技術進行改良及變化。舉例而言，被例示說明或描述成一實施例之部分的特徵可與另一實施例一起使用以產生又另一實施例。因此，所欲為本發明之標的物涵蓋落於附帶之申請專利範圍及其等效物之範疇內的此等改良及變化。
本發明之實施例提供具有改良之散熱效能同時保有伴隨SOI結構之有利電子元件特性之SOI元件製造的實施例。此外，具有上述優點的元件可根據本發明，利用對最常使用於半導體工業之製造方法進行極些微改良來製造。假定與現有製造方法的相容性得避免可面對新穎半導體解決方案所需之接近無法克服的製造成本投資，這是極大 的優點。本發明之實施例經由背側加工之應用、部分SOI包埋絕緣體層之去除，以及在SOI結構之背側上呈變化構形之散熱層沉積來達到此結果。
根據本發明之SOI結構可參考第2圖來描述。如第2圖所示，主動層103係設置在操作晶圓107上。根據上文中描述之習知技術，操作晶圓107是在主動層103之上。此外，主動層103是在散熱層200之上。散熱層200是導熱的且電絕緣的。可用於形成散熱層200的材料包括鑽石、類鑽碳、碳化矽、氧化鋁、氮化鋁、氧化鈹、氮化鈹、石墨烯，及類似奈米碳管之某些碳成形物。
選擇兼具電絕緣性及導熱性之用於散熱層200的材料，保留藉由SOI技術所提供之有利電氣特性，同時大幅地減少傳統使用二氧化矽絕緣體層之SOI元件所面對的散熱問題。舉例而言，純人造鑽石在300K之下的導熱性大約為3,300W/m * K且氧化鈹之導熱性為260W/m * K。這是與傳統SOI結構中的非導電性二氧化矽層比較，該二氧化矽層如上文中之描述係具有1.4W/m * K之導熱性。如本文及附帶之申請專利範圍中所使用者，一材料層若導熱性大於50W/m * K，則其具有高導熱性。鑽石與氧化鈹在散熱性能上提供優於傳統SOI結構100倍以上的改良。在本發明之特定實施例中，至少部分地去除絕緣體層102，且在沉 積一層導熱材料以形成導熱層200之前沉積另一非常薄的絕緣體層。絕緣層的極薄度增進結構自主動層103散熱至導熱材料層之能力。舉例而言，沉積絕緣層可包含相同材料之薄層以作為原始絕緣體層。導熱及非導電材料的優點係在未受限於傳統SOI結構之不良散熱特性之下，限制藉由保留主動層103中主動元件的電子特性來實現。
第2圖中顯現的結構係使用背側加工來製造。因為此SOI結構與典型SOI加工方法相反地，係自背側操作，所以使用於散熱層200的材料不需要依其對主動層103提供安定性之能力或作為用於製造主動層103中電路之適當基板的能力來選擇。這是因為原始絕緣體層-絕緣體層102-係供作基底層，同時製造電路，且操作晶圓107在背側加工期間提供支撐。因為絕緣體層102及基板101提供主動層103之機械支撐，故絕緣體層102之去除一般是不理想的。在無此等層在適當位置之下，主動層103之進一步加工將同樣地對電路104不利。然而，在此階段增添操作晶圓107容許積體電路之額外加工。使用於此背側加工之方法將更詳細地描述於下文中。
背側加工之另一有利態様為容許在半導體加工的後續階段中增添散熱層200，其相繼地容許可能無法另外施用之散熱層200之材料的使 用。與傳統途徑對照之下，背側加工容許於完成主動層103之半導體加工後，增添散熱層200。半導體製造方法的某些相要求溫度超過1000℃。某些材料無法耐受此等溫度且因此一般被視為不適於用作位在散熱層200處的熱分散層。然而，背側加工之使用容許使用更脆弱材料在散熱層200上。
根據本發明之積體電路可參考第3圖來描述。在第3圖中，如同SOI元件中常見者，一主動層103係設置在絕緣體層102上。然而，絕緣體層102已挖空的特定部分以形成藉由挖空的絕緣體區域300所定義的圖案。挖空的絕緣體區域並非必須是相鄰的，而是絕緣體層102可以各種不同方式形成圖案以暴露主動層103之不同部分。在第3圖中，散熱層200已被施覆在積體電路的整個背側表面，包括在挖空的絕緣體區域300。在本發明之特定實施例中，散熱層200係僅設置在挖空的絕緣體區域300中。在本發明之特定實施例中，使散熱層200形成圖案且僅設置於一部分挖空的絕緣體區域300中。在第3圖中，挖空的絕緣體區域300係藉由完全去除挖空的區域中之所有絕緣體材料來例示說明。然而，在本發明之特定實施例中，挖空的絕緣體區域300可由殘餘的薄絕緣層組成。絕緣體層之初始厚度一般自100奈米(nm)至1000nm。薄絕緣層可自5nm至100nm。然而，任何 程度的薄化將造成薄絕緣體層。雖然難以使用傳統方法達成，但約1nm之殘餘的絕緣體材料的單層即已足夠。任何程度的薄化將構成初始結構在散熱能力方面之改良。第3圖中所示的結構可保留藉由主動層103之隔離元件所提供之增進的電氣特性之優點，另一方面同時因為熱可側向流經主動層103且接著經由絕緣體已薄化或去除之散熱層200消散以提供增進的散熱作用。
絕緣體層102之去除的優點及缺點可藉由用於挖空的絕緣體區域300之特定圖案的形成來平衡。舉例而言，可使挖空的絕緣體區域300與主動層103中一最下層之金屬布線共同擴展。如第3圖中所示，挖空的絕緣體區域300係側向地與最下層金屬層301共同擴展。在本發明之特定實施例中，挖空的絕緣體區域300暴露最下層金屬層301之特定部分。在本發明之特定實施例中，挖空的絕緣體區域300暴露所有的最下層金屬層301。在本發明之特定實施例中，最下層金屬層301為形成於主動層103中用於電路的最下層布線。由平衡的觀點，此構形是高度有利的，因為若金屬布線未放置在絕緣體上，其等一般不會遭受改變的電氣特性。此外，金屬具有高度導熱性，且金屬布線一般連結至主動元件，使此等金屬線成為用於散熱之高效率通道。雖然極大部分之產生於主動 層103的熱係由主動元件產生，熱將自此等主動元件散發至金屬線且接著經由SOI結構之背側經由散熱層200消散。因為現代電路具有大量金屬層，使背側安排一更直接之出口通道的路線，此途徑一般優於安排使熱經由金屬線向上且離開SOI結構之頂部的路線。
另一根據本發明之絕緣體上半導體結構可參考第4圖來描述。顯示於第4圖之積體電路可用於描述用於挖空的絕緣體區域300的另一組圖案，其提供SOI結構一有利的散熱能力。在第4圖中，具有電晶體閘極401之電晶體的通道區域400係位在絕緣體層102的橫向範圍內。然而，挖空的絕緣體區域300暴露電晶體汲極402及電晶體源極403，因為挖空的絕緣體區域300係與電晶體汲極402及電晶體源極403橫向地共同擴展。散熱層200係設置於挖空的絕緣體區域300之暴露電晶體汲極402及電晶體源極403的部分。金屬接點404係設置於挖空的絕緣體區域300之另一部分。在本發明之特定實施例中，金屬接點404不具電氣主動性，而是存在以提供散熱路徑。在本發明之特定實施例中，金屬接點404可供作為主動層103中用於電路的電接點。舉例而言，金屬接點404可為用於自主動層103之電路帶出資訊信號以供另一系統使用。在另一例子中，金屬接點404 可為用於主動層103之電路的接地或電源線。在本發明之特定實施例中，凸塊金屬加工沉積凸塊金屬接點在顯示於第4圖之SOI結構上，以致於金屬接點404為SOI結構之凸塊金屬連接器。在上文描述之實施例中，其中金屬接點404不具電氣主動性，金屬接點404非一定必須為金屬，而是可為任何具有良好導熱性的材料。在本發明之特定實施例中，此等金屬接點為金屬柱接點。金屬柱接點可由金或銅組成。因為此等材料與焊料相較為更佳的導熱體，此等材料與焊料凸塊相較可更有利地實行。在本發明之特定實施例中，金屬接點404容許附接至電路板。在本發明之特定實施例中，金屬接點可容許附接至低溫共燒陶瓷基板、模組板、積體電路、凸塊金屬、金凸塊金屬、銅柱、金柱及任何金屬連接件。
在本發明之特定實施例中，挖空的絕緣體區域300將與主動層103之主動元件的部分橫向地共同擴展。如第4圖中所示，此等實施例可包括電晶體汲極402及電晶體源極403之暴露，另一方面保持由絕緣體層102覆蓋的電晶體通道400。此等實施例將呈現具有隔離之通道區域的有利態樣，另一方面容許高度緊鄰的散熱通道。因為通道400保持由絕緣體層102所覆蓋，將保留電晶體的電氣特性。除了更受控制的臨界電壓以外， 電晶體將呈現較少的漏電流且基板電容。又，因為電晶體之源極與汲極直接鄰接電晶體通道，存在有非常直接之通道至散熱層200。在本發明之其他特定實施例中，挖空的絕緣體區域300僅暴露SOI結構之一次組的主動元件。在本發明之其他特定實施例中，挖空的絕緣體區域300將暴露SOI結構之其他次組的獨立主動元件區域。
在本發明之特定實施例中，金屬接點404係設置在挖空的絕緣體區域300之第一部分。此外，散熱層200係設置在該挖空的絕緣體區域300之第二部分且亦設置在金屬接點404之一側。此一構形可見於第4圖中。熱將可直接由主動層103經由金屬接點404消散。此外，熱將能夠側向流經散熱層200且接著經由金屬接點404流出。雖然第4圖顯示此實施例與挖空的氧化物區域300係對應主動層300之區域來形成圖案之實施例的組合，此等實施例可單獨作用。
任何上述討論之關於使用挖空的絕緣體區域300以構成散熱層200與主動層103之部分對齊的圖案的實施例，可單獨地或組合地使用。此外，去除絕緣體材料之圖案以形成挖空的絕緣體區域300可與散熱層200之形成圖案的沉積組合。舉例而言，散熱層200可設置在SOI結構之整個背側上，可僅設置在挖空的絕緣體區域300，或 可設置在部分之挖空的絕緣體區域300。形成圖案之散熱層200之方法係於下文中討論。
形成圖案之挖空的絕緣體區域300或額外之散熱層200之本發明的實施例呈現有利的特性。雖然散熱層200為電氣絕緣的，在某些區域中遺留原始絕緣體材料產生某些優點。舉例而言，有可能使散熱層200包含電氣絕緣性較原始氧化物低的材料。此材料可經選擇以犧牲其電氣絕緣能力以使成本最小化且使導熱性最大化。在導電性具重要性的主動層103部分，原始絕緣體可留下且挖空的絕緣體區域300可位在其他處。在此方法中，形成圖案在選擇散熱層200之最適材料上容許另一程度之自由度。
形成圖案之挖空的絕緣體區域300提供另一優點，因為其可限制主動層103之界面狀態的產生。即使散熱層200為良好的電絕緣體，因為原始絕緣體之去除造成當施用散熱層200時無法再連接之懸鍵的產生，原始絕緣體一般將與主動層103有較佳的物理接觸。此將造成界面狀態的產生，該界面狀態可造成主動層103中電路的問題。形成圖案之挖空的絕緣體區域300可藉由容許原始絕緣體保留與主動層103之重要部位接觸，以有利地限制此等界面產生於主動層103之重要部位。
另一根據本發明之SOI結構可參考第5圖來描述。根據先前描述之傳統技術，第5圖例示說明操作晶圓107下方之主動層103。如參考本發明之其他實施例所述者，絕緣體層102及基板101已經由背側加工自主動層103之底部去除。在本發明之特定實施例中，操作晶圓107係經由暫時鍵結接合至主動層103。此意指此鍵結在半導體加工之後續階段可容易地斷開。在本發明之特定實施例中，以永久操作散熱層500及永久操作基板層501來例示說明之永久第二操作晶圓，在背側加工期間係直接接合至主動層103。在本發明之特定實施例中，永久操作基板層501係由與永久操作散熱層500相同之材料組成。此結構可容許可與先前描述之實施例媲美的散熱能力程度，但亦將有利地容許使用傳統技術以頂側接合至主動層103之電路。因為操作晶圓107係經由暫時鍵結接合，可於不再需要其在背側加工期間提供的支撐之後予以去除。接下來，將使主動層103之頂側暴露以容許頂側接合及各種不同的其他應用。
根據本發明之另一SOI結構可參考第6圖來描述。第6圖例示說明本發明之一特定實施例，其組合具有參考第5圖描述之具有背側永久操作的形成圖案之絕緣體層的態樣。在本發明之特定實施例中，永久操作基板層501及永久操作散熱層 500係在已施用散熱層200之後，設置在SOI結構之背側上。在本發明之特定實施例中，使用於永久操作散熱層500之材料可與使用於散熱層200之材料相同。散熱層200及500可經由濺鍍或一些其他方法施用。如同前文中所描述者，散熱層200係設置於藉由絕緣體層102之濺鍍形成之挖空的氧化物區域中。此例示說明於第6圖中的特定實施例顯示使絕緣體層102形成圖案以暴露最下層金屬層301，以與先前描述之本發明的特定實施例一致。事實上，所有上文中討論之形成圖案及散熱層的變化可與參考第5圖描述之永久操作觀念組合，以產生具有有利散熱及電氣特性之本發明的實施例。此等實施例將具有能夠前側接合至主動層103之電路的額外有利特性。
根據本發明之製造積體電路的方法可參考第7圖來描述。在本發明之特定實施例中，一製造積體電路的方法係在步驟700中，以製備用於加工之SOI晶圓開始。此步驟包含如同使用SIMOX或植入及切割方法所製造之由位在二氧化矽絕緣體上方之主動矽層所組成之SOI晶圓之實際製造。此步驟亦可包含購買預製之SOI晶圓及其製備以供進一步加工。
在本發明之特定實施例中，在步驟700之SOI晶圓的製造之後，隨後是步驟701之形 成SOI晶圓主動層中的主動電路。在此步驟期間及在此層中形成的電路可包括但不受限於例如CMOS、BiCMOS、SiGe、GaAs、InGaAs及GaN的技術。此電路可包含：例如二極體及電晶體之各種不同的主動元件；例如電阻器、電容器及導體之各種不同被動元件；以及例如金屬線及貫孔之路由電路。可進行各種不同的光微影術及化學沉積步驟以制定此電路。
在本發明之特定實施例中，在步驟701之主動電路的形成之後，隨後是SOI晶圓之背側加工。在本發明之特定實施例中，背側加工以步驟702中的在主動層上方將第二操作晶圓附接或永久接合至SOI晶圓為開始。用於引入永久接合至操作晶圓的方法包括永久有機或無機黏著劑、氧化物玻璃料接合、電鍍接合、分子熔融接合、任何形式之電磁接合及其他已知之用於產生永久晶圓接合的方法。
在操作晶圓永久接合至SOI結構之後，SOI晶圓基板可在步驟703中去除。基板可單獨地或組合地使用機械及化學手段去除。舉例而言，機械研磨可使用於將基板材料自大約800微米(μm)之初始厚度薄化至大約20μm。若基板為矽，基板材料的最終厚度可利用例如KOH或TMAH之濕式蝕刻去除。基板材料的最終厚度亦可 利用乾式電漿蝕刻來去除。基板可利用高精密度或蝕刻速率比例以去除。蝕刻速率比例意指自晶圓背側被去除之所欲基板材料的速率相對於不應被去除但被去除之額外材料的速率之比例。在本發明之特定實施例中，因為蝕刻速率比例可能極端高以供去除所有基板直至包埋的氧化物，故絕緣體層係為當作蝕刻擋止層的包埋之氧化物。
在本發明之特定實施例中，在步驟703之去除SOI基板之後，隨後是可制定任何先前描述之結構的額外背側加工。在本發明之特定實施例中，在去除SOI基板之後，隨後是步驟704之去除SOI絕緣體層以形成挖空的絕緣體區域。如前文中所述，絕緣體層可完全去除，僅全面薄化且保持比原始厚度更薄，或可用使挖空的絕緣體層形成如上述數種圖案中任一者之方式來去除。此等圖案可使用標準光微影技術或選擇性化學汽相沉積來形成。薄化絕緣體層必須小心地進行以避免損害主動層。雖然僅需要約1nm之單層絕緣體材料，薄化可能受限於原始絕緣體的均一性。舉例而言，若初始層以具有大於5nm之變異開始，則用於絕緣體去除之傳統方法將無法留下小於5nm之最終層。此外，此等圖案可建構成利用有利的交換以達遮蔽主動層之電路的程度及所得之SOI結構如上述般有效散熱的程度。
在本發明之特定實施例中，在步驟704之自SOI晶圓的背側去除絕緣體材料之後，隨後是步驟705之在挖空的絕緣體區域之SOI晶圓的背側上沉積散熱層。可進行此散熱層之沉積以產生任一上述的結構。此步驟可同樣地在去除基板材料後立即進行。此外，此步驟可在金屬接點的沉積期間進行，其中例如金屬接點係以二或更多步驟來設置，或若孔洞係稍後開啟於散熱層中以暴露用於電氣連接，則此步驟在金屬接點的沈積之後進行。在步驟705中，此散熱層之增添可經由化學汽相沉積、濺鍍或另一其他方法來達成。此外，根據前述揭露結構之散熱層的形成圖案的沉積可經由使用標準光微影術加工或選擇性化學汽相沉積來達成。如上文中所述，在本發明之特定實施例中，在此步驟中沉積的散熱層將為電氣絕緣的且導熱的。
在本發明之特定實施例中，在步驟705之在SOI晶圓的背側上沉積散熱層之後，隨後是鈍化SOI晶圓之背側上的界面狀態。在本發明之實施例中，其中在步驟704中去除整個絕緣體，因為在步驟705中沉積之散熱層有可能具有高界面狀態密度(界面狀態密度)，此可能是高度有利的。沉積膜傾向具有非常高的界面狀態密度，除非此等膜係在高於800℃之高溫下退火。因為此溫度高於已發展主動電路之後的標準晶圓可操作溫度，高溫 退火並非在此時機的選擇。然而，使用低溫退火可使此等界面狀態鈍化。在本發明之特定實施例中，此低溫退火將在400-450℃之溫度範圍下進行，且將在含純氫氣或形成氣體之含氫氣體環境中完成。形成氣體為非爆炸性N2及H2混合物。此鈍化層步驟可造成遠比其他方法所造成者更薄的散熱層。舉例而言，使用傳統化學汽相沉積設備或濺鍍設備，此層的厚度可為5nm至20nm且具有約+/-5%之均一性。因此，此步驟容許沉積非常薄的絕緣層，且因此容許非常有效率之自主動層的導熱作用。在此等實施例中，散熱層將包含一有效率展開之絕緣體材料層，其增進SOI結構之散熱效態。在本發明之特定實施例中，一高度導熱材料層係沉積在此絕緣體材料之薄層的背側，且此散熱層包含此薄絕緣體材料層及導熱材料層二者。
在本發明之特定實施例中，在步驟704之去除全部絕緣體層之後，可接著沈積一薄層，該薄層具有與在前述段落中描述的隨後進行低溫退火鈍化步驟之步驟704中被去除者相同之絕緣體材料。舉例而言，去除之絕緣體材料可為二氧化矽以及沉積且低溫退火的材料亦可為二氧化矽。二氧化矽因具有低界面狀態特性故為使用上有利的材料。二氧化矽將被去除且接著沉積的理由是沉積且低溫退火的製程可產生比經由使用上述方法 之原始層之部分回蝕可達到者更均一且更薄的絕緣體材料層。
在本發明之特定實施例中，在步驟705之在SOI晶圓之背側上沉積散熱層之後，隨後是在選擇之區域中去除散熱層，以容許在後續加工期間與主動層中的主動電路電氣接觸。在一實施例中，散熱層之挖空的部分可位於最低層金屬之區域係存在以暴露用於電氣接觸之金屬處。或者，在主動矽區域下可選擇性地去除散熱層，以容許與主動結構直接接觸。除了散熱層以外，可能要求去除其他介電層以暴露用於電氣接觸的各種不同導體。導熱層之去除可使用光微影術之已知手段及使用適當化學性質之乾式或濕式蝕刻來選擇性地完成。
在本發明之特定實施例中，自SOI晶圓之背側去除散熱層之區域，隨後是步驟706之金屬接點的沉積。此等金屬接點係沉積於在步驟704或步驟705中形成之挖空的絕緣體區域之第一部分。金屬接點能夠快速地自主動電路散熱。在本發明之特定實施例中，金屬接點可提供用於自主動電路散熱之散熱通道以及用於信號或電源連接至外部元件之接點二者。此等金屬接點可包含球形接合、焊料凸塊、銅柱或其他晶粒接點材料。金屬接點可額外地建構成附接至電路板，或低溫共燒陶瓷基板。在此步驟中產生的結構將藉此具有接點至結 構之底側上的SOI結構之主動層，其在標準SOI元件中為相反的位向。
根據本發明之製造積體電路的方法可參考第8圖來說明。在本發明之特定實施例中，用於製造積體電路之方法以步驟800之用於加工之SOI晶圓的製備開始，且繼續步驟801之SOI晶圓之主動層中電路的形成。步驟800及801可分別參考先前描述之步驟700及701來進行。步驟802可包含接合操作晶圓至SOI晶圓之主動層的頂側。操作晶圓可暫時地接合至主動層。用於導引一暫時接合至操作晶圓的製程包括例如布魯爾科技公司(Brewer Science)的HT 10.10、3M公司的WSS(晶圓支撐系統)、HD Micro公司的聚亞醯(HD Micro polyimide)及TMAT之黏著劑。此操作晶圓可包含將接合至主動矽且設置在基板上之絕緣體層。在此點，主動電路將因此夾置在二絕緣體層之間。或者，操作晶圓可包含一導電性或半導體性材料。在步驟802之操作晶圓的暫時接合之後，可如同先前分別描述於步驟703、704及705者，進行所有步驟803、804及805。
在本發明之特定實施例中，在步驟805之散熱層的沉積之後可隨後進行步驟806之附接或永久接合第二、永久性操作晶圓至主動層下方的SOI結構。此背側加工步驟的功效是改變可形 成至SOI結構之主動電路的接點之方向。一旦此第二操作晶圓係永久地接合至SOI晶圓之背側，由於原始操作晶圓係使用暫時的且可逆的製程來接合的事實，故在步驟807中，原始操作晶圓可容易地去除。用於導致永久接合至頂側操作晶圓之製程包括永久有機黏著劑、氧化物半熔質接合、賈凡尼電流接合、分子熔融接合、任何電磁接合方法，及其他用於產生永久晶圓接合之已知方法。一些接合方法，例如分子熔融接合，可能要求欲接合之二表面具有高度的平坦度。若絕緣體材料被選擇性地去除，可能將非平面性引入晶圓之表面，其使得接合更困難。在該情況中，在接合步驟之前，化學機械拋光可用於平坦化晶圓之表面，改良接合效率。
在步驟806中製造之結構將具有暴露於其頂側之SOI結構之主動層且進一步加工容許自頂側直接連接至主動電路。在步驟806中接合之第二、永久性操作晶圓可完全由電絕緣性但導熱性之材料組成。此外，第二操作晶圓可由此一設置在基板材料上的材料組成。此第二構形可節省成本，因為基板材料將提供最終SOI元件所需要的安定性，另一方面不需要使用那麼多極昂貴的導熱材料。在步驟805中，在二、永久性操作晶圓上的導熱材料有可能由沉積的相同材料所組成，以形成散熱層。或者，在步驟806中接合之永久操作晶圓可 由導電性材料或半導體材料組成，例如矽或高電阻率矽。
背側應變感應層
本發明之實施例提供SOI結構之主動元件的製造，該等主動元件具有應變感應材料與其等通緊密接觸。本發明之實施例容許在元件製造過程中，在比施用應變感應層之通常階段更晚的階段中引入此類應變感應材料。此容許增進之應變感應層效率，另一方面同時在間歇的製造階段中降低損害SOI結構的風險。此外，具有上述益處的元件可根據本發明對半導體工業中最常使用之製造過程進行極小的改良來製造。假使與現存的製造過程之相容性避免可面對新穎半導體解決方案之幾乎不可克服的固定製造成本投資，這是極大的優點。本發明之實施例經由背側加工之利用、SOI絕緣體層之部分的可能去除，及在SOI結構之背側上不同構形來達到此結果。
將機械拉力或壓縮應變引入材料中包含主動元件之通道可增加電荷載子在此一主動元件中的移動率。一般而言，感應拉伸應變增加電子的移動率且感應壓縮應變增加電洞的移動率。n-型主動元件，例如n-型金屬氧化物半導體(NMOS)，因為在NMOS元件中的電荷載子為電子，若其通道感應拉伸應變，將因此能夠在較高頻 率下操作。同樣地，p-型主動元件，例如p-型金屬氧化物半導體，因為在PMOS元件元件中的電荷載子為電子，若其通道感應壓縮應變，將因此能夠在較高頻率下操作。
根據本發明之SOI結構可參考第9圖來描述。第9圖例示說明SOI結構，其中包含主動層103、絕緣體層102，及基板之原始SOI晶圓已附接操作晶圓107且已進行背側加工以去除其基板。電路已經產生於包括例如NMOS 900之n-型主動元件及例如PMOS 901之p-型主動元件的主動層103。此外，應變感應層902係存在於絕緣體層102的背側。
與半導體元件中感應應變的典型途徑相較，例示說明於第9圖中的構形具有某些有利的特性。在元件中的應力伴隨其產生的益處可造成例如晶圓翹曲的問題，所以理想的是儘可能明確地保持半導體結構內感應的應變全部量是有限的且成為目標。因為應變感應層之效能隨待產生應變之區域與應變區域間之距離減少而增加，半導體內感應的全部應變是有限的，另一方面藉由儘可能地鄰近主動元件之通道來放置應變感應層，以達到相同的有利通道應變。因為最底層一般必須首先被沉積，故由頂部加工之製造途徑的觀點，這是有問題的。因此，應變感應層一般沉積在FET元件之閘極之 上，且因此位在與通道有一實質距離處。再者，應變層中的非平面性係經由形成圖案之閘極而引入，使應變感應層之效果依例如FET元件之長度及寬度之幾何效果而定。此外，於涉及600-1050℃範圍之極高溫度的應變層沉積之後，半導體元件進行進一步的加工步驟。此必要性對半導體元件具有二弱化效果。首先，藉由應變感應層感應的應變在高溫度退火期間可能降低，其與應變感應層之整體目的背道而馳。第二，應變感應層可造成主動層之塑性變形及晶圓翹曲，其可造成例如滑動及差排產生的矽晶體缺陷，其將顯著地降低所得元件之電氣效態及產品產率。相反地，根據本發明使用背側加工之應變感應層的沉積，容許在主動層已完成加工之後，使應變感應層緊密接觸主動元件之通道而沉積，因此避免在早期階段引入應力所伴隨的問題。
在本發明之特定實施例中，應變感應層係用微影製程或例如在下文中參考第11圖來討論之其他製造方法來施用，其容許應變感應層之形成圖案的沉積。第9圖例示說明一特殊的實施例，其中應變感應層902已被形成圖案成為包含拉伸應變層903及壓縮應變層904。在本發明之特定實施例中，此二部分之應變感應層902可使用不同材料來形成，該等材料具有在主動層103上產生拉伸 應變或壓縮應變的傾向。可感應拉伸應變之材料包括氮化矽及氮化鋁。可感應壓縮應變之材料包括氮化矽、氮化鋁及類鑽碳。依材料的沉積條件而定，相同材料可感應壓縮應變或拉伸應變。在本發明之特定實施例中，此二部分之應變感應層902可藉由在不同條件下沉積相同材料來形成。數種材料可被應用，其中材料之應變感應特性可藉由調整沉積條件來控制。舉例而言，在不同條件下利用化學汽相沉積來沉積氮化矽或氮化鋁，可產生拉伸應變或壓縮應變。在本發明之特定實施例中，拉伸應變層903可沉積在具有例如NMOS 900之n-型主動元件之SOI結構的區域上，且壓縮應變層904可沉積在具有例如PMOS 901之p-型主動元件之SOI結構的區域上。藉此，可有效地增進二元件的載子移動率。
在本發明之特定實施例中，在背側加工期間，於SOI結構之底部施用均一的應變感應層。此等實施例在特定載子型式的主動元件在主動層103之電路中佔優勢時，具有特別的實用性。舉例而言，若在主動層103中的主動元件主要是NMOS電晶體，均一的拉伸應變層可施用至SOI結構之背側。藉此，將增進NMOS電晶體，且由更多的NMOS電晶體之增進所提供的利益將勝過任何PMOS電晶體中載子移動率之電位弱化改變。
在本發明之特定實施例中，一應變感應層或多數應變感應層係直接施用至主動層103的背側。此係藉由在應變感應層902的沉積之前的去除絕緣體層102之額外背側加工步驟來達成。此等實施例共享容許在半導體元件加工順序之較後階段沉積應變感應層的有益特性。然而，在此等實施例中，應變感應層係更靠近主動層103。因此，要求較低之總體應力，其可增進所得之半導體元件的電氣特性及良率，另一方面仍增進其主動元件之通道中之電荷載子的移動率。在本發明之特定實施例中，當應變感應層902直接沉積在主動層103上時，應變感應層902係由電氣絕緣材料組成，以保留SOI結構之有益特性。既感應應變又可作為電氣絕緣體的材料包括氮化矽、氮化鋁、碳化矽及類鑽碳。
在本發明之特定實施例中，應用不同的圖案以於主動層103中感應應變。此等圖案可產生與電荷載子的流動垂直之雙軸應變或單軸應變。此等圖案可藉由施用如上述之多數至少部分垂直之共同擴展的應變感應層來形成。同樣地，此等圖案可藉由施用如上述之沉積於挖空的絕緣體區域的應變感應層來形成。可感應拉伸應變或壓縮應變的不同圖案可參考第10圖來描述。閘極1000係由應變感應層1001圍繞。若應變感應層1001為拉 伸應變感應層，此圖案將在閘極1000下方之通道中產生雙軸拉伸應變。若應變感應層1001為壓縮應變感應層，此圖案將閘極1000下方之通道中產生雙軸壓縮應變。閘極1010係由應變感應層1011圍繞。閘極1010之寬度相對於長度的比例大。因此，應變感應層1011之應用將在閘極1010下方之通道中感應佔優勢的單軸應變，其與流經該通道之電荷載子流平行，且根據應變感應層1011係對應地為壓縮或拉伸而為壓縮或拉伸。閘極1020係位在應變感應層1021上。此圖案將在閘極1020下方之通道中感應佔優勢的單軸應變，其與流經該通道之電荷載子流垂直，且因應變感應層1021對應地為分別為壓縮或拉伸而為壓縮或拉伸。最後，閘極1030係由應變感應層1031圍繞。若將相同的材料使用於應變感應層1031及1011，此圖案的效果將產生相反之由層1011感應的應變。舉例而言，若應變感應層1031為拉伸感應的，則閘極1030下方之通道中將感應壓縮應變。同樣地，若應變感應層1031是壓縮的，則閘極1030下方通道中將感應拉伸應變。
根據本發明之SOI結構可參考第11圖來描述。第11圖例示說明包含主動層103之SOI結構，其中絕緣體層102已根據特定圖案去除以形成挖空的絕緣體區域300，且在主動層103中 產生所欲的拉伸力分布。在本發明之特定實施例中，於所有應變感應層902使用相同的材料，可在主動層103中感應拉伸應變及壓縮應變二者。如上文中參考第10圖所描述者，可於應變感應層1011及1031使用相同材料以在閘極1010及1030下方之通道中感應相反形式的應變。如第11圖所例示說明者，挖空的絕緣體區域300可暴露例如NMOS 900之n-型主動元件的通道，以及環繞例如PMOS 901之p-型主動元件的通道形成圖案。在此例子中，應變感應層902可為均一的拉伸應變感應層，其等將與挖空的絕緣體區域300之圖案協力增進NMOS 900中的電子及PMOS 901中的電洞之移動率。在本發明之特定實施例中，與前述實施例相較，圖案之極性及沉積材料之應變形式被交換，且將達到相同的雙重增進效果。
在本發明之特定實施例中，挖空的絕緣體區域300可被形成僅暴露主動層103中的支組主動元件。舉例而言，去除挖空的絕緣體區域300以呈僅暴露例如NMOS 900之n-型元件的通道之圖案，且接著在SOI結構之背側沉積6拉伸應變感應層。同樣地，在本發明之特定實施例中，與前述實施例相較，圖案之極性及沉積材料之應變形式可被交換。在本發明之特定實施例中，在餘留之絕緣體區域下層的應變感應層可經由蝕刻製程被 去除。雖然在此等實施例中，僅有一形式的元件被拉緊，其將仍然導致有利的效態，尤其是在更重度依賴特定形式之半導體材料的設計中。
在本發明之特定實施例中，與SOI結構之背側接點的感應主動元件中應變的材料亦可供作散熱層。因此，在此說明書之第一節中的任一散熱層可由額外感應應變的層來取代。此外，此實施例與該等實施例的組合產生有利的結果，其中應變感應層係形成圖案以與例如主動元件之通道的熱源接觸。在一特定實施例中，應變感應層將沉積在主動元件之通道上且將兼作應變及散熱層，且其亦將以標準絕緣體層在SOI元件中作用的方式與元件分隔。藉由電氣分隔、導熱及應變感應可提供所有此等有利特性的材料包括氮化鋁、碳化矽及類鑽碳。在本發明之特定實施例中，絕緣體層102可被完全去除且被形成圖案的熱散佈層取代，該熱散佈層可散熱且同時提供用於如參考第10圖所述之應變感應層的圖案。
根據本發明之製造積體電路的方法可參考第12圖來描述。在步驟1200中，利用背側加工，自SOI結構之背側去除基板。在本發明之特定實施例中，SOI結構已進行顯著的加工以致於SOI結構之主動層中的電路係接近完成。在步驟1200中之基板的去除係與參考第7圖之步驟703所描述 者相同。在本發明之特定實施例中，在步驟1200之後，隨後是步驟1203之在SOI結構之背側上的應變感應層沉積。沉積之應變感應層可經由濺鍍、化學汽相沉積或任何其他方法沉積在SOI層的整個背側表面上。應變感應層可感應壓縮應變或拉伸應變。再者，在步驟1203中，沉積層可利用微影術或其他方法形成圖案以沉積一部分之第一應變層，且接著在步驟1205中形成另一應變層。在此例子中，將形成多部分之應變感應層，其可具有一拉伸感應部及一壓縮感應部。在本發明之一特定實施例中，多部分之應變感應層事實上可使用與步驟1203及1205中相同的材料，組合此二步驟之個別不同的加工條件來形成。如上文中所描述者，例如氮化矽之材料依其被施與的條件而定以施加拉伸或壓縮應力。
在本發明之特定實施例中，在步驟1200之基板材料的去除之後，隨後是步驟1201中之絕緣體材料的去除。此去除可涉及參考第7圖步驟704討論之任何方法。在本發明之特定實施例中，在步驟1201之後，隨後可為步驟1202之散熱層的沉積。此沉積可涉及參考第7圖步驟705及706討論之任何方法。在本發明之特定實施例中，在步驟1201之後，隨後可替換成步驟1203之應變感應層的沉積。在本發明之特定實施例中，其中應 變感應層及散熱層為同一者時，在此二步驟之間將沒有差別。在本發明之特定實施例中，步驟1201之絕緣體層去除可自SOI結構之背側完全去除絕緣體材料。若在此步驟之後，隨後是應變層1203之沉積，所得之SOI結構將包含直接沉積在主動層之背側的應變層。
在本發明之特定實施例中，步驟1201中之絕緣體材料去除可如上述般以特定圖案的形式去除絕緣體材料。之後可隨後是步驟1203之應變層的沉積，以致於應變層係沉積在步驟1201中形成之挖空的絕緣體區域。舉例而言，僅有位在電路之打算感應應變的該等部分下的絕緣體材料被去除，例如僅有位在n-型元件下者。在該例子中，應變感應層將為拉伸的且僅有n-型元件將有利地產生應變，另一方面p-型元件係保留標稱狀態。作為另一實施例，絕緣體材料可保留於n-型元件通道之下，以及在p-型元件通道之下的對應負型圖案中，以致於單一應變感應層可依需要在主動層上產生拉伸應變及壓縮應變二者。在步驟1201中絕緣體材料的圖案化去除，隨後亦可依序是步驟1203及1205，以如同上述般在挖空的絕緣體區域之不同部分中，沉積不同種類的應變感應層。
在本發明之特定實施例中，在步驟1203之SOI結構之背側上之應變感應層的沉積， 隨後是步驟1204之沉積的應變感應層之部分的圖案化去除。此步驟將因此形成挖空的應變層區域。在步驟1205中，第二應變層係沉積在SOI結構的背側上。結果，此第二應變層將填滿挖空的應變層區域。在步驟1206中，可去除未填滿挖空的應變層區域的多餘應變層，以形成SOI結構之均一背側表面。與其他實施例相較，此途徑具有特定有利的方面，因為僅有步驟1204中之應變層去除需要形成圖案。在步驟1206中之第二應變層去除可涉及機械研磨至均一程度，或藉由第一及第二應變層之化學組成差異來輔助的控制式蝕刻。此外，在步驟1203及1205中之應變感應層的實際沉積可為均一的。考慮例如化學汽相沉積之一些沉積形式並非總是能夠修正至詳細微影圖案化的事實，此途徑是有利的，因為其可以更有效率的方式達成詳細的圖案化。
雖然本發明之實施例已主要就其特定實施例來討論，亦可能有其他變化。所描述之系統的各種不同構形可用於取代或增添至在本文中呈現的構形。舉例而言，雖然所討論的元件通常係參考矽基板及氧化物絕緣體層，本發明可在任何形式之絕緣體上半導體晶圓、結構或元件上具有功用。舉例而言，本發明將與藍寶石上矽結構組合以產生功用。此外，本發明可使用例如CMOS、雙極、 BiCMOS、SiGe、GaAs、InGaAs、GaN之任何形式的技術，以及任何形式之半導體技術或化合物半導體技術以在電路上作用或操作。如上文中所述，絕緣體層不需要完全被去除。絕緣體層可完整地保留且散熱層可接著設置在絕緣體層之表面上。此外，整個絕緣體層可被薄化以取代完全被去除，或可形成含有殘餘的薄化絕緣體層之挖空的絕緣體區域。此外，可具有設置在本文中所述之該等層之間的額外材料層。半導體加工是高度精細的領域，且若絕對需要描述本發明以避免混淆的話，該等層為僅於本文中述及者。舉例而言，可具有設置在主動層上之鈍化層，以防止電路與其環境反應。此外，例如當描述主動層或絕緣體層時使用辭語“層”，並未排除此層可由一種以上的材料組成。舉例而言，除了位在SOI結構之整個主動層之下的二氧化矽絕緣體以外，在主動電路的金屬線下可具有玻璃或一些其他絕緣體層。然而，專門術語“絕緣體層”可涵蓋玻璃及二氧化矽絕緣體之整個結構。
熟習該項技術者將瞭解到，前述說明僅供例示，且未意欲限制本發明。在本案揭露中無一內容表明本發明係受限於要求特定形式之半導體加工的系統或受限於積體電路。功能可依所欲藉由硬體或軟體在執行。一般而言，任何圖式僅意欲 表示一種可能的構形，且可能有許多變化。熟習該項技術者將亦可瞭解與本發明一致的方法及系統，係適用於包含任何有關來自電子或光子元件之熱的散熱之廣範圍應用。
雖然說明書已就本發明之特定實施例詳細描述，應瞭解到，熟習該項技術者，在達到瞭解前述內容後，可容易地思及此等實施例之改變、變化及等效物。本發明的此等及其他改良及變化，可由熟習該項技術者實施，而未偏離更明確地描述於附帶之申請專利範圍中之本發明的精神及範疇。
103‧‧‧主動層
104‧‧‧電路
107‧‧‧操作晶圓
200‧‧‧散熱層

Claims (23)

  1. 一種製造一積體電路之方法，該方法包含以下步驟：在一絕緣體上半導體晶圓之一主動層中形成複數個主動裝置，該等主動裝置包含n-型通道電晶體和p-型通道電晶體，每個主動裝置具有一通道；其中該等複數個主動裝置主要(predominantly)為n-型通道電晶體或主要為p-型通道電晶體；自設置在該絕緣體上半導體晶圓之一背側上的一基板層去除一基板材料；以及在接近至少一個n-型通道電晶體和至少一個p-型通道電晶體之該通道處或在至少一個n-型通道電晶體和至少一個p-型通道電晶體之該通道的一部分中形成單一層的應變感應材料。
  2. 如請求項1所述之方法，該方法進一步包含以下步驟：選擇該應變感應材料之一材料或一排列中之一者，該應變感應材料提供在該n-型通道電晶體或該p-型通道電晶體中之電荷載子之一移動率之一增加。
  3. 如請求項1所述之方法，該方法進一步包含以下步驟：在形成該應變感應材料之前，自該絕緣體上半導體晶圓之該背側去除一絕緣 體材料。
  4. 如請求項1所述之方法，其中形成該應變感應材料之步驟在該絕緣體上半導體晶圓之該背側上形成變化構形。
  5. 如請求項1所述之方法，其中形成該應變感應材料之步驟選擇性地形成一機械拉伸應變感應材料和一壓縮應變感應材料中之至少一者。
  6. 如請求項1所述之方法，其中用來形成該應變感應材料的一材料係選擇自包含下列項目之群組：氮化矽、氮化鋁及類鑽碳。
  7. 如請求項6所述之方法，該方法進一步包含以下步驟：改變條件，其中在該等條件下將該材料沉積以在該應變感應材料中產生一壓縮或拉伸應變。
  8. 如請求項1所述之方法，該方法進一步包含以下步驟：將該應變感應材料排列成不同圖案，該等圖案在與電荷載子之流動相平行或相垂直的方向上產生雙軸應變或單軸應變。
  9. 如請求項1所述之方法，該方法進一步包含以下步驟：將該應變感應材料排列成選擇自包含下列項目之群組之圖案：圍繞該主動裝置之一閘極之一圖案、圍繞具有寬度相對於長度的比例大的該主動裝置之該閘極之一圖案、橫向 的一條紋圖案及沿著該閘極之一側形成的一條紋圖案。
  10. 如請求項1所述之方法，該方法進一步包含以下步驟：針對在該主動層中的主動裝置之一子集來排列該應變感應材料。
  11. 如請求項1所述之方法，該方法進一步包含以下步驟：針對該應變感應材料使用一材料，該材料具有大於50W/m * K的導熱性。
  12. 一種積體電路產品，該積體電路產品係根據請求項1之方法而產生。
  13. 一種製造一半導體裝置之方法，該方法包含以下步驟：在一絕緣體上半導體晶圓之一主動層中形成複數個主動裝置，該等主動裝置包含n-型通道電晶體和p-型通道電晶體，每個主動裝置具有一通道和一閘極；其中該等複數個主動裝置主要為n-型通道電晶體或主要為p-型通道電晶體；以及在形成該等主動裝置之步驟之後，形成單一層的應變感應材料，該應變感應材料係位於(i)在接近至少一個n-型通道電晶體和至少一個p-型通道電晶體之該通道處或在至少一個n-型通道電晶體和至少一個p-型通道電晶體之該通道中，及(ii)在自該閘極的該通道之一相對側上。
  14. 如請求項13所述之方法，該方法進一步包含以下步驟：自該絕緣體上半導體晶圓之一背側去除一絕緣體材料。
  15. 如請求項14所述之方法，其中去除該絕緣體材料之步驟將在形成該應變感應材料之前自該絕緣體上半導體晶圓之該背側去除該絕緣體材料。
  16. 如請求項13所述之方法，其中形成該應變感應材料之步驟在該絕緣體上半導體晶圓之一背側上形成變化構形。
  17. 如請求項13所述之方法，其中形成該應變感應材料之步驟選擇性地形成一機械拉伸應變感應材料和一壓縮應變感應材料中之至少一者。
  18. 如請求項13所述之方法，其中用來形成該應變感應材料的一材料係選擇自包含下列項目之群組：氮化矽、氮化鋁及類鑽碳。
  19. 一種半導體裝置產品，該半導體裝置產品係根據請求項13之方法而產生。
  20. 一種製造一積體電路之方法，該方法包含以下步驟：在一絕緣體上半導體晶圓之一主動層中形成複數個主動裝置，該等主動裝置包含n-型通道電晶體和p-型通道電晶體，每個主動裝置具有一 通道；自設置在該絕緣體上半導體晶圓之一背側上的一基板層去除一基板材料；自該絕緣體上半導體晶圓之該背側去除一絕緣體材料；以及在去除一絕緣體材料之後，在接近至少一個n-型通道電晶體和至少一個p-型通道電晶體之該通道處或在至少一個n-型通道電晶體和至少一個p-型通道電晶體之該通道的一部分中，形成單一層的應變感應材料；其中自該絕緣體上半導體之該背側去除一絕緣體材料之步驟包含將該絕緣體材料去除成一圖案，以使得該圖案和該應變感應材料協力(act in tandem)以增進在該等n-型通道電晶體和該等p-型通道電晶體中的電荷載子之移動率。
  21. 如請求項20所述之方法，其中用來形成該應變感應材料的一材料係選擇自包含下列項目之群組：氮化矽、氮化鋁及類鑽碳。
  22. 如請求項21所述之方法，該方法進一步包含以下步驟：改變條件，其中在該等條件下將該材料沉積以在該應變感應材料中產生一壓縮或拉伸應變。
  23. 一種製造一積體電路之方法，該方法包含以下步驟： 在一絕緣體上半導體晶圓之一主動層中形成複數個主動裝置，該等主動裝置包含n-型通道電晶體和p-型通道電晶體，每個主動裝置具有一通道；自設置在該絕緣體上半導體晶圓之一背側上的一基板層去除一基板材料；在接近至少一個n-型通道電晶體或至少一個p-型通道電晶體之該通道處或在至少一個n-型通道電晶體或至少一個p-型通道電晶體之該通道的一部分中，形成一第一層的應變感應材料；去除該第一層的應變感應材料之部分；以及在該第一層的應變感應材料之一所去除部分中形成一第二層的應變感應材料，其中這兩層的應變感應材料基本上是共平面。
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