CN102318041B - 用于电沉积铜的工艺,在穿硅通孔(tsv)中的芯片间、芯片到晶片间和晶片间的互连 - Google Patents

用于电沉积铜的工艺,在穿硅通孔(tsv)中的芯片间、芯片到晶片间和晶片间的互连 Download PDF

Info

Publication number
CN102318041B
CN102318041B CN200980156992.4A CN200980156992A CN102318041B CN 102318041 B CN102318041 B CN 102318041B CN 200980156992 A CN200980156992 A CN 200980156992A CN 102318041 B CN102318041 B CN 102318041B
Authority
CN
China
Prior art keywords
copper
tsvs
wafer
technique
deposition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN200980156992.4A
Other languages
English (en)
Chinese (zh)
Other versions
CN102318041A (zh
Inventor
罗伯特·F·普赖塞尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Atotech Deutschland GmbH and Co KG
Original Assignee
Atotech Deutschland GmbH and Co KG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atotech Deutschland GmbH and Co KG filed Critical Atotech Deutschland GmbH and Co KG
Publication of CN102318041A publication Critical patent/CN102318041A/zh
Application granted granted Critical
Publication of CN102318041B publication Critical patent/CN102318041B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D21/00Processes for servicing or operating cells for electrolytic coating
    • C25D21/16Regeneration of process solutions
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00Electroplating: Baths therefor
    • C25D3/02Electroplating: Baths therefor from solutions
    • C25D3/38Electroplating: Baths therefor from solutions of copper
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02Electroplating of selected surface areas
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/18Electroplating using modulated, pulsed or reversing current
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/60Electroplating characterised by the structure or texture of the layers
    • C25D5/605Surface topography of the layers, e.g. rough, dendritic or nodular layers
    • C25D5/611Smooth layers
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/60Electroplating characterised by the structure or texture of the layers
    • C25D5/615Microstructure of the layers, e.g. mixed structure
    • C25D5/617Crystalline layers
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00Electroplating characterised by the article coated
    • C25D7/12Semiconductors
    • C25D7/123Semiconductors first coated with a seed layer or a conductive layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05573Single external layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13025Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Electroplating And Plating Baths Therefor (AREA)
CN200980156992.4A 2009-02-17 2009-12-16 用于电沉积铜的工艺,在穿硅通孔(tsv)中的芯片间、芯片到晶片间和晶片间的互连 Expired - Fee Related CN102318041B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/372,113 2009-02-17
US12/372,113 US20100206737A1 (en) 2009-02-17 2009-02-17 Process for electrodeposition of copper chip to chip, chip to wafer and wafer to wafer interconnects in through-silicon vias (tsv)
PCT/IB2009/007793 WO2010094998A1 (en) 2009-02-17 2009-12-16 Process for electrodeposition of copper chip to chip, chip to wafer and wafer to wafer interconnects in through-silicon vias (tsv)

Publications (2)

Publication Number Publication Date
CN102318041A CN102318041A (zh) 2012-01-11
CN102318041B true CN102318041B (zh) 2014-05-07

Family

ID=42126356

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200980156992.4A Expired - Fee Related CN102318041B (zh) 2009-02-17 2009-12-16 用于电沉积铜的工艺,在穿硅通孔(tsv)中的芯片间、芯片到晶片间和晶片间的互连

Country Status (6)

Country Link
US (1) US20100206737A1 (enExample)
EP (1) EP2399281B1 (enExample)
JP (1) JP5743907B2 (enExample)
CN (1) CN102318041B (enExample)
TW (1) TW201034120A (enExample)
WO (1) WO2010094998A1 (enExample)

Families Citing this family (64)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7816181B1 (en) * 2009-06-30 2010-10-19 Sandisk Corporation Method of under-filling semiconductor die in a die stack and semiconductor device formed thereby
US9714474B2 (en) * 2010-04-06 2017-07-25 Tel Nexx, Inc. Seed layer deposition in microscale features
US20120024713A1 (en) * 2010-07-29 2012-02-02 Preisser Robert F Process for electrodeposition of copper chip to chip, chip to wafer and wafer to wafer interconnects in through-silicon vias (tsv) with heated substrate and cooled electrolyte
US20120056331A1 (en) * 2010-09-06 2012-03-08 Electronics And Telecommunications Research Institute Methods of forming semiconductor device and semiconductor devices formed by the same
US8786066B2 (en) * 2010-09-24 2014-07-22 Intel Corporation Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming same
EP2668317B1 (en) * 2011-01-26 2017-08-23 MacDermid Enthone Inc. Process for filling vias in the microelectronics
US8970043B2 (en) 2011-02-01 2015-03-03 Maxim Integrated Products, Inc. Bonded stacked wafers and methods of electroplating bonded stacked wafers
JP5754209B2 (ja) * 2011-03-31 2015-07-29 大日本印刷株式会社 半導体装置の製造方法
US8753981B2 (en) 2011-04-22 2014-06-17 Micron Technology, Inc. Microelectronic devices with through-silicon vias and associated methods of manufacturing
EP2518187A1 (en) * 2011-04-26 2012-10-31 Atotech Deutschland GmbH Aqueous acidic bath for electrolytic deposition of copper
US8691691B2 (en) 2011-07-29 2014-04-08 International Business Machines Corporation TSV pillar as an interconnecting structure
US8894868B2 (en) 2011-10-06 2014-11-25 Electro Scientific Industries, Inc. Substrate containing aperture and methods of forming the same
CN102376641B (zh) * 2011-11-24 2013-07-10 上海华力微电子有限公司 铜填充硅通孔的制作方法
US20130140688A1 (en) * 2011-12-02 2013-06-06 Chun-Hung Chen Through Silicon Via and Method of Manufacturing the Same
CN102569251B (zh) * 2012-02-22 2014-07-02 华进半导体封装先导技术研发中心有限公司 三维封装用金属间化合物填充的垂直通孔互连结构及制备方法
US20130249047A1 (en) * 2012-03-26 2013-09-26 Nanya Technology Corporation Through silicon via structure and method for fabricating the same
CN103378057B (zh) * 2012-04-20 2016-06-29 南亚科技股份有限公司 半导体芯片以及其形成方法
CN103378059B (zh) * 2012-04-27 2016-04-27 南亚科技股份有限公司 穿硅通孔与其形成方法
US9006896B2 (en) * 2012-05-07 2015-04-14 Xintec Inc. Chip package and method for forming the same
KR20150022987A (ko) * 2012-06-07 2015-03-04 렌슬러 폴리테크닉 인스티튜트 3-차원 집적에서 tsv(through silicon vias) 스트레스를 감소시키기 위한 컨포멀한 코팅 탄성 쿠션의 이용
CN102703938B (zh) * 2012-06-07 2015-04-22 上海交通大学 硫酸铜电镀液的应力消除剂
WO2014012381A1 (zh) * 2012-07-17 2014-01-23 上海交通大学 铜互连微柱力学性能原位压缩试样及其制备方法
CN103715132B (zh) * 2012-09-29 2017-12-01 中芯国际集成电路制造(上海)有限公司 金属互连结构的形成方法
US8933564B2 (en) * 2012-12-21 2015-01-13 Intel Corporation Landing structure for through-silicon via
CN103060859B (zh) * 2012-12-27 2015-04-22 建滔(连州)铜箔有限公司 用于改善毛箔毛面锋形的添加剂和电解铜箔生产工艺
CN103103585B (zh) * 2012-12-29 2015-09-16 上海新阳半导体材料股份有限公司 一种用于铜互连的高速凸点电镀方法
EP2754732B1 (en) * 2013-01-15 2015-03-11 ATOTECH Deutschland GmbH Aqueous composition for etching of copper and copper alloys
KR101992224B1 (ko) * 2013-01-15 2019-06-24 미쯔비시 가스 케미칼 컴파니, 인코포레이티드 실리콘 에칭액 및 에칭방법 그리고 미소전기기계소자
KR20140094061A (ko) * 2013-01-16 2014-07-30 주식회사 잉크테크 연속 도금 장치 및 연속 도금 방법
US8933562B2 (en) 2013-01-24 2015-01-13 International Business Machines Corporation In-situ thermoelectric cooling
US9470710B2 (en) * 2013-02-27 2016-10-18 Texas Instruments Incorporated Capacitive MEMS sensor devices
CN103280427B (zh) * 2013-06-13 2016-08-10 华进半导体封装先导技术研发中心有限公司 一种tsv正面端部互连工艺
CN103290438B (zh) * 2013-06-25 2015-12-02 深圳市创智成功科技有限公司 用于晶圆级封装的电镀铜溶液及电镀方法
DE112013002916T5 (de) * 2013-06-27 2015-03-05 Intel IP Corporation Hochleitende, hochfrequente Durchkontaktierung für elektronische Anlagen
CN103361681B (zh) * 2013-08-08 2016-11-16 上海新阳半导体材料股份有限公司 能改变tsv微孔镀铜填充方式的添加剂c及包含其的电镀液
US20150069609A1 (en) * 2013-09-12 2015-03-12 International Business Machines Corporation 3d chip crackstop
KR20150057148A (ko) * 2013-11-18 2015-05-28 삼성전자주식회사 반도체 장치
CN103668356B (zh) * 2013-12-17 2016-04-13 上海交通大学 在铜互连硫酸铜镀液中添加Fe2+和Fe3+的电镀方法
CN103695973B (zh) * 2013-12-17 2016-07-06 上海交通大学 在铜互连甲基磺酸铜镀液中添加Fe2+和Fe3+的电镀方法
US9373613B2 (en) * 2013-12-31 2016-06-21 Skyworks Solutions, Inc. Amplifier voltage limiting using punch-through effect
CN104465564B (zh) * 2014-01-06 2017-09-15 昆山西钛微电子科技有限公司 晶圆级芯片tsv封装结构及其封装方法
CN103887232B (zh) * 2014-04-04 2016-08-24 华进半导体封装先导技术研发中心有限公司 改善tsv金属填充均匀性的方法
US9515035B2 (en) 2014-12-19 2016-12-06 International Business Machines Corporation Three-dimensional integrated circuit integration
US10068181B1 (en) * 2015-04-27 2018-09-04 Rigetti & Co, Inc. Microwave integrated quantum circuits with cap wafer and methods for making the same
US20170145577A1 (en) * 2015-11-19 2017-05-25 Rohm And Haas Electronic Materials Llc Method of electroplating low internal stress copper deposits on thin film substrates to inhibit warping
FR3046878B1 (fr) * 2016-01-19 2018-05-18 Kobus Sas Procede de fabrication d'une interconnexion comprenant un via s'etendant au travers d'un substrat
CN107706146B (zh) * 2016-08-08 2020-07-28 中芯国际集成电路制造(上海)有限公司 半导体器件的制备方法
CN106757191B (zh) * 2016-11-23 2019-10-01 苏州昕皓新材料科技有限公司 一种具有高择优取向的铜晶体颗粒及其制备方法
US11121301B1 (en) 2017-06-19 2021-09-14 Rigetti & Co, Inc. Microwave integrated quantum circuits with cap wafers and their methods of manufacture
US10475808B2 (en) 2017-08-30 2019-11-12 Macronix International Co., Ltd. Three dimensional memory device and method for fabricating the same
CN108615704B (zh) * 2018-03-27 2020-05-08 中国科学院上海微系统与信息技术研究所 一种硅通孔互连的制作工艺、由此形成的硅通孔互连结构及其应用
CN108754555B (zh) * 2018-08-29 2020-04-28 广东天承科技有限公司 一种电镀液及其电镀方法
US10867855B2 (en) 2019-05-13 2020-12-15 Honeywell International Inc. Through silicon via fabrication
KR20250151620A (ko) 2019-08-19 2025-10-21 아토테크 도이칠란트 게엠베하 운트 콤파니 카게 구리로 충전된 마이크로비아들을 포함하는 고밀도 상호연결 인쇄 회로 기판을 제조하는 방법
US12063751B2 (en) 2019-08-19 2024-08-13 Atotech Deutschland GmbH & Co. KG Manufacturing sequences for high density interconnect printed circuit boards and a high density interconnect printed circuit board
CN110453255B (zh) * 2019-08-30 2020-10-09 广州皓悦新材料科技有限公司 一种具有高深镀能力的vcp镀铜光亮剂及其制备方法
CN111041535A (zh) * 2019-12-25 2020-04-21 浙江振有电子股份有限公司 一种连续移动式电镀通孔双面板的方法
CN111155152B (zh) * 2019-12-26 2022-11-01 西安泰金工业电化学技术有限公司 一种用于pcb水平电镀工序中降低生产成本的方法
TWI741466B (zh) 2019-12-27 2021-10-01 鉑識科技股份有限公司 利用水/醇溶性有機添加劑製備之奈米雙晶層及其製備方法
CN112018078B (zh) * 2020-07-29 2022-10-25 复旦大学 一种铜互连结构及其制作方法
CN112151504B (zh) * 2020-08-17 2022-04-29 复旦大学 一种带有封孔层的铜互连结构及其制备方法
CN113174620B (zh) * 2021-04-22 2022-05-03 浙江集迈科微电子有限公司 一种镀液流速加强型tsv金属柱的电镀方法
FI20215520A1 (en) * 2021-05-04 2022-11-05 Iqm Finland Oy Superconducting vias in the substrate
CN115573009A (zh) * 2022-10-17 2023-01-06 苏州苏纳光电有限公司 高深宽比tsv结构、其制备方法与应用

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6793795B1 (en) * 1999-01-21 2004-09-21 Atotech Deutschland Gmbh Method for galvanically forming conductor structures of high-purity copper in the production of integrated circuits
US20060216921A1 (en) * 2005-03-25 2006-09-28 Osamu Kato Through conductor and its manufacturing method

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4344387C2 (de) * 1993-12-24 1996-09-05 Atotech Deutschland Gmbh Verfahren zur elektrolytischen Abscheidung von Kupfer und Anordnung zur Durchführung des Verfahrens
DE19545231A1 (de) * 1995-11-21 1997-05-22 Atotech Deutschland Gmbh Verfahren zur elektrolytischen Abscheidung von Metallschichten
DE19653681C2 (de) * 1996-12-13 2000-04-06 Atotech Deutschland Gmbh Verfahren zur elektrolytischen Abscheidung von Kupferschichten mit gleichmäßiger Schichtdicke und guten optischen und metallphysikalischen Eigenschaften und Anwendung des Verfahrens
US20040045832A1 (en) * 1999-10-14 2004-03-11 Nicholas Martyak Electrolytic copper plating solutions
JP2001267726A (ja) * 2000-03-22 2001-09-28 Toyota Autom Loom Works Ltd 配線基板の電解メッキ方法及び配線基板の電解メッキ装置
JP2004119606A (ja) * 2002-09-25 2004-04-15 Canon Inc 半導体基板の貫通孔埋め込み方法および半導体基板
DE10311575B4 (de) * 2003-03-10 2007-03-22 Atotech Deutschland Gmbh Verfahren zum elektrolytischen Metallisieren von Werkstücken mit Bohrungen mit einem hohen Aspektverhältnis
US20090008792A1 (en) * 2004-11-19 2009-01-08 Industrial Technology Research Institute Three-dimensional chip-stack package and active component on a substrate
ATE484943T1 (de) * 2006-03-30 2010-10-15 Atotech Deutschland Gmbh Elektrolytisches verfahren zum füllen von löchern und vertiefungen mit metallen
KR100945504B1 (ko) * 2007-06-26 2010-03-09 주식회사 하이닉스반도체 스택 패키지 및 그의 제조 방법
US7939941B2 (en) * 2007-06-27 2011-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of through via before contact processing
US7825517B2 (en) * 2007-07-16 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for packaging semiconductor dies having through-silicon vias
KR101185886B1 (ko) * 2007-07-23 2012-09-25 삼성전자주식회사 유니버설 배선 라인들을 포함하는 반도체 칩, 반도체패키지, 카드 및 시스템
TWI335059B (en) * 2007-07-31 2010-12-21 Siliconware Precision Industries Co Ltd Multi-chip stack structure having silicon channel and method for fabricating the same
US7902069B2 (en) * 2007-08-02 2011-03-08 International Business Machines Corporation Small area, robust silicon via structure and process
TWI341554B (en) * 2007-08-02 2011-05-01 Enthone Copper metallization of through silicon via
US7776741B2 (en) * 2008-08-18 2010-08-17 Novellus Systems, Inc. Process for through silicon via filing

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6793795B1 (en) * 1999-01-21 2004-09-21 Atotech Deutschland Gmbh Method for galvanically forming conductor structures of high-purity copper in the production of integrated circuits
US20060216921A1 (en) * 2005-03-25 2006-09-28 Osamu Kato Through conductor and its manufacturing method

Also Published As

Publication number Publication date
EP2399281B1 (en) 2016-04-20
EP2399281A1 (en) 2011-12-28
TW201034120A (en) 2010-09-16
JP5743907B2 (ja) 2015-07-01
JP2012518084A (ja) 2012-08-09
CN102318041A (zh) 2012-01-11
US20100206737A1 (en) 2010-08-19
WO2010094998A1 (en) 2010-08-26

Similar Documents

Publication Publication Date Title
CN102318041B (zh) 用于电沉积铜的工艺,在穿硅通孔(tsv)中的芯片间、芯片到晶片间和晶片间的互连
EP2611950B1 (en) Process for electrodeposition of copper chip to chip chip to wafer and wafer to wafer interconnects in through-silicon vias (tsv), with heated substrate and cooled electrolyte
KR101105485B1 (ko) 관통전극형 채움 장치 및 방법
US12424453B2 (en) Low temperature direct copper-copper bonding
KR101807313B1 (ko) 듀얼 스테이트 저해제를 지닌 전해질을 이용한 관통형 실리콘 비아 충진
US9376758B2 (en) Electroplating method
TW201919150A (zh) 通遮罩互連線製造中的電氧化金屬移除
CN104651893A (zh) 用于电镀的碱预处理
JP2009527912A (ja) 半導体デバイスの製造において直接銅めっきし、かつ充填して相互配線を形成するための方法及び組成物
TWI513863B (zh) 銅電鍍組合物及使用此組合物填充半導體基板中之凹洞之方法
KR101818655B1 (ko) 실리콘 관통전극의 무결함 충전방법 및 충전방법에 사용되는 구리 도금액
US20130249096A1 (en) Through silicon via filling
CN103003473B (zh) 刻蚀铜和铜合金的方法
JP4472673B2 (ja) 銅配線の製造方法及び銅めっき用電解液
US11598016B2 (en) Electrochemical plating system and method of using
TW200536965A (en) Copper plating of semiconductor devices using intermediate immersion step

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20140507

Termination date: 20181216