CN102203923B - 形成多个晶体管栅极的方法及形成具有至少两种不同功函数的多个晶体管栅极的方法 - Google Patents

形成多个晶体管栅极的方法及形成具有至少两种不同功函数的多个晶体管栅极的方法 Download PDF

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CN102203923B
CN102203923B CN200980143451.8A CN200980143451A CN102203923B CN 102203923 B CN102203923 B CN 102203923B CN 200980143451 A CN200980143451 A CN 200980143451A CN 102203923 B CN102203923 B CN 102203923B
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古尔特杰·S·桑胡
马克·基尔鲍赫
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Micron Technology Inc
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Abstract

本发明涉及一种形成具有至少两种不同功函数的多个晶体管栅极的方法，其包含在衬底上方形成具有不同宽度的第一及第二晶体管栅极，其中第一宽度比第二宽度窄。在所述衬底上方包含在所述第一及第二栅极上方沉积材料。在蚀刻室内，从所述第一及第二栅极两者上方蚀刻所述材料以暴露所述第一栅极的导电材料且减小接纳于所述第二栅极上方的所述材料的厚度但仍使所述第二栅极被所述材料覆盖。在所述蚀刻之后原位地在所述蚀刻室内，使所述衬底在至少300℃的衬底温度下经受包括金属的等离子以将所述金属扩散到所述第一栅极中，从而相比于所述第二栅极的功函数修改所述第一栅极的功函数。

Description

形成多个晶体管栅极的方法及形成具有至少两种不同功函数的多个晶体管栅极的方法
技术领域
本文中所揭示的实施例涉及形成多个晶体管栅极的方法，所述多个晶体管栅极可具有或可不具有至少两种不同功函数。
背景技术
场效应晶体管是集成电路制作中所使用的一种类型的电子组件。此类场效应晶体管包含在其之间接纳有沟道区域的一对源极/漏极区域。接近所述沟道区域接纳栅极且通过栅极电介质将所述栅极与沟道区域分离。通过将适合电压施加到晶体管的栅极，沟道区域变得导电。因此，在将适合阈值电压施加到所述栅极之后，晶体管从非导通状态切换为导通状态。期望将晶体管的阈值电压保持为小且还期望将晶体管的功率消耗保持为低。栅极的可确定阈值电压的一个重要性质是功函数。正是栅极的功函数连同沟道区域的掺杂水平一起确定场效应晶体管装置的阈值电压。为了将晶体管的阈值电压保持为小且将功率消耗保持为低，期望栅极材料的功函数约等于沟道区域的材料的功函数。
通常，并非集成电路的所有晶体管均具有相同构造或材料。因此，应认识到且通常期望将不同晶体管栅极制作为具有至少两种不同功函数。提供不同功函数的一种方式是提供待由不同材料形成的不同栅极电极。举例来说，对于导电多晶硅，使用不同导电性增强掺杂剂及浓度可为不同晶体管提供不同功函数。对于金属栅极，还已知使用不同的金属或金属合金中的不同金属量会影响成品装置的功函数。
附图说明
图1是根据本发明一实施例的工艺中的衬底的示意性截面图。
图2是继图1所展示步骤之后的处理步骤处的图1衬底的视图。
图3是继图2所展示步骤之后的处理步骤处的图2衬底的视图。
图4是继图3所展示步骤之后的处理步骤处的图3衬底的视图。
图5是继图4所展示步骤之后的替代处理步骤处的图3衬底的视图。
图6是根据本发明一实施例的工艺中的另一衬底的示意性截面图。
图7是继图6所展示步骤之后的处理步骤处的图6衬底的视图。
图8是继图7所展示步骤之后的处理步骤处的图7衬底的视图。
图9是继图8所展示步骤之后的处理步骤处的图8衬底的视图。
图10是根据本发明一实施例的工艺中的另一衬底的示意性截面图。
图11是继图10所展示步骤之后的处理步骤处的图10衬底的视图。
图12是继图11所展示步骤之后的处理步骤处的图11衬底的视图。
图13是继图12所展示步骤之后的处理步骤处的图12衬底的视图。
图14是继图13所展示步骤之后的处理步骤处的图13衬底的视图。
图15是继图14所展示步骤之后的处理步骤处的图14衬底的视图。
图16是根据本发明一实施例的工艺中的另一衬底的示意性截面图。
图17是继图16所展示步骤之后的处理步骤处的图16衬底的视图。
图18是继图17所展示步骤之后的处理步骤处的图17衬底的视图。
具体实施方式
参考图1到图4来描述形成具有至少两种不同功函数的多个晶体管栅极的第一实例性方法。参考图1，一般来说用参考编号10指示衬底(其可为半导体衬底)。在本文件的上下文中，术语“半导体衬底”或“半导电衬底”被定义为意指包括半导电材料的任一构造，包含但不限于例如半导电晶片(单独地或以其上包括其它材料的组合件形式)及半导电材料层(单独地或以包括其它材料的组合件形式)的块体半导电材料。术语“衬底”是指任一支撑结构，包含但不限于上文所描述的半导电衬底。衬底10包含半导电区域12，在所述半导电区域内源极/漏极及沟道区域(未展示)已被制作或将被制作。实例性材料12为用一种或一种以上导电性增强杂质适合地掺杂到一个或一个以上浓度的单晶硅。衬底10可包含其它层或区域，例如并非是本发明的特定材料的沟槽隔离件(未展示)。
已在衬底12上方形成栅极电介质14。栅极电介质14的实例性厚度是从约3纳米到约10纳米，其中约5纳米作为特定实例。已在衬底12/14上方形成第一晶体管栅极16及第二晶体管栅极18。第一栅极16具有第一宽度17且第二栅极18具有第二宽度19，其中第一宽度17比第二宽度19窄。在所描绘的实施例中，已在衬底12/14上方形成多个第一栅极16及多个第二栅极18，其中第一栅极16已形成于第一区20内且第二栅极18已形成于不同第二区22内。并非制作于第一区20内的所有栅极都一定具有相同材料、大小或形状，且并非制作于第二区22内的所有晶体管栅极都一定具有相同材料、大小或形状。实例性第一宽度17是从约20纳米到约75纳米，其中约50纳米作为特定实例。实例性宽度19是从约40纳米到约200纳米，其中约150纳米作为特定实例。
在本文件的上下文中，“栅极”或“晶体管栅极”单独地指代场效应晶体管栅极构造的导电部分，且栅极构造可包含额外材料，例如绝缘侧壁间隔件、绝缘顶盖及/或栅极电介质。将实例性栅极16、18展示为不具有形成于其上方或其周围的绝缘间隔件或顶盖，且包括导电区域24。然而，可提供绝缘顶盖及/或间隔件。此外，可使用快闪及其它栅极构造。因此，导电区域24可包括晶体管的控制栅极区域或浮动栅极区域。导电区域24可为同质的或不同质的。实例性材料包含经导电掺杂多晶硅、导电金属化合物及一种或一种以上元素形式金属，包含多种元素形式金属的合金。实例性金属包含铂、钴、铱、钛、钨、钽、铝、铁、锆、钒及铪。
可通过任一现有或尚待开发的方式形成晶体管栅极16及18。一种技术包含光刻图案化及蚀刻，其中图1将对材料24的蚀刻描绘为已相对于栅极电介质14选择性地进行使得其保持横跨于半导电材料12上方的导电栅极中的邻近导电栅极之间。或者，可不选择性地进行所述处理或继续蚀刻以移除一些或所有栅极电介质14以使其不被接纳于栅极之间的衬底材料12上方。此外，图1描绘其中将晶体管栅极制作为具有相等厚度的实例，但也可使用多个厚度及/或配置。导电区域24的实例性厚度是从约10纳米到约100纳米，其中约75纳米作为特定实例。另外，图1描绘晶体管定向是平面的或水平的。还涵盖替代配置，例如垂直晶体管及/或形成于沟槽中的晶体管，且无论其是现有的还是尚待开发的。
参考图2，已在衬底10上方包含分别在第一及第二栅极16、18上方沉积材料28。材料28可为绝缘的、导电的(包含经导电掺杂半导电材料)或半导电的，包含此些性质的任一组合。实例包含二氧化硅、氮化硅、多晶硅、碳、氮化钛、氮化钽及氮化钨。可将材料28沉积为小于、等于或大于第一及第二栅极16、18中的每一者的厚度。无论如何，材料28可大致保形地或不保形地沉积于第一及第二栅极中的每一者上方，且可经沉积以具有平面或非平面最外表面。图2描绘其中已以大致保形方式将材料28沉积为具有非平面最外表面29且沉积为小于第一及第二栅极16、18中的每一者的厚度的厚度的实例。在一些实施例中，材料28具有与晶体管栅极16、18的导电区域24的最外部分的组成不同的组成。
参考图3，已将衬底10放置于蚀刻室内，且已从第一栅极16与第二栅极18两者上方蚀刻材料28。对材料28的蚀刻已有效地暴露第一栅极16的导电材料且减小接纳于第二栅极18上方的材料28的厚度但仍使第二栅极18被材料28覆盖。仅举例来说，实例性适合蚀刻室包含能够实现至少300℃的衬底温度的高温等离子蚀刻器，例如由加利福尼亚州圣克拉拉的应用材料公司(Applied Materials，Inc.of Santa Clara，California)出售的DPSII G3 HT等离子蚀刻反应器的蚀刻室及由加利福尼亚州菲蒙市的Lam研究公司(Lam Research Corporation of Fremont，California.)出售的2300Kiyo等离子蚀刻反应器的蚀刻室。此类反应器理想地实现提供高于300℃的衬底温度的等离子蚀刻，但可使用其它反应器。
在一个实施例中，可操作此类反应器以产生其中蚀刻动作已完全清除材料28以使其不被接纳于相比于较宽宽度晶体管栅极18宽度较窄的晶体管栅极16上方的实例性图3所描绘结果，其中在暴露较窄宽度晶体管栅极16时或在暴露较窄宽度晶体管栅极16之后不久便停止图3的蚀刻动作。将由技术人员取决于晶体管栅极宽度以及接纳于晶体管栅极16、18上方的材料28的组成及配置来选择适合条件及蚀刻化学品。理想地将蚀刻进行为具有相当高偏置的等离子蚀刻及经部分地物理驱动的蚀刻，使得接近窄宽度栅极16有效地形成小面以帮助比较大宽度栅极18更快地暴露此类特征。举例来说，在材料28基本上由碳组成的情况下，实例性条件包含从约250℃到约400℃的衬底温度、从约20毫托到约100毫托的室压、从约100W到约500W的电感功率及从约200W到约600W的偏置功率。实例性蚀刻气体包含从0sccm到约500sccm的Ar、He、Ne、Kr及Xe中的一者或其组合加上从约50sccm到约200sccm的N2以及从约250sccm到约100sccm的O2，其中N2与O2的体积比理想地为至少2∶1。可由技术人员针对用于材料28的除碳以外的材料来确定替代或重叠条件及化学品。蚀刻动作可或可不清除材料28以使其不横跨于晶体管栅极中的邻近晶体管栅极之间，其中图3描绘其中某种厚度的材料28保持横跨于邻近晶体管栅极之间的实例。
参考图4，且原位地在蚀刻室内并在图3的蚀刻之后，已使衬底10在至少300℃的衬底温度下经受包括金属的等离子以将所述金属扩散到第一栅极16中，从而相比于第二栅极18的功函数修改第一栅极16的功函数。在本文件的上下文中，原位动作需要所述经受在发生蚀刻的恰同一室中且在蚀刻与经受包括金属的等离子之间不从蚀刻室移除衬底的情况下进行。来自等离子的金属在开始扩散时可处于或可不处于等离子状态中，且因此可替代地呈气态。图4通过图式中的点画描绘到导电区域24中的金属扩散，其中点指示扩散的金属。此扩散可将或可不将金属同质地分布于整个导电区域24中，且无论导电区域24在暴露于含有金属的等离子之前是否同质。图4描绘其中第一栅极26的导电区域24内的金属扩散在整个区域24中不同质的实例。在此情况下，来自等离子的金属到导电区域24内的扩散理想地是扩散到栅极电介质14的所描绘上表面的至少约10纳米内以对栅极的功函数产生显著影响。此外，衬底所暴露到的等离子可包含一种或一种以上不同金属，以便可将一种或一种以上不同金属扩散到第一栅极16的导电区域24中。可由技术人员取决于对栅极的功函数的所要影响来选择及确定扩散的金属量。此外，此可基于例如以下因素来影响：等离子组成、等离子条件、暴露于等离子的时间及金属扩散到其中的导电区域的组成。
暴露于等离子也可或可不将来自等离子的金属扩散到接纳于第二栅极18上方的材料28中，且无论如何接纳于第二栅极18上方的材料28可或可不屏蔽所述金属中的任何金属以使其不在暴露于等离子期间扩散到第二栅极18中。图4描绘其中某种金属扩散已发生到材料28中但尚未有效地将任何金属扩散到第二栅极18中的任一者内的实例。图5描绘替代实施例衬底10a，已在适当之处利用来自第一描述实施例的相似编号，其中用后缀“a”来指示差异。在图5的等离子暴露中，金属的扩散已有效地扩散到材料28中且穿过材料28扩散到第二栅极18的导电区域24的最外部分中。无论如何，金属到第二栅极18内的任何此扩散均显著小于到第一栅极16中的扩散，以便相比于可对或可不对第二栅极18发生的任何功函数修改而修改第一栅极的功函数。
在(例如)第一栅极16的导电区域24包含元素形式金属或元素形式金属合金的情况下，将固有地增加功函数的实例性金属的扩散包含铂、钴及铱。此外，如果导电区域24在金属扩散之前包含包括铂、钴及铱中的一者或其组合的合金，那么更多铂、钴及铱到此类导电区域中的扩散将往往增加功函数。对应地，减小金属导电区域中的功函数的金属实例包含钛、钨、钽、铝及铁。此外，举例来说，如果导电区域24的最外部分包括经导电掺杂多晶硅，那么金属的扩散可将导电区域24的最外部分形成为包括导电金属硅化物。在一个理想实施例中，等离子中的金属是从有机金属化合物获得的。实例包含用于镍的四羰基镍、用于铁的二茂铁、用于钛的Ti(N(CH3)2)4及/或Ti(N(C2H5)2)4、用于钽的五(二甲基酰胺基)钽、用于钴的Co2(CO)8及用于铂的Pt(C2H5C5H4)(CH3)3。可替代地使用除有机金属化合物以外的化合物，举例来说，例如TiCl4的金属卤化物及其它化合物。电感耦合高温蚀刻反应器中的实例性条件包含从300℃到约400℃的衬底温度、从约5毫托到约200毫托的室压、从约100W到约1,000W的电感/源功率及从0W到约100W的偏置功率。含金属气体的实例性流率是从约10sccm到约200sccm，且从0sccm到约1,000sccm的适合惰性载体气体或许改进等离子均匀度及密度(即，Ar、He、Xe、Kr、Ne及/或N2)。可通过衬底搁置于其上的基座或其它支撑件的温度来控制衬底温度。举例来说，上文所描述的反应器可使其基座设定为300℃或高于300℃的温度，其中暴露于等离子期间的衬底温度取决于等离子的条件而高出约10℃到50℃。
图3的蚀刻及图4或图5的暴露于等离子可在材料28中的任何材料上方接纳或未接纳任何掩模的情况下发生，其中在图3到图5的所描绘横截面中材料28中的任何材料上方未展示/接纳掩模。
参考图6到图10关于衬底10b来描述形成具有至少两种不同功函数的多个晶体管栅极的另一实例性实施例方法。已在适当之处利用来自第一描述实施例的相似编号，其中用后缀“b”或用不同编号来指示差异。参考图6，已在衬底12/14上方形成包括导电区域33的多个晶体管栅极32。所述晶体管栅极可具有或可不具有至少两种不同宽度，其中在图6中将栅极32展示为具有相等宽度。图6的晶体管栅极可具有图1中的栅极16、18中的一者或另一者的实例性配置或者其它配置。仅举例来说，导电区域33的组成可与上文结合第一描述实施例的晶体管16、18所描述的组成相同。可相对于晶体管栅极32提供侧壁间隔件及/或顶盖。
已在晶体管栅极32的导电区域33上方提供材料34，其中此材料具有与导电区域33的最外部分的组成不同的组成。另外，实例性材料及属性包含上文关于第一描述实施例中的材料28所描述的那些材料及属性中的任一者。
参考图7，已形成掩模36以覆盖晶体管栅极32中的一些晶体管栅极且使晶体管栅极32中的其它晶体管栅极不被掩模36覆盖。可利用任一适合现有或尚待开发的掩模，且(举例来说)其中此掩模完全地或部分地牺牲。实例性材料包含具有或不具有一个或一个以上抗反射涂覆层的光致抗蚀剂。
参考图8，在适合蚀刻室内且在形成掩模36之后，已蚀刻材料34以使其不被接纳于未被掩模36覆盖的那些晶体管栅极32上。实例性室、化学品及条件包含上文结合用以产生图3衬底的处理所描述的那些室、化学品及条件中的任一者。可将或可不将材料34蚀刻为决不完全横跨于未被掩模36覆盖的经暴露晶体管栅极32中的邻近经暴露晶体管栅极之间。图8展示在蚀刻之后一些材料34横跨于经暴露栅极32中的邻近经暴露栅极之间。或者，可移除未被掩模36覆盖的所有材料34。
参考图9，且在图8的蚀刻之后原位地在蚀刻室内，已使衬底10b在至少300℃的衬底温度下经受包括金属的等离子。暴露于等离子已有效地将来自等离子的金属扩散到未被掩模36覆盖的晶体管栅极32的导电区域中以相比于被掩模36覆盖的晶体管栅极32的功函数修改未经覆盖晶体管栅极32的功函数。理想地，掩模36屏蔽来自等离子的金属中的任何金属以使其不扩散到经覆盖/经掩蔽晶体管栅极32的导电区域33中。实例性处理条件及化学品如上文结合图4及图5实施例所描述。因此，导电区域33在暴露于等离子之前及之后可为或可不为同质的，且金属可均匀地或仅部分地扩散到导电区域33中而仍影响并修改未被掩模36覆盖的晶体管栅极32的功函数。
形成多个晶体管栅极的方法的实施例可产生或可不产生不同栅极的至少两种不同功函数。如上文所描述的实例性实施例产生不同栅极的至少两种不同功函数。在图10到图15中关于衬底10c展示未必产生至少两种不同功函数的实施例的一个实例。已在适当之处利用来自第一描述实施例的相似编号，其中用后缀“c”或用不同编号来指示差异。参考图10，已在衬底12/14上方形成具有导电区域42的多个晶体管栅极40。实例性材料及构造包含上文关于图1到图9实施例所描述的那些材料及构造中的任一者。已在衬底12/14上方包含在晶体管栅极40中的邻近晶体管栅极上方且横跨于其之间沉积第一材料44。第一材料44具有与晶体管栅极40的导电区域42的最外部分的组成不同的组成。实例性材料及属性包含上文关于材料28/34所描述的那些材料及属性中的任一者。因此，举例来说，第一材料44可具有或可不具有平面最外表面，其中在图10中展示非平面最外表面。
参考图11，已蚀刻第一材料44以移除其从而使其不横跨于晶体管栅极40中的邻近晶体管栅极之间，但仍使第一材料44覆盖晶体管栅极40的顶部及侧壁。
参考图12，已在衬底上方包含在晶体管栅极40中的邻近晶体管栅极上方且横跨于其之间沉积第二材料46。第二材料46在组成上可与第一材料44的最外部分的组成相同或不同。此外，第二材料46可具有平面或非平面最外表面，其中在图12中展示平面最外表面。实例包含上文针对材料28所描述的那些实例中的任一者。可将第二材料46沉积为小于、等于或大于晶体管栅极40的厚度的厚度。
参考图13，已蚀刻第二材料46以使其不被接纳于晶体管栅极40中的至少一些晶体管栅极上方但保持横跨于晶体管栅极40中的邻近晶体管栅极之间。图13描绘其中已蚀刻第二材料44以使其不被接纳于所有晶体管栅极40上方的实施例。此蚀刻可在有掩蔽或无掩蔽的情况下进行。
参考图14，在蚀刻室内且在蚀刻第二材料46之后，已蚀刻第一材料44以使其不被接纳于晶体管栅极40中的至少一些晶体管栅极上方，其中图14描绘其中已蚀刻第一材料44以使其不被接纳于所有晶体管栅极40上方的实例。在第二材料46具有与第一材料44不同的组成的情况下，此蚀刻可或可不相对于此第二材料选择性地进行，其中如图14中所展示已进行选择性蚀刻。无论如何，在一个实施例中，如图13中所展示的对第二材料46的蚀刻可在与图14所描绘的蚀刻相同的蚀刻室内进行。此外，在一个实施例中，可在图13的第二材料蚀刻之后原位地发生如图14中所展示的对第一材料44的蚀刻以使其不被接纳于晶体管栅极40中的至少一些晶体管栅极上方。举例来说，可如上文结合图3及图8实施例中的任一者所描述的那样进行图14中的对第一材料44的实例性蚀刻。
参考图15，已使衬底10c在至少300℃的衬底温度下经受包括金属的等离子以将来自等离子的金属扩散到晶体管栅极40的导电区域42中从而修改晶体管栅极40的功函数。在如图14中所描绘的对第一材料44的蚀刻以使其不被接纳于晶体管栅极40中的至少一些晶体管栅极上方之后，已在蚀刻室内原位地进行此经受/暴露。实例性处理可如上文关于图4、图5及图9实施例中的任一者所描述。在如图14及图15所描绘的在暴露于等离子期间暴露所有晶体管栅极的情况下，所有晶体管栅极40的功函数将被修改。图16到图18描绘其中部分地由于在暴露于等离子期间第二材料中的一些材料保持在晶体管栅极中的一些晶体管栅极上方而产生至少两种不同功函数的实例性替代实施例。
具体来说，图16到图18描绘相对于替代实施例衬底10d的处理。已在适当之处利用来自上文所描述实施例的相似编号，其中用后缀“d”或用不同编号来指示差异。图16描绘继图12实施例之后的关于第二材料46d对衬底10d的处理。在图16中，已掩蔽第二材料46d(未展示掩模)同时已使第二材料46d中的一些第二材料向外暴露并对其进行蚀刻以使其在立面上仅接纳于晶体管栅极40中的一些晶体管栅极(具体来说，是图16中留下的三个所图解说明的栅极)上方。
图17描绘借此已蚀刻第一材料44以使其不被接纳于晶体管栅极40中的经暴露晶体管栅极上方且从而不接纳于仅一些晶体管栅极上方的后续处理。图18描绘其中原位地在其内发生了图17蚀刻的蚀刻室内已将衬底10d暴露于上文所描述的含金属等离子以将金属扩散到三个留下的所图解说明晶体管栅极40的导电区域42中的后续处理。
在一个实施例中，一种方法涵盖在衬底上方形成包括导电区域的多个晶体管栅极。所述晶体管栅极可具有或可不具有至少两种不同宽度。图1、图6或图16的上文所述及所示多个晶体管栅极中的任一者为此类晶体管栅极的实例。在晶体管栅极的导电区域上方提供材料，其中此材料具有与晶体管栅极的导电区域的最外部分的组成不同的组成。材料28、34、44及46中的任何一者或其组合为此材料的实例。此外，举例来说，第一材料44与第二材料46的组合(无论是否移除第一材料44以使其不完全横跨于晶体管栅极40之间)也是此实例性材料。因此，如本文件中此处及别处所使用的“材料”并不需要同质性且可包含多种不同组成及/或密度区域及/或层。
在蚀刻室内，以毯覆方式蚀刻所述材料以使其不被接纳于晶体管栅极的导电区域上方。实例性室、化学品及条件如上文关于对材料28、34及44中的任一者的蚀刻所描述。仅举例来说，从图13转到图14时的处理可被视为描绘此实施例：借此将材料44展示为以毯覆方式进行蚀刻以使其不被接纳于栅极40的导电区域42上方。或者，仅举例来说，可以毯覆方式蚀刻图2及图6的衬底以分别移除材料28及34以使其不被接纳于所有所描绘晶体管栅极的导电区域上方。
接着，在毯覆蚀刻之后原位地在蚀刻室内，使衬底在至少300℃的衬底温度下经受包括金属的等离子以将来自所述等离子的金属扩散到晶体管栅极的导电区域中从而修改晶体管栅极的功函数。起相同作用的实例性技术、条件及化学品可为如上文关于图4、图5、图9、图15及图18中的任一者的处理所描述的那些技术、条件及化学品。

Claims (21)

1.一种形成具有至少两种不同功函数的多个晶体管栅极的方法，其包括：
在衬底上方形成第一及第二晶体管栅极，所述第一晶体管栅极具有第一宽度且所述第二晶体管栅极具有第二宽度，所述第一宽度比所述第二宽度窄；
在所述衬底上方包含在所述第一及第二晶体管栅极上方沉积材料；
在蚀刻室内，蚀刻所述材料以暴露所述第一晶体管栅极的导电材料且使所述材料留在所述第二晶体管栅极上方；及
在所述蚀刻之后原位地在所述蚀刻室内，使所述衬底在至少300℃的衬底温度下经受等离子相金属或气相金属以将所述金属扩散到所述第一晶体管栅极中，从而相比于所述第二晶体管栅极的功函数修改所述第一晶体管栅极的功函数。
2.根据权利要求1所述的方法，其中所述蚀刻减小接纳于所述第二晶体管栅极上方的所述材料的厚度。
3.根据权利要求1所述的方法，其中接纳于所述第二晶体管栅极上方的所述材料屏蔽所述金属中的任何金属以使其不在所述经受期间扩散到所述第二晶体管栅极中。
4.根据权利要求1所述的方法，其中所述经受还将所述金属扩散到接纳于所述第二晶体管栅极上方的所述材料中。
5.根据权利要求4所述的方法，其中接纳于所述第二晶体管栅极上方的所述材料屏蔽所述金属中的任何金属以使其不在所述经受期间扩散到所述第二晶体管栅极中。
6.根据权利要求4所述的方法，其中所述金属中的一些金属还扩散到所述第二晶体管栅极中。
7.根据权利要求1所述的方法，其中在所述材料中的任何材料上方未接纳任何掩模的情况下发生所述蚀刻及所述经受。
8.一种形成具有至少两种不同功函数的多个晶体管栅极的方法，其包括：
在衬底上方形成多个晶体管栅极，所述晶体管栅极包括导电区域；
在所述晶体管栅极的所述导电区域上方提供材料，所述材料具有与所述晶体管栅极的所述导电区域的最外部分的组成不同的组成；
在提供所述材料之后，形成掩模以覆盖所述晶体管栅极中的一些晶体管栅极且使所述晶体管栅极中的其它晶体管栅极不被所述掩模覆盖；
在蚀刻室内且在形成所述掩模之后，蚀刻所述材料以使其不被接纳于未被所述掩模覆盖的所述晶体管栅极上方；及
在所述蚀刻之后原位地在所述蚀刻室内，使所述衬底在至少300℃的衬底温度下经受等离子相金属或气相金属以将所述金属扩散到未被所述掩模覆盖的所述晶体管栅极的所述导电区域中，从而相比于被所述掩模覆盖的所述晶体管栅极的功函数修改未被所述掩模覆盖的所述晶体管栅极的功函数。
9.根据权利要求8所述的方法，其中所述掩模屏蔽所述金属中的任何金属以使其不扩散到被所述掩模覆盖的所述晶体管栅极的所述导电区域中。
10.根据权利要求8所述的方法，其中所述导电区域的至少所述最外部分包括元素形式金属或元素形式金属合金中的至少一者。
11.根据权利要求10所述的方法，其中所有所述导电区域基本上由一种或一种以上元素形式金属或一元素形式金属合金组成。
12.根据权利要求8所述的方法，其中所述导电区域的至少所述最外部分包括经导电掺杂多晶硅，所述经受在所述晶体管栅极的未被所述掩膜覆盖的所述导电区域内形成导电金属硅化物。
13.一种形成多个晶体管栅极的方法，其包括：
在衬底上方形成多个晶体管栅极，所述晶体管栅极包括导电区域；
在所述衬底上方包含在所述晶体管栅极中的邻近晶体管栅极上方且横跨于其之间沉积第一材料，所述第一材料具有与所述晶体管栅极的所述导电区域的最外部分的组成不同的组成；
蚀刻所述第一材料以移除其从而使其不横跨于所述晶体管栅极中的邻近晶体管栅极之间但仍使所述第一材料覆盖所述晶体管栅极的顶部及侧壁；
在蚀刻所述第一材料之后，在所述衬底上方包含在所述晶体管栅极中的邻近晶体管栅极上方且横跨于其之间沉积第二材料；
蚀刻所述第二材料以使其不被接纳于所述晶体管栅极中的至少一些晶体管栅极上方但保持横跨于所述晶体管栅极中的邻近晶体管栅极之间；
在蚀刻室内且在蚀刻所述第二材料之后，蚀刻所述第一材料以使其不被接纳于所述晶体管栅极中的所述至少一些晶体管栅极上方；及
在所述蚀刻所述第一材料以使其不被接纳于所述晶体管栅极中的所述至少一些晶体管栅极上方之后原位地在所述蚀刻室内，使所述衬底在至少300℃的衬底温度下经受等离子相金属或气相金属以将所述金属扩散到所述晶体管栅极中的所述至少一些晶体管栅极的所述导电区域中从而修改所述晶体管栅极中的所述至少一些晶体管栅极的功函数。
14.根据权利要求13所述的方法，其中在所述室内发生所述第二材料的蚀刻，此后原位地发生所述蚀刻所述第一材料以使其不被接纳于所述晶体管栅极中的所述至少一些晶体管栅极上方。
15.根据权利要求13所述的方法，其包括将所述多个晶体管栅极形成为具有至少两种不同宽度。
16.一种形成多个晶体管栅极的方法，其包括：
在衬底上方形成多个晶体管栅极，所述晶体管栅极包括导电区域；
在所述晶体管栅极的所述导电区域上方提供材料，所述材料具有与所述晶体管栅极的所述导电区域的最外部分的组成不同的组成；
在蚀刻室内，以毯覆方式蚀刻所述材料以使其不被接纳于所述晶体管栅极的所述导电区域上方；及
在所述蚀刻之后原位地在所述蚀刻室内，使所述衬底在至少300℃的衬底温度下经受等离子相金属或气相金属以将所述金属扩散到所述晶体管栅极的所述导电区域中，从而修改所述晶体管栅极的功函数。
17.根据权利要求16所述的方法，其中所述金属不同质地分布于所述导电区域中，并且所述导电区域在所述经受之后为不同质的。
18.根据权利要求17所述的方法，其中所述导电区域在所述经受之前为同质的。
19.根据权利要求16所述的方法，其中所述导电区域在所述经受之前及之后为同质的。
20.根据任一前述权利要求所述的方法，其中所述经受为经受等离子相金属。
21.根据任一前述权利要求所述的方法，其中所述经受为经受气相金属。
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