CN102017138A - 裸片堆叠系统及方法 - Google Patents

裸片堆叠系统及方法 Download PDF

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Publication number
CN102017138A
CN102017138A CN2008800160357A CN200880016035A CN102017138A CN 102017138 A CN102017138 A CN 102017138A CN 2008800160357 A CN2008800160357 A CN 2008800160357A CN 200880016035 A CN200880016035 A CN 200880016035A CN 102017138 A CN102017138 A CN 102017138A
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China
Prior art keywords
nude film
conductive
coupled
nude
conduction
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CN2008800160357A
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CN102017138B (zh
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亨利·桑切斯
拉克西米纳拉扬·夏尔马
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Qualcomm Inc
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Qualcomm Inc
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Priority to CN201310219251.4A priority Critical patent/CN103296015B/zh
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Abstract

本发明揭示裸片堆叠系统及方法。在实施例中，裸片具有表面，所述表面包括钝化区域、至少一个导电接合垫区域及经定尺寸以容纳至少第二裸片的导电堆叠裸片容纳区域。

Description

裸片堆叠系统及方法
技术领域
本发明大体上涉及裸片堆叠。
背景技术
技术进步已产生更小且更强大的计算装置。举例来说，当前存在多种便携式个人计算装置，包括无线计算装置，例如便携式无线电话、个人数字助理(PDA)及寻呼装置，其体积小、重量轻且易于由用户携带。更明确地说，例如蜂窝式电话及因特网协议(IP)电话的便携式无线电话可经由无线网络传达语音及数据包。另外，许多此种无线电话包括并入于其中的其它类型的装置。举例来说，无线电话还可包括数字静态相机、数字视频相机、数字记录机及音频文件播放器。同样，无线电话可处理可用以接入因特网的可执行指令，所述指令包括例如网页浏览器应用程序的软件应用程序。因此，这些无线电话可包括重要计算能力。
通常，此种装置的计算能力可由多个半导体装置提供，其中每一半导体装置包括具有专门电路的裸片。例如具有调制解调器电路的裸片及具有通信电路的裸片的两个或两个以上裸片可在封装中堆叠于衬底上。堆叠裸片的一个典型方法在主裸片(host die)与堆叠裸片之间使用导电间隔物层。导电间隔物层电连接到堆叠裸片的底部，但由于在主裸片的表面上的保护钝化层而不电连接到主裸片的顶部。使用线接合在封装衬底上将堆叠裸片、导电间隔物层及主裸片连接到导电垫。然而，此堆叠方法由于增加的装配过程步骤及封装成本而可为困难且昂贵的。另外，例如在硅间隔物上的导电铝表面层的典型间隔物材料并不良好地固定到例如裸片附着材料及模制化合物的封装材料。
发明内容
在特定实施例中，揭示一种半导体装置。半导体装置包括具有表面的第一裸片，所述表面包括钝化区域、至少一个导电接合垫区域及大导电区域。举例来说，大导电区域可为至少10,000平方微米。
在另一实施例中，揭示一种裸片堆叠系统，其包括具有表面的第一裸片，所述表面包括钝化区域、至少一个导电接合垫区域及导电堆叠裸片容纳区域。导电堆叠裸片容纳区域经定尺寸以容纳至少第二裸片。
在另一实施例中，一种装置包括第一裸片。第一裸片具有表面，所述表面包括钝化区域、至少一个导电接合垫区域及导电裸片容纳区域，所述导电裸片容纳区域经定尺寸以容纳待耦合到第二裸片的至少一个导电耦合元件。
在另一实施例中，揭示一种包括多个半导体装置的封装。封装包括具有表面的第一裸片，所述表面包括钝化区域、至少一个导电接合垫区域、至少10,000平方微米的第一大导电区域及至少10,000平方微米的第二大导电区域。封装还包括与第一大导电区域的至少一部分接触的第二裸片。封装进一步包括与第二大导电区域的至少一部分接触的第三裸片。
在另一实施例中，揭示一种系统，其包括倒装芯片安装的装置，所述倒装芯片安装的装置包括耦合到第二裸片的第一裸片。系统还包括耦合到第二裸片的第三裸片。第三裸片具有表面，所述表面包括钝化区域、至少一个导电接合垫区域及经定尺寸以容纳至少第四裸片的导电堆叠裸片容纳区域。
由所揭示的实施例提供的一个特定优点为通过在裸片堆叠中消除间隔物层而减小了封装尺寸且降低了制造成本。通过归因于堆叠裸片之间的热导性的改进热散逸而提供另一优点。通过无需线接合的在堆叠裸片之间的电连接提供另一优点。
在审阅整个申请案之后，本发明的其它方面、优点及特征将变得显而易见，整个申请案包括以下部分：附图说明、实施方式及权利要求书。
附图说明
图1为裸片堆叠系统的第一说明性实施例的俯视图；
图2为图1的裸片堆叠系统沿线2-2的横截面图；
图3为裸片堆叠系统的第二说明性实施例的俯视图；
图4为图3的裸片堆叠系统沿线4-4的横截面图；
图5为裸片堆叠系统的第三说明性实施例的俯视图；
图6为图5的裸片堆叠系统沿线5-5的横截面图；及
图7为包括堆叠裸片的通信装置的框图。
具体实施方式
参考图1，其描绘裸片堆叠系统的第一说明性实施例的俯视图且大体上表示为100。系统100包括经由线接合(例如代表性线接合120)耦合到第一裸片102的半导体装置封装衬底101。第一裸片102具有表面，所述表面包括钝化区域104、例如代表性接合垫区域106的导电接合垫区域、第一导电堆叠裸片容纳区域108及第二导电堆叠裸片容纳区域110。
第一导电堆叠裸片容纳区域108经定尺寸以容纳至少第二裸片112。第二导电堆叠裸片容纳区域110经定尺寸以容纳至少第三裸片114。在特定实施例中，导电堆叠裸片容纳区域108及110中的每一者大于例如接合垫区域106的常规接合垫区域，且具有至少10,000平方微米的导电区域。作为说明性实例，导电堆叠裸片容纳区域108及110的一者或一者以上可具有边长大约为100微米的实质上正方形形状。如在本文中所使用，1微米(micron)＝1微米(micrometer)＝1um＝0.000001米。
在特定实施例中，钝化区域104发挥作用以保护第一裸片102的顶面且致使表面为电惰性的。举例来说，钝化区域104可包括氧化物或SiN层。例如接合垫区域106的导电接合垫区域及导电堆叠裸片容纳区域108及110可包括经由钝化区域104中的开口耦合到第一裸片102的表面且可近接的导电材料。
在特定实施例中，第一裸片102充当第二裸片112、第三裸片114或两者的主裸片。第二裸片112安置于第一导电堆叠裸片容纳区域108内且与第一导电堆叠裸片容纳区域108的至少一部分接触，从而建立到第一裸片102的电连接。第二裸片112还可分别经由例如代表性线接合122及124的线接合而耦合到半导体封装衬底101及第一裸片102。举例来说，第二裸片112可经由底部导体耦合到系统接地，所述导体电耦合到第一导电堆叠裸片容纳区域108。第二裸片112还可经由例如代表性线接合122及124的线接合接收系统功率及控制信号。
第三裸片114安置于第二导电堆叠裸片容纳区域110内且与第二导电堆叠裸片容纳区域110的至少一部分接触，从而建立到第一裸片102的电连接。第三裸片114还可分别经由例如代表性线接合132及134的线接合而耦合到半导体封装衬底101及第一裸片102。举例来说，第三裸片114可经由底部导体耦合到系统接地，所述导体电耦合到第二导电堆叠裸片容纳区域110且还可经由例如代表性线接合132及134的线接合接收系统功率及控制信号。
在特定实施例中，每一裸片102、112及114适合于执行分离功能，所述功能可相互操作以提供专用封装。举例来说，在数据处理半导体封装中，第一裸片102可包括功率管理电路且第二裸片114可包括数据处理电路。对于移动环境中的数据处理来说，第三裸片114可包括通信电路或调制解调器电路。作为另一实例，第一裸片102可包括功率管理电路且第二裸片114可包括操作装置显示器的显示器电路。
作为特定实例，第一裸片102可包括功率管理集成电路(PMIC)。第二及第三裸片112及114可包括控制器或其它处理器，模拟数字转换器(A/D)、显示器控制器或其任何组合。作为另一实例，系统100可针对移动环境而设计，且可包括PMIC、射频(RF)电路及通信处理器。
通过将堆叠裸片112及114经由钝化区域104中的开口耦合到第一裸片102的导电裸片容纳区域108及110，与在裸片之间使用间隔物层的堆叠技术相比，封装高度减小。减小的封装高度在具有多个堆叠裸片的实施例(例如包括耦合到第二裸片112的第四裸片(未图示)的替代实施例)中可更加显著。包括多个堆叠裸片的实施例说明于图5-6中。
在图2中描绘裸片堆叠系统100沿线2-2的横截面图200。在特定实施例中，第二裸片112可经由导电裸片附着材料240在第一导电堆叠裸片容纳区域108处固定到第一裸片102。第三裸片114还可经由导电裸片附着材料242固定到第二导电堆叠裸片容纳区域110。裸片附着材料240、242还可为导热的以散逸在堆叠裸片112及114处产生的热。
参考图3，其描绘裸片堆叠系统的第二说明性实施例的俯视图且大体上表示为300。系统300包括耦合到第一裸片302的封装衬底301。第二裸片304经由多个导电耦合元件306耦合到第一裸片302。在图4中描绘裸片堆叠系统300沿线4-4的横截面图400。
第一裸片302的顶面包括钝化区域308、至少一个导电接合垫区域310及经定尺寸以容纳第二裸片304的导电耦合元件306中的一者或一者以上的导电裸片容纳区域410。在特定实施例中，钝化区域308覆盖第一裸片302的顶面且形成开口以暴露接合垫区域，例如导电接合垫区域310，且暴露导电裸片容纳区域410。在特定实施例中，导电裸片容纳区域410具有至少10,000平方微米的区域，同时每一接合垫区域(例如导电接合垫区域310)小于10,000平方微米，例如为500平方微米到4,000平方微米。在另一实施例中，第一裸片302包括多个导电裸片容纳区域，每一者具有至少10,000平方微米的区域。
导电耦合元件306附着到第二裸片304且在导电堆叠裸片容纳区域410处电耦合到第一裸片302。导电耦合元件306可包括导电引线、垫、焊料球、引脚、螺柱、用以建立导电连接的其它结构或其任何组合。在特定实施例中，导电耦合元件306为倒装芯片凸块。
在特定实施例中，第一裸片302在导电裸片容纳区域410中具有多个电接触元件412。电接触元件412经定位以在第二裸片302在倒装芯片堆叠裸片布置中耦合到第一裸片302时接触第二裸片302的导电耦合元件306。电接触元件412可彼此电隔离以启用第一裸片302与第二裸片304之间的独立并联电路径。举例来说，当电接触元件412中的每一者与导电耦合元件306的对应一者接触时，一个或一个以上电源及多个电信号可在第一裸片302与第二裸片304之间并行地通信。
在特定实施例中，例如当使用不同工艺技术制造第一裸片302及第二裸片304时，第一裸片302及第二裸片304可具有不同成品率。举例来说，第一裸片302为互补硅上金属(metal-on-silicon)(CMOS)装置、绝缘体上硅(SOI)装置、体半导体装置、硅锗(SiGe)装置或砷化镓(GaAs)装置，且第二裸片304可为与第一裸片302不同类型的装置。作为特定实例，第一裸片302可为CMOS类型的装置且第二裸片304可为非CMOS类型的装置，例如SOI装置、SiGe装置、GaAs装置或例如微机电系统(MEMS)装置的体装置。在特定实施例中，用于封装的裸片302及304的堆叠次序可基于裸片302及304的成品率而确定。举例来说，较高成品率的裸片可堆叠于较低成品率的裸片下方以改进整体封装成品率、成本、制造时间或其任何组合。
参考图5，其描绘裸片堆叠系统的第三说明性实施例的俯视图且大体上表示为500。倒装芯片安装的装置503包括耦合到第二裸片504的第一裸片508。系统500还包括耦合到第二裸片504且安装到衬底501的第三裸片502。第四裸片510耦合到第三裸片502。图6中描绘系统500沿线6-6的横截面图600。
第三裸片502充当用于倒装芯片安装的装置503及第四裸片510的主裸片。第三裸片502的顶面具有钝化区域514以减少裸片表面处的不合需要的相互作用。钝化区域514包括开口以提供对至少一个导电接合垫区域516及导电堆叠裸片容纳区域512的近接。导电堆叠裸片容纳区域512经定尺寸以容纳至少第四裸片510。在特定实施例中，导电堆叠裸片容纳区域512经定尺寸以容纳多个裸片。举例来说，导电堆叠裸片容纳区域512可包括耦合到电源或系统接地的大的导电及导热表面且可足够大以供多个裸片坐落。
第二裸片504经由例如倒装芯片凸块的多个导电耦合元件506在第二导电堆叠裸片容纳区域624处耦合到第三裸片502，第二裸片504可经由钝化区域514中的开口近接第二导电堆叠裸片容纳区域624。第二导电堆叠裸片容纳区域624包括经布置以耦合到导电耦合元件506的多个触点626。在特定实施例中，第二裸片504的底面在不使用间隔物层的情况下直接接触第二导电堆叠裸片容纳区域624的至少一部分。第二裸片504不经由线接合耦合到第三裸片502。在替代实施例中，第二裸片504除可经由多个导电耦合元件506耦合到主裸片之外，还可经由一个或一个以上线接合耦合到主裸片。
第一裸片508经由裸片附着材料622耦合到第二裸片504。在特定实施例中，裸片附着材料622为导热粘着材料。例如代表性线接合520及522的线接合分别将第一裸片508耦合到第三裸片502的接合垫及耦合到衬底501的接合垫。另外，第一裸片508可经由裸片附着材料622电耦合到第二裸片504。举例来说，裸片附着材料622可在第二裸片504的顶面上的导电区域与第一裸片508的底面上的导电区域之间提供电接触。裸片附着材料的实例包括聚合物粘着剂及裸片附着合金。
第四裸片510经由导电裸片附着材料620以电方式且以机械方式耦合到导电堆叠裸片容纳区域512。第四裸片510还经由线接合(例如，代表性线接合530)耦合到第三裸片502的线接合垫(例如导电垫区域516)。另外，第四裸片510还经由线接合(例如，代表性线接合532)耦合到衬底501的线接合垫。
参考图7，其描绘包括堆叠裸片的通信装置的框图且大体表示为700。通信装置700包括芯片组720，所述芯片组720包括例如包括功率管理集成电路(PMIC)722的裸片的第一裸片。芯片组720还包括堆叠于第一裸片上的，例如包括数字信号处理器(DSP)710的裸片。在特定实施例中，DSP 710如关于图1到6所描述耦合到PMIC 722的导电裸片容纳区域。
显示器控制器726可耦合到数字信号处理器710及耦合到显示器728。另外，存储器732耦合到数字信号处理器710。编码器/解码器(编解码器)734还可耦合到数字信号处理器710。扬声器736及麦克风738可耦合到编解码器734。另外，无线控制器740可耦合到数字信号处理器710及耦合到无线天线742。调制解调器760还可耦合到DSP710。
在特定实施例中，如关于图1-6所描述，DSP 710、显示器控制器726、存储器732、编解码器734、无线控制器740、调制解调器760或其任何组合可包括耦合到PMIC 722的堆叠裸片或倒装芯片。另外，通信装置700可包括多个裸片的一个或一个以上堆叠。举例来说，DSP 710可堆叠于PMIC 722上，且调制解调器760可堆叠于DSP 710上。
在特定实施例中，电源744及输入装置730耦合到PMIC 722。此外，在特定实施例中，如图7中所说明，显示器728、输入装置730、扬声器736、麦克风738、无线天线742及电源744各自耦合到芯片组720的组件。
所属领域的技术人员将进一步了解，结合本文所揭示的实施例描述的各种说明性逻辑块、配置、模块、电路及算法步骤可实施为电子硬件、计算机软件或两者的组合。为清楚地说明硬件与软件的此互换性，各种说明性组件、块、配置、模块、电路及步骤已在上文大体上在其功能性方面而描述。将此功能性实施为硬件还是软件视特定应用及强加于整个系统的设计约束而定。所属领域的技术人员可针对每一特定应用以不同方式实施所描述的功能性，但此类实施决策不应被解释为导致偏离本发明的范围。
结合本文中所揭示的实施例而描述的方法或算法的步骤可直接以硬件、由处理器所执行的软件模块或所述两者的组合体现。软件模块可驻留在RAM存储器、快闪存储器、ROM存储器、PROM存储器、EPROM存储器、EEPROM存储器、寄存器、硬磁盘、可装卸磁盘、CD-ROM或此项技术中已知的任何其它形式的存储媒体中。示范性存储媒体耦合到处理器，以使得处理器可从存储媒体读取信息且向存储媒体写入信息。在替代例中，存储媒体可与处理器成一体。处理器及存储媒体可驻留于ASIC中。ASIC可驻留于计算装置或用户终端中。在替代例中，处理器及存储媒体可作为离散组件驻留于计算装置或用户终端中。
提供所揭示实施例的先前描述以使任何所属领域的技术人员能够制作或使用所揭示实施例。所属领域的技术人员将易于明了对这些实施例的各种修改，且本文所界定的一般原理可在不偏离本发明的精神或范围的情况下应用于其它实施例。因此，不希望将本发明限制于本文中展示的实施例，而是赋予其与所附权利要求书所界定的原理及新颖特征相一致的可能的最广泛范围。

Claims (25)

1.一种半导体装置，其包含：
第一裸片，其具有表面，所述表面包括钝化区域、至少一个导电接合垫区域及经定尺寸以容纳至少第二裸片的大导电区域。
2.根据权利要求1所述的装置，其中所述大导电区域为至少10,000平方微米。
3.根据权利要求1所述的装置，其进一步包含至少10,000平方微米的第二大导电区域。
4.根据权利要求3所述的装置，其进一步包含：
第二裸片，其与所述大导电区域的至少一部分接触；以及
第三裸片，其与所述第二大导电区域的至少一部分接触。
5.一种系统，其包含：
第一裸片，其具有表面，所述表面包括钝化区域、至少一个导电接合垫区域及经定尺寸以容纳至少第二裸片的导电堆叠裸片容纳区域。
6.根据权利要求5所述的系统，其进一步包含安置于所述导电堆叠裸片容纳区域内的第二裸片。
7.根据权利要求6所述的系统，其中所述第二裸片电连接到所述第一裸片。
8.根据权利要求5所述的系统，其中所述第二裸片包括多个导电元件，所述多个导电元件经由所述导电堆叠裸片容纳区域电耦合到所述第一裸片。
9.根据权利要求8所述的系统，其中所述多个导电元件包括垫、焊料球、引脚或其任何组合。
10.一种装置，其包含：
第一裸片，其具有表面，所述表面包括钝化区域、至少一个导电接合垫区域及导电裸片容纳区域，所述导电裸片容纳区域经定尺寸以容纳待耦合到第二裸片的至少一个导电耦合元件。
11.根据权利要求10所述的装置，其中所述至少一个导电耦合元件包括导电引线、导电垫或导电焊料球。
12.根据权利要求10所述的装置，其中所述导电裸片容纳区域适合于容纳待耦合到所述第二裸片的多个导电耦合元件，所述多个导电耦合元件包含倒装芯片凸块。
13.根据权利要求10所述的装置，其进一步包含多个导电裸片容纳区域，每一导电裸片容纳区域具有至少10,000平方微米的区域。
14.根据权利要求10所述的装置，其中所述至少一个导电接合垫区域小于10,000平方微米。
15.根据权利要求10所述的装置，其中所述第二裸片经由所述至少一个导电耦合元件耦合到所述第一裸片且进一步包含耦合到所述第二裸片的第三裸片。
16.根据权利要求10所述的装置，其中所述第一裸片为CMOS装置、绝缘体上硅(SOI)装置、体半导体装置、硅锗装置及砷化镓装置中的一者，且其中所述第二裸片为与所述第一裸片不同类型的装置。
17.根据权利要求16所述的装置，其中所述第一裸片为CMOS且所述第二裸片为非CMOS类型的装置。
18.根据权利要求10所述的装置，其中所述第一裸片具有第一成品率且所述第二裸片具有第二成品率。
19.一种包括多个半导体装置的封装，所述封装包含：
第一裸片，其具有表面，所述表面包括钝化区域、至少一个导电接合垫区域、至少10,000平方微米的第一大导电区域及至少10,000平方微米的第二大导电区域；
第二裸片，其与所述第一大导电区域的至少一部分接触；以及
第三裸片，其与所述第二大导电区域的至少一部分接触。
20.根据权利要求19所述的封装，其中所述第一裸片包括功率管理电路且所述第二裸片包括数据处理电路。
21.根据权利要求19所述的封装，其中所述第三裸片包括通信电路。
22.根据权利要求19所述的封装，其进一步包含耦合到所述第二裸片的第四裸片。
23.根据权利要求19所述的封装，其中所述第一裸片包括功率管理电路且所述第二裸片包括显示器电路。
24.一种系统，其包含：
倒装芯片安装的装置，其包括第一裸片，所述第一裸片耦合到第二裸片；
第三裸片，其耦合到所述第二裸片且具有表面，所述表面包括钝化区域、至少一个导电接合垫区域及经定尺寸以容纳至少第四裸片的导电堆叠裸片容纳区域。
25.根据权利要求24所述的装置，其中所述第二裸片具有表面，所述表面在不使用间隔物层的情况下直接接触所述导电堆叠裸片容纳区域的至少一部分。
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