CN103620766A - 用于无芯基板的原位建立针栅阵列及其制造方法 - Google Patents
用于无芯基板的原位建立针栅阵列及其制造方法 Download PDFInfo
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Abstract
一种无芯针栅阵列(PGA)基板包括在不需要使用焊料的情况下集成到PGA基板的PGA引脚。制造无芯PGA基板的工艺通过在PGA引脚上形成构建层来集成PGA引脚,以使通孔直接接触于PGA引脚的引脚头。
Description
技术领域
公开的实施例涉及一种针栅阵列基板。
附图说明
为了理解获得实施例的方式,将参考附图来呈现以上简单描述的各个实施例的更具体的描述。这些附图描述不一定按比例绘制并且不被认为是对范围的限制的实施例。一些实施例将通过使用所附附图用附加特征和细节来描述和解释,其中:
图1为根据示例实施例的具有集成引脚的无芯针栅阵列基板的截面正面图;
图1a为根据示例实施例的在处理期间的图1中所描绘的无芯针栅阵列基板的截面正面图;
图1b为根据示例实施例的在处理期间的图1a中所描绘的无芯针栅阵列基板的截面正面图;
图1c为根据示例实施例的在处理期间的图1b中所描绘的无芯针栅阵列基板的截面正面图;
图1d为根据示例实施例的在处理期间的图1c中所描绘的无芯针栅阵列基板的截面正面图;
图2为根据示例实施例的包括具有集成引脚的无芯针栅阵列基板的多芯片封装的截面正面图;
图3为根据示例实施例的包括具有集成引脚的无芯针栅阵列基板的堆叠芯片封装的截面正面图;
图4为根据示例实施例的包括具有集成引脚的无芯针栅阵列基板的层叠封装的截面正面图;
图5为根据示例实施例的工艺和方法流程图;以及
图6为根据实施例的计算机系统的示意图。
具体实施方式
公开了无芯针栅阵列基板被组装并且与微电子装置耦合作为芯片封装的过程。现将参照附图,在附图中相似的结构可设置有相似的后缀标记标识。为了更清楚地显示各个实施例的结构,包括在本文中的附图为集成电路结构的图解表示。因此,虽然仍包括所示实施例的所要求保护的结构,但单独的或在芯片封装中的所制造的芯片基板的实际外观(例如在显微照片中)可能会出现不同。此外,附图仅显示有利于理解所示实施例的结构。可能不包括本领域已知的附加的结构以保持附图的清晰。
图1为根据示例实施例的作为芯片封装100的具有集成引脚的无芯针栅阵列基板(PGA)的截面正面图。可理解“集成引脚”意指PGA引脚与无芯PGA基板110原位形成。
描绘了具有多个引脚112的无芯PGA基板110。引脚112包括引脚头114。作为整体,引脚112和引脚头114为PGA基板110的一部分,使得PGA基板110已被制造成包括引脚112的整体结构。换句话说,没有焊料被用于将引脚112耦合至无芯PGA基板110。在无芯PGA基板110的制造期间,引脚112被制造成无芯PGA基板110的组成部分。虽然引脚头114与引脚112成整体,但引脚头114也是PGA的焊盘114。
如所描绘的,包括引脚头114的引脚112通过信号通孔116和电源-接地通孔118附接至无芯PGA基板110。信号通孔116与引脚头114直接接触。类似地,电源-接地通孔118也与引脚头114直接接触。本公开中的“直接接触”意味着引脚116不具有中间电性结构(诸如通孔116和118与引脚头114之间的焊料)。
在实施例中,电源-接地通孔118被配置为多个电源-接地通孔118用于给定引脚头114,诸如两个电源-接地通孔118用于给定引脚头。这与配置为单个通孔用于给定引脚头的信号通孔116形成对比。换句话说,用于给定引脚头的信号通孔的数量小于用于给定引脚头的电源-接地通孔的数量。如实施例中所示,信号通孔116为用于给定引脚的单个通孔,而电源-接地通孔118比信号通孔的数量多。例如在实施例中,信号通孔116为用于给定引脚的单个通孔,而用于给定引脚的电源-接地通孔118在数量上比信号通孔的数量多一个。换句话说,在实施例中,每个引脚头的电源-接地通孔的数量为每个引脚头的信号通孔的数量的两倍。
第一中间层120分别包围信号-和电源/接地通孔116和118,以及将引脚头114集成在无芯PGA基板110的引脚侧处的第一中间层120中。引脚侧还被称为作为PGA与基础基板(例如,母板)连接的焊盘侧。在引脚112和引脚头114处进一步给无芯PGA基板110制造多个迹线,其中的一条迹线通过附图标记122表示。由于迹线122与第一中间层120接触,因此迹线122可被称为第一级迹线122。邻接第一中间层120制造第二中间层124。继续PGA基板110的进一步构建,直到后续的中间层126和阻焊掩模128形成PGA基板110的管芯侧的一部分。后续的迹线130与后续的中间层126接触。在实施例中,从第一中间层120到后续的中间层126的层的数量在从2到15的范围内。在实施例中,从第一中间层120到后续的中间层126的层的数量在从3到9的范围内。公开了用于无芯PGA基板实施例的若干质量和数量。在实施例中,PGA108的每个引脚112具有引脚长度132以及引脚头宽度134。任何两个相邻的引脚112在中心136上间隔开。
PGA基板110和PGA108配置成支持诸如由美国加利福尼亚州圣克拉拉市的英特尔公司制造的处理器之类的微电子装置128的芯片封装100。微电子装置138可配置成倒装芯片138并且通过多个电隆起焊盘耦合至无芯PGA基板110,其中的一个电隆起焊盘通过附图标记140表示。
在实施例中,PGA基板110具有从0.200微米(μm)到0.8μm范围内的厚度。在实施例中,PGA基板110具有0.7μm的厚度。可使用其他厚度。
“引脚拉伸强度”被定义为施加在一个引脚112上直到它失效的拉力,失效意味着直到从无芯基板110撕掉。在实施例中,引脚拉伸强度在从3kg到10kg的范围内。在实施例中,引脚拉伸强度为5kg。在对于具有60μm的通孔直径的2-通孔的示例中,引脚拉伸强度大于5kg,诸如10kg。
根据所公开的实施例,与传统技术相比,引脚间距136减小。在实施例中,引脚间距136在从350μm(中心到中心)到800μm的范围内。在实施例中,引脚间距136在从400μm到550μm的范围内。在实施例中,引脚间距136在从450μm到500μm的范围内。
根据所公开的实施例,与传统技术相比,引脚长度132减小。在实施例中,引脚长度132在从0.6mm到1.4mm的范围内。在实施例中,引脚长度132在从0.8mm到1.2mm的范围内。在实施例中,引脚长度为1mm。在实施例中,长度132除以宽度133的引脚长宽比在从5:1至20:1的范围内。
在实施例中,无芯PGA基板110作为芯片封装100被组装到诸如膝上型或上网本计算机之类的移动系统。描述了其中可插入引脚112的基础基板190。在实施例中,基础基板190为作为刀片服务器的一部分的板。在实施例中,基础基板190为作为微服务器的一部分的板。在实施例中,基础基板190为诸如用于移动计算机(例如,平板)的母板之类的板。
图1a为根据示例实施例的在处理期间的图1中所描绘的无芯针栅阵列基板110的截面正面图。前驱结构101配置有PGA引脚模具142。PGA引脚模具142可与相似的PGA引脚模具142'相对地放置以用于制造用途。PGA引脚模具142和相似的PGA引脚模具142'可通过释放层144附连,该释放层144在后续的处理中用于隔开不连续的PGA无芯基板。进一步的处理将涉及通过使用PGA引脚模具142制造的无芯PGA基板,但是可推断出用于相似的PGA引脚模具142’的处理。
在实施例中,通过化学镀方法处理PGA引脚模具142以将籽晶层146粘附到其上。PGA引脚模具142包括多个引脚凹槽,其中的一个引脚凹槽通过附图标记148表示。籽晶层146覆盖PGA引脚模具142并进入凹槽148内。若干凹槽148的间隔被配置成容纳有用设计,诸如针对图1和本公开中其他地方描绘的结构描述的任何实施例。在示例实施例中,通过所选的PGA引脚模具142建立500μm的引脚间距134。
图1b为根据示例实施例的在处理期间的图1a中所描绘的无芯针栅阵列基板的截面正面图。前驱结构102包括PGA引脚模具142,该引脚模具142已通过使用籽晶层146作为阴极对针栅阵列前驱膜150进行电镀而被处理。在实施例中,籽晶层146为电工级铜,以及PGA前驱膜150也为电工级铜。图1c为根据示例实施例的在处理期间的图1b中所描绘的无芯针栅阵列基板的截面正面图。前驱结构103包括PGA基板142,该PGA基板142已以通过将图案蚀刻到PGA前驱膜150中被处理以形成各个间隔开的引脚112。处理还形成作为引脚112的一部分的引脚头114。
图1d为根据示例实施例的在处理期间的图1c中所描绘的无芯针栅阵列基板的截面正面图。如图1d中的中间处理期间所示,已通过一系列的建立层形成包括PGA基板110的两个相对的PGA基板104。如所描绘的,已采用其中已分别形成信号-和电源/接地通孔116和118的第一中间层120来覆盖引脚112。第一中间层120还将引脚头114集成到其中。在引脚112和引脚头114处进一步给PGA基板110制造多个第一级迹线,其中的一条第一级迹线通过附图标记122表示。邻接第一中间层120制造第二中间层124。继续PGA基板100的进一步构建,直到后续的中间层126(图1)和阻焊掩模128。
在实施例中,PGA108的每个引脚112具有引脚长度132以及引脚头宽度133。任何两个相邻的引脚在中心136上间隔开。PGA基板100和PGA108被配置为支持微电子装置138的芯片封装。微电子装置138可配置成倒装芯片138并且通过多个电隆起焊盘耦合至无芯PGA基板110,其中的一个电隆起焊盘通过附图标记140表示。
图2为根据示例实施例的包括具有集成引脚的无芯针栅阵列基板210的多芯片封装200的截面正面图。描绘了具有多个引脚212的无芯PGA基板210。引脚212包括引脚头214。作为整体,引脚212和引脚头214为PGA基板210的一部分,使得PGA基板210已被制造成包括引脚212的整体结构。换句话说,没有焊料被用于将引脚212耦合至无芯PGA基板210。在无芯PGA基板210的制造期间,引脚212被制造成无芯PGA基板210的组成部分。如所描绘的,类似于针对图1A所示的芯片封装110的公开内容,包括引脚头214的引脚212通过信号通孔216和电源-接地通孔218被附连至无芯PGA基板210,第一中间层220分别包围信号-和电源/接地通孔216和218,以及将引脚头214集成到在无芯PGA基板210的引脚侧的第一中间层220中。在引脚212和引脚头214处进一步给无芯PGA基板210制造多个迹线,其中的一条迹线通过附图标记222表示。由于迹线222与第一中间层220接触,因此迹线222可被称为第一级迹线222。邻接第一中间层220制造第二中间层224。继续PGA基板210的进一步建立直到后续的中间层226和阻焊掩模228形成PGA基板210的管芯侧的一部分。后续的迹线230与后续的中间层226接触。
PGA基板210和PGA208配置成支持诸如由美国加利福尼亚州圣克拉拉市的英特尔公司制造的处理器之类的微电子装置238以及后续的微电子装置248的多芯片封装200。在实施例中,微电子装置238为倒装芯片238并且通过多个电隆起焊盘耦合至无芯PGA基板210,其中的一个电隆起焊盘通过附图标记240表示,而且后续的微电子装置248为丝焊250芯片,丝焊250芯片安装有背对无芯PGA基板210的管芯侧的有源表面。在实施例中,装置238为处理器,以及装置248为射频装置。在实施例中,这两个芯片像微电子装置238那样倒装安装。
现可理解,针对图1中所描绘的无芯基板110描绘和描述的无芯基板质量可应用于多芯片封装无芯PGA基板210。现可理解,无芯PGA基板210可与诸如图1中所示出和描述的基础基板190实施例中的基础基板连接。
图2为根据示例实施例的包括具有集成引脚的无芯针栅阵列基板310的堆叠芯片封装300的截面正面图。描绘了具有多个引脚312的无芯PGA基板310。引脚312包括引脚头314。作为整体,引脚312和引脚头314为PGA基板310的一部分,使得PGA基板310已被制造成包括引脚312的整体结构。换句话说,没有焊料被用于将引脚312耦合至无芯PGA基板310。在无芯PGA基板310的制造期间,引脚312被制造成无芯PGA基板310的组成部分。如所描绘的,类似于针对图1中所描绘的芯片封装310和图2中所描绘的包括无芯PGA基板210的多芯片封装200的公开内容,包括引脚头314的引脚312通过信号通孔316以及电源-接地通孔318附连至无芯PGA基板310。第一中间层320分别包围信号-和电源/接地通孔316和318,以及将引脚头314集成在无芯PGA基板310的引脚侧的第一中间层320中。在引脚310和引脚头312处进一步给无芯PGA基板310制造多个迹线,其中的一条迹线通过附图标记322表示。由于迹线322与第一中间层320接触,因此迹线322可被称为第一级迹线322。邻接第一中间层320制造第二中间层324。继续PGA基板310的进一步构建直到后续的中间层326和阻焊掩模328形成PGA基板310的管芯侧的一部分。后续的迹线330与后续的中间层326接触。
PGA基板310和PGA308配置成支持诸如由美国加利福尼亚州圣克拉拉市的英特尔公司制造的处理器之类的微电子装置338以及堆叠的后续微电子装置348的堆叠芯片封装300。在实施例中,微电子装置338为硅通孔352倒装芯片338并且通过多个电隆起焊盘耦合至无芯PGA基板310,其中的一个电隆起焊盘通过附图标记340表示,而且后续的微电子装置354为倒装芯片354,倒装芯片354安装有正对朝向无芯PGA基板310的管芯侧并且耦合至TSV352的有源表面。在实施例中,装置338为处理器,以及装置348为诸如固态驱动器的存储器装置。现可理解,针对图1和2中所描绘的无芯基板110和210描绘和描述的无芯基板质量可应用于堆叠芯片封装无芯PGA基板310,反之亦然。现可理解,无芯PGA基板310可与诸如图1中所示出和描述的基础基板190实施例之类的基础基板连接。
图4为根据示例实施例的包括具有集成引脚412的无芯针栅阵列基板410的层叠封装400的截面正面图。描绘了具有多个引脚412的无芯PGA基板410。引脚412包括引脚头414。作为整体,引脚412和引脚头414为PGA基板410的一部分,使得PGA基板410已被制造成包括引脚412的整体结构。换句话说,没有焊料被用于将引脚412耦合至无芯PGA基板410。在无芯PGA基板410的制造期间,引脚412被制造成无芯PGA基板410的组成部分。如所描绘的,类似于针对图1中所描绘的芯片封装110、图2中所描绘的包括无芯PGA基板20的多芯片封装200、以及图3中所描绘的堆叠芯片PGA基板封装300的公开内容,包括引脚头414的引脚412通过信号通孔416以及电源-接地通孔418附连至无芯PGA基板410。第一中间层420分别包围信号-和电源/接地通孔416和418,以及将引脚头414集成在无芯PGA基板410的引脚侧的第一中间层120中。在引脚410和引脚头412处进一步给无芯PGA基板410制造多个迹线,其中的一条迹线通过附图标记422表示。由于迹线422与第一中间层420接触,因此迹线422可被称为第一级迹线422。邻接第一中间层420制造第二中间层424。继续PGA基板410的进一步构建直到后续的中间层426和阻焊掩模428形成PGA基板410的管芯侧的一部分。后续的迹线430与后续的中间层426接触。
PGA基板410和PGA408配置成支持诸如由美国加利福尼亚州圣克拉拉市的英特尔公司制造的处理器之类的微电子装置438以及POP后续的微电子装置448的层叠芯片封装(POP)400。在实施例中,微电子装置438通过多个电隆起焊盘耦合至无芯PGA基板410,其中的一个电隆起焊盘通过附图标记440表示,以及POP后续的微电子装置454为倒装芯片454,倒装芯片454安装有面朝POP基板460的有源表面,POP基板460利用POP电隆起焊盘462安装在无芯PGA基板410的管芯侧上。在实施例中,装置438为处理器,以及装置448为诸如固态驱动器的存储器装置。现可理解,针对图1、2和3中所描绘的无芯基板110、201和310描绘和描述的无芯基板质量可应用于POP无芯PGA基板410,反之亦然。现可理解,无芯PGA基板410可与诸如图1中所示出和描述的基础基板190实施例的基础基板连接。
图5为根据示例实施例的工艺和方法流程图500。
在510,工艺包括在PGA引脚模具上形成籽晶层。在非限制的示例实施例中,通过化学镀在引脚模具42上形成铜籽晶层146。
在520,工艺包括在籽晶层上形成PGA前驱膜。在非限制的示例实施例中,籽晶层146为电工级铜并且用作阴极以形成也由电工级铜组成的针栅前驱150。
在530,工艺包括图案化针栅前驱以形成单独的间隔开的引脚。在非限制的示例实施例中,通过根据图案蚀刻针栅前驱来形成引脚112。
在540,工艺包括形成无芯针栅阵列基板,该无芯针栅阵列基板包含作为其中的整体部分的间隔开的引脚。换句话说,没有焊料被用于将引脚接合至无芯PGA基板中的通孔。在非限制的示例实施例中,第一中间层120分别包围信号-和电源/接地通孔116和118,以及将引脚头114集成在无芯PGA基板110的引脚侧的第一中间层120中。根据示例实施例的进一步处理包括形成迹线和电介质的若干中间层直到在无芯针栅阵列基板110的管芯侧处形成后续的中间层126和阻焊掩模128。在实施例中,工艺在510开始并且在540结束。
在方法实施例中的550,将微电子装置组装至无芯针栅阵列基板。在非限制的示例实施例中,将处理器138倒装组装至无芯针栅阵列基板110。在非限制的示例实施例中,将处理器238倒装组装至多芯片无芯针栅阵列基板210,并将装置248丝焊组装至多芯片无芯针栅阵列基板210。在非限制的示例实施例中,将硅通孔处理器338倒装组装至无芯针栅阵列基板310,以及通过耦合至硅通孔352将装置354倒装接合至处理器338。在非限制的示例实施例中,后续的装置448为组装至无芯针栅阵列基板410的POP。在实施例中,工艺在510开始并且在550结束。在实施例中,方法在540开始并且在550结束。
在方法实施例中的560中,将无芯PGA基板被组装至诸如关于图6所描绘的任何计算机系统实施例之类的计算机系统。
图6为根据实施例的计算机系统的示意图。所描绘的计算机系统600(也称为电子系统600)可具体化根据若干所公开的实施例中的任一个和在本公开中所陈述的它们的等价方案的无芯针栅阵列基板。包括无芯针栅阵列基板的装置被组装至计算机系统。计算机系统600可以为诸如上网本计算机的移动装置。计算机系统可以为台式计算机。计算机系统600可以集成至汽车。计算机系统600可以集成至电视机。计算机系统600可以集成至DVD播放器。计算机系统600可以集成至数码摄像机。
在实施例中,电子系统600为计算机系统,该计算机系统包括用以电耦合电子系统600的多个部件的系统总线620。系统总线620为单个总线或根据各个实施例的总线的任何组合。电子系统600包括将功率提供至集成电路610的电压源630。在一些实施例中,电压源630通过系统总线620将电流提供至集成电路610。
集成电路610电耦合至系统总线620并且包括任何电路,或根据实施例的电路的组合。在实施例中,集成电路610包括处理器612,处理器612可以为包括无芯针栅阵列基板实施例的任何类型的装置。如本文所使用的,处理器612可意指任何类型的电路,诸如,但不限于,微处理器、微控制器、图形处理器、数字信号处理器、或其他处理器。在实施例中,SRAM实施例在处理器的存储器高速缓存中找到。可包括在集成电路610中的其他类型的电路为定制电路或专用集成电路(ASIC),例如,在诸如蜂窝电话、智能电话、寻呼机、便携式计算机、双向无线电、以及类似的电子系统的无线装置中使用的通信电路614。在实施例中,处理器610包括诸如静态随机存取存储器(SRAM)之类的管芯上存储器616。在实施例中,处理器610包括诸如嵌入式动态随机存取存储器(eDRAM)的嵌入式管芯上存储器616。
在实施例中,集成电路610被诸如本公开中所陈述的图形处理器或射频集成电路或以上两者的后续的集成电路611补充。在实施例中,双集成电路610包括诸如eDRAM之类的嵌入式管芯上存储器617。双集成电路611包括RFIC双处理器613和双通信电路615和诸如SRAM的双管芯上存储器617。在实施例中,双通信电路615被特别配置成用于RF处理。在实施例中,至少一个无源器件680耦合至后续的集成电路611,使得集成电路611和至少一个无源器件作为包括包含集成电路610和集成电路611的无芯针栅阵列基板的任何装置实施例的一部分。
在实施例中,电子系统600包括天线元件682,诸如在本公开中所陈述的任何无芯针栅阵列基板实施例。通过使用天线元件682,诸如电视机的远程设备684可通过装置实施例通过无线链路远程地操作。例如,通过无线链路操作的智能手机上的应用诸如通过蓝牙○R技术将指令广播至高达约30m距离处的电视机。
在实施例中,电子系统600还包括又可包括适合于特定应用的一个或多个存储器元件的外部存储器640(诸如以RAM形式的主存储器642)、一个或多个硬盘驱动器644、和/或处理可移动介质646(诸如软盘、光盘(CD)、数字可变盘(DVD)、闪存驱动器、以及本领域已知的其他可移动介质)的一个或多个驱动器。在实施例中,外部存储器640被堆叠为TSV芯片,TSV芯片已根据任何所公开的实施例被组装至无芯针栅阵列基板。在实施例中,外部存储器640为嵌入式存储器648,这种装置包括根据任何所公开的实施例配合至无芯针栅阵列基板的TSV芯片。
在实施例中,电子系统600还包括显示装置650以及音频输出660。在实施例中,电子系统600包括输入装置,诸如控制器670,该控制器670可以为键盘、鼠标、触摸板、小键盘、轨迹球、游戏控制器、话筒、语音识别装置、或将信息输入至电子系统600的任何其他输入装置。在实施例中,输入装置670包括相机。在实施例中,输入装置670包括数字录音机。在实施例中,输入装置670包括相机和数字录音机。
基础基板690可以是计算系统600的一部分。在实施例中,基础基板690为母板,该母板支持包括无芯针栅阵列基板的装置。在实施例中,基础基板690为刀片服务器的一部分,该刀片服务器支持包括无芯针栅阵列基板的装置。在实施例中,基础基板690为微服务器的一部分,该微服务器支持包括无芯针栅阵列基板的装置。在实施例中,基础基板690为平板母板的一部分,该平板母板支持包括无芯针栅阵列基板的装置。可理解,诸如无芯针栅阵列基板的辅助低成本封装可以为计算机系统600以及其上组装辅助低成本封装的母板的一部分。在实施例中,基础基板690为板,该板支持包括无芯针栅阵列基板的装置。在实施例中,基础基板690包括包含在虚线690中的至少一个功能并且为诸如无线通信器的用户外壳的基板。
如本文所示的,可在多个不同实施例、包括根据若干所公开的实施例和它们的等价方案中的任一个的无芯针栅阵列基板的装置、电子系统、计算机系统、制造集成电路的一个或多个方法、以及制造和组装包括根据在各个实施例中所陈述的若干所公开的实施例和它们的本领域公认的等价方案中的任一个的无芯针栅阵列基板的装置的一个或多个方法中实现集成电路610。元件、材料、几何图形、大小、以及操作的顺序都可改变以适合包括无芯针栅阵列基板实施例和它们的等价方案的特定I/O耦合需要。
虽然管芯可指的是可能会在相同的句子中被提及的处理器芯片、RF芯片、RFIC芯片、IPD芯片或存储器芯片,但不应当被解释成它们为等价结构。在本说明书通篇中对“一个实施例”或“实施例”的引用意味着结合该实施例描述的特定特征、结构或特性包括在本发明的至少一个实施例中。在本说明书通篇中各处出现的短语“在一个实施例中”或“在实施例中”不一定全部指的是同一实施例。而且,特定特征、结构、或特性可按照任何合适的方式在一个或多个实施例中组合。
诸如“上部”和“下部”“上方”和“下方”之类的术语可通过参考所示的X-Z坐标来理解,以及诸如“相邻”之类的术语可通过参考X-Y坐标或非-Z坐标来理解。
提供本发明内容的摘要以符合37C.F.R.第1.72(b)章节,该章节要求摘要允许读者迅速查明技术公开内容的本质和要点。该摘要是以它不用于解释或限制权利要求的范围或含义的理解而提交的。
在上述具体实施方式中,为了将公开内容串成整体,各个特征在单个实施例中被组合到一起。这种公开方法不应被解释为反映声明要求保护的本发明相比各个权利要求中明确陈述的特征而言需要更多特征的意图。相反,如所附权利要求反映出来的那样,本发明的方面少于以上公开的单个实施例的所有特征。因此,以下权利要求在此被包括到本具体实施方式中,其中各个权利要求自身独立作为单独的优选实施例。
本领域技术人员将容易理解,可在为了解释本发明的本质已描述和示出的细节、材料、以及部件的排列和方法阶段中作出各种其他改变,而不背离所附权利要求中所表达的本发明的原理和范围。
Claims (29)
1.一种无芯针栅阵列基板,包括:
管芯侧和焊盘侧;
针栅阵列(PGA)信号引脚,所述针栅阵列(PGA)信号引脚与所述焊盘侧集成设置,其中所述PGA信号引脚与设置在第一中间层中的第一通孔直接接触并且还与接触所述第一中间层的第一迹线直接接触;
PGA电源-接地引脚,所述PGA电源-接地引脚与所述焊盘侧集成设置,其中所述PGA电源-接地引脚与设置在所述第一中间层中的第一通孔直接接触并且还与接触所述第一中间层的第一迹线直接接触;
后续的中间层,所述后续的中间层毗邻管芯侧设置,其中来自所述PGA信号引脚和PGA电源-接地引脚的电连接通过所述后续的中间层耦合;
后续的迹线,所述后续的迹线与后续的中间层接触;
多个中间的中间层,所述多个中间的中间层设置在所述第一中间层和后续的中间层之间;以及
多个信号中间通孔,所述多个信号中间通孔将PGA信号引脚电耦合至所述管芯侧;以及
多个电源-接地中间通孔,所述多个电源-接地中间通孔将PGA电源-接地引脚电耦合至所述管芯侧。
2.如权利要求1所述的无芯针栅阵列基板,其特征在于,在所述第一中间层和所述后续的中间层之间设置数量在1与50之间的中间层。
3.如权利要求1所述的无芯针栅阵列基板,其特征在于,所述PGA信号引脚具有从3kg到10kg范围内的引脚拉伸强度。
4.如权利要求1所述的无芯针栅阵列基板,其特征在于,所述PGA信号引脚具有5kg的引脚拉伸强度。
5.如权利要求1所述的无芯针栅阵列基板,其特征在于,所述PGA信号引脚为第一PGA信号引脚,进一步包括相邻的PGA信号引脚,其中所述第一PGA信号引脚和相邻的PGA信号引脚按从350μm(中心到中心)至800μm范围内的引脚间距设置。
6.如权利要求1所述的无芯针栅阵列基板,其特征在于,所述PGA信号引脚为第一PGA信号引脚,进一步包括相邻的PGA信号引脚,其中所述第一PGA信号引脚和相邻的PGA信号引脚按从450μm至500μm范围内的引脚间距设置。
7.如权利要求1所述的无芯针栅阵列基板,其特征在于,所述PGA信号引脚具有从0.6mm到1.4mm范围内的引脚长度。
8.如权利要求1所述的无芯针栅阵列基板,其特征在于,所述PGA信号引脚具有1mm的引脚长度。
9.如权利要求1所述的无芯针栅阵列基板,其特征在于,所述无芯针栅阵列基板具有从0.200μm到0.8μm范围内的厚度。
10.如权利要求1所述的无芯针栅阵列基板,其特征在于,所述无芯针栅阵列基板具有从0.400μm到0.7μm范围内的厚度。
11.如权利要求1所述的无芯针栅阵列基板,其特征在于,在所述第一中间层和所述后续的中间层之间设置数量在1与50之间的中间层,其中所述PGA信号引脚具有从3kg至10kg范围内的引脚拉伸强度,其中所述PGA信号引脚为第一PGA信号引脚,进一步包括相邻的PGA信号引脚,并且其中所述第一PGA信号引脚和相邻的PGA信号引脚按从350μm(中心到中心)到800μm范围内的引脚间距设置,其中所述PGA信号引脚为第一PGA信号引脚,进一步包括相邻的PGA信号引脚,并且其中所述第一PGA信号引脚和相邻的PGA信号引脚按从450μm到500μm范围内的引脚间距设置,其中所述PGA信号引脚具有从0.6mm到1.4mm范围内的引脚长度,并且其中所述无芯针栅阵列基板具有从0.400μm到0.8μm范围内的厚度。
12.一种芯片封装,包括:
微电子装置,所述微电子装置设置在无芯针栅阵列(PGA)基板的管芯侧上,其中所述无芯PGA基板包括:
管芯侧和焊盘侧;
PGA信号引脚,所述PGA信号引脚与所述焊盘侧集成设置,其中所述PGA信号引脚与设置在第一中间层中的第一通孔直接接触并且还与接触所述第一中间层的第一迹线直接接触;
PGA电源-接地引脚,所述PGA电源-接地引脚与所述焊盘侧集成设置,其中所述PGA电源-接地引脚与设置在所述第一中间层中的第一通孔直接接触并且还与接触所述第一中间层的第一迹线直接接触;
后续的中间层,所述后续的中间层毗邻所述管芯侧设置,其中来自所述PGA信号引脚和PGA电源-接地引脚的电连接通过所述后续的中间层耦合;
后续的迹线,所述后续的迹线与后续的中间层接触;
多个中间的中间层,所述多个中间的中间层设置在所述第一中间层和后续的中间层之间;
多个信号中间通孔,所述多个信号中间通孔将PGA信号引脚电耦合至所述管芯侧;以及
多个电源-接地中间通孔,所述多个电源-接地中间通孔将所述PGA电源-接地引脚电耦合至所述管芯。
13.如权利要求12所述的芯片封装,其特征在于,所述微电子装置倒装安装在所述管芯侧上。
14.如权利要求12所述的芯片封装,其特征在于,所述微电子装置倒装安装在所述管芯侧上,其中所述无芯PGA基板包括:
管芯侧和焊盘侧;
PGA信号引脚,所述PGA信号引脚与所述焊盘侧集成设置,其中所述PGA信号引脚与设置在第一中间层中的第一通孔直接接触并且还与接触所述第一中间层的第一迹线直接接触;
PGA电源-接地引脚,所述PGA电源-接地引脚与所述焊盘侧集成设置,其中所述PGA电源-接地引脚与设置在所述第一中间层中的第一通孔直接接触并且还与接触所述第一中间层的第一迹线直接接触;
后续的中间层,所述后续的中间层毗邻所述管芯侧设置,其中来自所述PGA信号引脚和PGA电源-接地引脚的电连接通过所述后续的中间层耦合;
后续的迹线,所述后续的迹线与后续的中间层接触;
多个中间的中间层,所述多个中间的中间层设置在所述第一中间层和后续的中间层之间;
多个信号中间通孔,所述多个信号中间通孔将PGA信号引脚电耦合至所述管芯侧;以及
多个电源-接地中间通孔,所述多个电源-接地中间通孔将所述PGA电源-接地引脚电耦合至所述管芯。
15.如权利要求12所述的芯片封装,其特征在于,所述微电子装置为第一微电子装置并且其中所述第一微电子装置倒装安装在管芯侧上,所述芯片封装进一步包括在所述管芯侧上并且毗邻所述第一微电子装置设置的后续的微电子装置。
16.如权利要求12所述的芯片封装,其特征在于,所述微电子装置为第一微电子装置,并且其中所述第一微电子装置倒装安装在管芯侧上,所述芯片封装进一步包括在所述管芯侧上并且毗邻所述第一微电子装置设置的后续的微电子装置,其中所述无芯PGA基板包括:
管芯侧和焊盘侧;
PGA信号引脚,所述PGA信号引脚与所述焊盘侧集成设置,其中所述PGA信号引脚与设置在第一中间层中的第一通孔直接接触并且还与接触所述第一中间层的第一迹线直接接触;
PGA电源-接地引脚,所述PGA电源-接地引脚与所述焊盘侧集成设置,其中所述PGA电源-接地引脚与设置在所述第一中间层中的第一通孔直接接触并且还与接触所述第一中间层的第一迹线直接接触;
后续的中间层,所述后续的中间层毗邻所述管芯侧设置,其中来自所述PGA信号引脚和PGA电源-接地引脚的电连接通过所述后续的中间层耦合;
后续的迹线,所述后续的迹线与后续的中间层接触;
多个中间的中间层,所述多个中间的中间层设置在所述第一中间层和后续的中间层之间;
多个信号中间通孔,所述多个信号中间通孔将PGA信号引脚电耦合至所述管芯侧;以及
多个电源-接地中间通孔,所述多个电源-接地中间通孔将所述PGA电源-接地引脚电耦合至所述管芯。
17.如权利要求12所述的芯片封装,其特征在于,所述微电子装置为第一微电子装置并且其中所述第一微电子装置倒装安装在管芯侧上,所述芯片封装进一步包括在所述第一微电子装置上堆叠的后续的微电子装置。
18.如权利要求12所述的芯片封装,其特征在于,所述微电子装置为第一微电子装置并且其中所述第一微电子装置倒装安装在管芯侧上,所述芯片封装进一步包括在所述第一微电子装置上堆叠的后续的微电子装置,其中所述无芯PGA基板包括:
管芯侧和焊盘侧;
PGA信号引脚,所述PGA信号引脚与所述焊盘侧集成设置,其中所述PGA信号引脚与设置在第一中间层中的第一通孔直接接触并且还与接触所述第一中间层的第一迹线直接接触;
PGA电源-接地引脚,所述PGA电源-接地引脚与所述焊盘侧集成设置,其中所述PGA电源-接地引脚与设置在所述第一中间层中的第一通孔直接接触并且还与接触所述第一中间层的第一迹线直接接触;
后续的中间层,所述后续的中间层毗邻所述管芯侧设置,其中来自所述PGA信号引脚和PGA电源-接地引脚的电连接通过所述后续的中间层耦合;
后续的迹线,所述后续的迹线与后续的中间层接触;
多个中间的中间层,所述多个中间的中间层设置在所述第一中间层和后续的中间层之间;
多个信号中间通孔,所述多个信号中间通孔将PGA信号引脚电耦合至所述管芯侧;以及
多个电源-接地中间通孔,所述多个电源-接地中间通孔将所述PGA电源-接地引脚电耦合至所述管芯。
19.如权利要求12所述的芯片封装,其特征在于,所述微电子装置为第一微电子装置,进一步包括安装在所述管芯侧上的后续的芯片封装,并且其中所述后续的芯片封装包括设置在所述后续的芯片封装上的后续的微电子装置。
20.如权利要求12所述的芯片封装,其特征在于,所述微电子装置为第一微电子装置,进一步包括安装在所述管芯侧上的后续的芯片封装,并且其中所述后续的芯片封装包括设置在所述后续的芯片封装上的后续的微电子装置,其中所述无芯PGA基板包括:
管芯侧和焊盘侧;
PGA信号引脚,所述PGA信号引脚与所述焊盘侧集成设置,其中所述PGA信号引脚与设置在第一中间层中的第一通孔直接接触并且还与接触所述第一中间层的第一迹线直接接触;
PGA电源-接地引脚,所述PGA电源-接地引脚与所述焊盘侧集成设置,其中所述PGA电源-接地引脚与设置在所述第一中间层中的第一通孔直接接触并且还与接触所述第一中间层的第一迹线直接接触;
后续的中间层,所述后续的中间层毗邻所述管芯侧设置,其中来自所述PGA信号引脚和PGA电源-接地引脚的电连接通过所述后续的中间层耦合;
后续的迹线,所述后续的迹线与后续的中间层接触;
多个中间的中间层,所述多个中间的中间层设置在所述第一中间层和后续的中间层之间;
多个信号中间通孔,所述多个信号中间通孔将PGA信号引脚电耦合至所述管芯侧;以及
多个电源-接地中间通孔,所述多个电源-接地中间通孔将所述PGA电源-接地引脚电耦合至所述管芯。
21.一种形成无芯针栅阵列基板的工艺,包括:
在针栅阵列引脚模具上形成籽晶层;
在所述籽晶层上形成PGA前驱膜;
图案化所述PGA前驱膜以实现多个间隔开的PGA引脚;以及
形成集成PGA引脚的无芯PGA基板,包括:
形成第一中间层以限定所述无芯PGA基板的焊盘侧,其中所述第一中间层在所述PGA引脚的引脚头处接触所述PGA引脚;
将通孔填充到所述第一中间层中,其中所述通孔与所述PGA引脚的引脚头接触;以及形成后续的中间层,以限定为靠近无芯PGA基板的管芯侧。
22.如权利要求21所述的工艺,进一步包括将第一微电子装置组装至所述管芯侧。
23.如权利要求21所述的工艺,进一步包括将第一微电子装置和后续的微电子装置组装至所述管芯侧。
24.一种计算机系统,包括:
微电子装置,所述微电子装置设置在无芯针栅阵列(PGA)基板的管芯侧上,其中所述无芯PGA基板包括:
管芯侧和焊盘侧;
PGA信号引脚,所述PGA信号引脚与所述焊盘侧集成设置,其中所述PGA信号引脚与设置在第一中间层中的第一通孔直接接触并且还与接触所述第一中间层的第一迹线直接接触;
PGA电源-接地引脚,所述PGA电源-接地引脚与所述焊盘侧集成设置,其中所述PGA电源-接地引脚与设置在所述第一中间层中的第一通孔直接接触并且还与接触所述第一中间层的第一迹线直接接触;
后续的中间层,所述后续的中间层毗邻所述管芯侧设置,其中来自所述PGA信号引脚和PGA电源-接地引脚的电连接通过所述后续的中间层耦合;
后续的迹线,所述后续的迹线与后续的中间层接触;
多个中间的中间层,所述多个中间的中间层设置在所述第一中间层和后续的中间层之间;
多个信号中间通孔,所述多个信号中间通孔将PGA信号引脚电耦合至所述管芯侧;以及
多个电源-接地中间通孔,所述多个电源-接地中间通孔将所述PGA电源-接地引脚电耦合至所述管芯;以及
基础基板,所述基础基板支持所述无芯PGA基板。
25.如权利要求24所述的计算机系统,其特征在于,所述基础基板为移动装置的一部分。
26.如权利要求24所述的计算机系统,其特征在于,所述基础基板为刀片服务器的一部分。
27.如权利要求24所述的计算机系统,其特征在于,所述基础基板为微服务器的一部分。
28.如权利要求24所述的计算机系统,其特征在于,所述基础基板为车辆的一部分。
29.如权利要求27所述的计算机系统,其特征在于,所述基础基板为电视机的一部分。
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