TWI559481B - 用於無核心基體之原處建置接腳柵格陣列及其製造方法 - Google Patents
用於無核心基體之原處建置接腳柵格陣列及其製造方法 Download PDFInfo
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- TWI559481B TWI559481B TW101120104A TW101120104A TWI559481B TW I559481 B TWI559481 B TW I559481B TW 101120104 A TW101120104 A TW 101120104A TW 101120104 A TW101120104 A TW 101120104A TW I559481 B TWI559481 B TW I559481B
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Description
揭露之實施例係有關於接腳柵格陣列基體。
本發明係有關於接腳柵格陣列基體。
依據本發明之一實施例,係特地提出一種無核心接腳柵格陣列基體,包含:一晶粒側及一焊墊側;一接腳柵格陣列(PGA)信號接腳,其設置成與該焊墊側形成一體,其中該PGA信號接腳與設置在一第一間層中之一第一通孔直接接觸且亦與接觸該第一間層之一第一線路直接接觸;一PGA電力-接地接腳,其設置成與該焊墊側形成一體,其中該PGA電力-接地接腳與設置在該第一間層中之一第一通孔直接接觸且亦與接觸該第一間層之一第一線路直接接觸;一後續間層,其設置成與該晶粒側相鄰,其中來自該PGA信號接腳與該PGA電力-接地接腳之多數電連接係透過該後續間層耦合;一後續線路,其與該後續間層接觸;多數中間間層,其設置在該第一間層與後續間層之間;多數信號中間通孔,其電耦合該PGA信號接腳與該晶粒側;及,多數電力-接地中間通孔,其耦合該PGA電力-接地接腳與該晶粒側。
依據本發明之一實施例,係特地提出一種晶片封裝體,包含:一微電子裝置,其設置在一無核心接腳柵格陣
列(PGA)基體之一晶粒側上,其中該無核心PGA基體包括:該晶粒側及一焊墊側;一PGA信號接腳,其設置成與該焊墊側形成一體,其中該PGA信號接腳與設置在一第一間層中之一第一通孔直接接觸且亦與接觸該第一間層之一第一線路直接接觸;一PGA電力-接地接腳,其設置成與該焊墊側形成一體,其中該PGA電力-接地接腳與設置在該第一間層中之一第一通孔直接接觸且亦與接觸該第一間層之一第一線路直接接觸;一後續間層,其設置成與該晶粒側相鄰,其中來自該PGA信號接腳與該PGA電力-接地接腳之多數電連接係透過該後續間層耦合;一後續線路,其與該後續間層接觸;多數中間間層,其設置在該第一間層與後續間層之間;多數信號中間通孔,其電耦合該PGA信號接腳與該晶粒側;及,多數電力-接地中間通孔,其耦合該PGA電力-接地接腳與該晶粒。
依據本發明之一實施例,係特地提出一種形成一無核心接腳柵格陣列基體之製程,包含:在一接腳柵格陣列接腳模具上形成一晶種層;在該晶種層上形成一PGA先質薄膜;使該PGA先質薄膜圖案化以得到多數分開PGA接腳;及形成一與該等PGA接腳一體地結合之無核心PGA基體,包括:形成一第一間層以界定該無核心PGA基體之一焊墊側,其中該第一間層與該等PGA接腳在其接腳頭處接觸;將一通孔填入該第一間層,其中該通孔與該等PGA接腳之一接腳頭直接接觸;及,形成一後續間層以鄰接地界定該無核心PGA基體之一晶粒側。
依據本發明之一實施例,係特地提出一種電腦系統,包含:一微電子裝置,其設置在一無核心接腳柵格陣列(PGA)基體之一晶粒側上,其中該無核心PGA基體包括:該晶粒側及一焊墊側;一PGA信號接腳,其設置成與該焊墊側形成一體,其中該PGA信號接腳與設置在一第一間層中之一第一通孔直接接觸且亦與接觸該第一間層之一第一線路直接接觸;一PGA電力-接地接腳,其設置成與該焊墊側形成一體,其中該PGA電力-接地接腳與設置在該第一間層中之一第一通孔直接接觸且亦與接觸該第一間層之一第一線路直接接觸;一後續間層,其設置成與該晶粒側相鄰,其中來自該PGA信號接腳與該PGA電力-接地接腳之多數電連接係透過該後續間層耦合;一後續線路,其與該後續間層接觸;多數中間間層,其設置在該第一間層與後續間層之間;多數信號中間通孔,其電耦合該PGA信號接腳與該晶粒側;及,多數電力-接地中間通孔,其耦合該PGA電力-接地接腳與該晶粒;及,一底基體,其支持該無核心PGA基體。
為了解實施例獲得之方式,將藉由參照附加圖式提供以上簡單說明之各種實施例之一更特定說明。這些圖式描述不一定依比例繪製且不應被視為限制範圍之多數實施例。某些實施例將以另外特性及細節透過使用該等添附圖式說明及解釋,其中:第1圖是依據一實施例之具有多數一體接腳之一無核
心接腳柵格陣列基體的橫截面圖;第1a圖是依據一實施例之在第1圖中所示之無核心接腳柵格陣列基體在加工時的橫截面圖;第1b圖是依據一實施例之在第1a圖中所示之無核心接腳柵格陣列基體在加工時的橫截面圖;第1c圖是依據一實施例之在第1b圖中所示之無核心接腳柵格陣列基體在加工時的橫截面圖;第1d圖是依據一實施例之在第1c圖中所示之無核心接腳柵格陣列基體在加工時的橫截面圖;第2圖是包括依據一實施例之具有多數一體接腳之一無核心接腳柵格陣列基體之一多晶片封裝體的橫截面圖;第3圖是包括依據一實施例之具有多數一體接腳之一無核心接腳柵格陣列基體之一堆疊晶片封裝體的橫截面圖;第4圖是包括依據一實施例之具有多數一體接腳之一無核心接腳柵格陣列基體之一疊合式封裝體的橫截面圖;第5圖是依據一實施例之一製程及方法流程圖;及第6圖是依據一實施例之一電腦系統的示意圖。
以下揭露其中多數無核心接腳柵格陣列基體與多數微電子裝置組裝及耦合作為多數晶片封裝體之多數製程。
以下將參照其中類似結構可具有類似後綴符號表示之圖式。為更清楚地顯示各種實施例之結構,在此包括之圖
式係積體電路結構之示意圖。因此,例如在一顯微照片中,單獨或在多數晶片封裝體中製成之晶片基體的真正外觀會看起來不同,但是仍具有所示實施例之請求保護的結構。此外,該等圖式可只顯示對了解所示實施例有幫助之結構。可能不會包括在所屬技術領域中習知之其他結構以保持該等圖式之清晰性。
第1圖是依據一實施例之作為一晶片封裝體100之具有多數一體接腳之一無核心接腳柵格陣列(PGA)基體110的橫截面圖。可了解的是“一體接腳”表示該等PGA接腳係與該無核心PGA基體110在原處形成。
顯示之一無核心PGA基體110具有多數接腳112。該等接腳112包括多數接腳頭114。作為一單元,該等接腳112及接腳頭114係該無核心PGA基體110之一部份使得該無核心PGA基體110已製成為一包括該等接腳112之一體結構。換言之,沒有使用焊料耦合該等接腳112與該無核心PGA基體110。在製造該無核心PGA基體110時,該等接腳112係製成為其一體部份。該等接腳頭114亦為該PGA之多數墊114,但是它們係與該等接腳頭114形成一體。
如圖所示,包括該等接腳頭114之接腳112係透過多數信號通孔116及多數電力-接地通孔118附接於該無核心PGA基體110。類似地,該等電力-接地通孔118亦直接接觸該等接腳頭114。在這揭露中“直接接觸”表示該等接腳116在該等通孔116與118及該等接腳頭114之間沒有例如焊料之中間電結構。
在一實施例中,該等電力-接地通孔118係構形為一既定接腳頭114有多數個,例如一既定接腳頭有兩個。這與構形為既定接腳頭有單一通孔之信號通孔116形成對比。換言之,一既定接腳頭之信號通孔的數目小於一既定接腳頭之電力-接地通孔的數目。如在一實施例中所示,該信號通孔116是一既定接腳有單一通孔且該電力-接地通孔118係多於信號通孔之數目。例如在一實施例中,該信號通孔116是一既定接腳有單一通孔且一既定接腳之電力-接地通孔118的數目比信號通孔數目多1。換言之,在一實施例中,每接腳頭之電力-接地通孔的數目是每接腳頭之信號通孔數目的兩倍。
一第一中間層120分別封閉該等信號-及電力-接地通孔116與118,且在該無核心PGA基體110之一接腳側一體地結合該等接腳頭114於其內。由於該PGA與例如一母板之一底基體連接,因此該接腳側亦被稱為焊墊(land)側。該無核心PGA基體110更在該等接腳112及接腳頭114製造有多數線路,且其中一線路係以122表示。因為該線路122與該第一間層120接觸,所以它可被稱為一第一層線路122。一第二間層124係抵靠該第一間層120製成。該PGA基體110繼續再增層直到一後續間層126及一焊料遮罩128形成其一晶粒側之一部份。一後續線路130與該後續間層126接觸。在一實施例中,由該第一間層120至該後續間層126之層數係在一由2至15之範圍內。在一實施例中,由該第一間層120至該後續間層126之層數係在一由3至9之範圍內。就該等無核心
PGA基體揭露數種質與量。在一實施例中,該PGA108之各接腳112具有一接腳長度132及一接腳頭寬度134。任兩相鄰接腳112係中心分開136。
該PGA基體110及該PGA108係構形為一晶片封裝體100,且該晶片封裝體100支持一微電子裝置138,例如由加州Santa Clara之Intel公司製造之一處理器。該微電子裝置138可構形為一倒裝晶片138且藉由多數電凸塊與該無核心PGA基體110耦合,且其中一電凸塊係以符號140表示。
在一實施例中,該PGA基體110具有一在由0.200微米(μm)至0.8μm之範圍內的厚度。在一實施例中,該PGA基體110具有一0.7μm之厚度。可使用其他厚度。
“接腳-抗拉強度”係定義為施加在接腳112上直到它斷裂為止,這表示直到它由該無核心基體110撕離為止之拉力。在一實施例中,接腳-抗拉強度係在一由3kg至10kg之範圍內。在一實施例中,接腳-抗拉強度是5kg。對於具有一通孔直徑60μm之2-通孔例的一實施例而言,該接腳-抗拉強度大於5kg,例如10kg。
依據所揭露之實施例,接腳間距136相對於習知技術減少。在一實施例中,接腳間距136係在一由350μm(中心至中心)至800μm之範圍內。在一實施例中,接腳間距136係在一由400μm至550μm之範圍內。在一實施例中,接腳間距136係在一由450μm至500μm之範圍內。
依據所揭露之實施例,接腳長度132相對於習知技術減少。在一實施例中,接腳長度132係在一由0.6mm至1.4mm
之範圍內。在一實施例中,接腳長度132係在一由0.8mm至1.2mm之範圍內。在一實施例中,接腳長度132係1mm。在一實施例中,長度132除以寬度133之接腳長寬比係在一由5:1至20:1之範圍內。
在一實施例中,該無核心PGA基體110係組裝至例如一膝上或筆記型電腦之一移動型系統作為一晶片封裝體100。一底基體190係顯示為該等接腳112可插入其中。在一實施例中,該底基體190是一刀峰型伺服器之一部份的一板。在一實施例中,該底基體190是一微型伺服器之一部份的一板。在一實施例中,該底基體190是一板,例如用於如一平板電腦之移動型電腦之一母板。
第1a圖是第1a圖是依據一實施例之在第1圖中所示之無核心接腳柵格陣列基體110在加工時的橫截面圖。一先質結構101係構形成具有一PGA接腳模具142。該PGA接腳模具142可放置成抵靠一類似PGA接腳模具142'以達成製造實用性。該PGA接腳模具142及該類似PGA接腳模具142'可藉由一離型層144附接,且該離型層144在稍後加工中被用來分離不同PGA無核心基體。進一步加工將提及藉由使用該PGA接腳模具142製造之該無核心PGA基體,但是可推及用於該類似PGA接腳模具142'之加工。
在一實施例中,該PGA接腳模具142係藉由無電極方法加工以將一晶種層146黏著在其上。該PGA接腳模具142包括多數接腳凹部,其中一凹部係以符號148表示。該晶種層146覆蓋該PGA接腳模具142且進入該等凹部148。數個凹部
148之間隔係構形成可配合一有用設計,例如用於第1圖及在這揭露中其他地方所示結構之任何所述實施例。在一實施例中,一500μm之接腳間距134係由該選定之PGA接腳模具142建立。
第1b圖是依據一實施例之在第1a圖中所示之無核心接腳柵格陣列基體在加工時的橫截面圖。該先質結構102包括該PGA接腳模具142,且該PGA接腳模具142已藉由利用該晶種層146作為一陰極電鍍一接腳柵格陣列先質薄膜150加工。在一實施例中,該晶種層146是電氣級銅且該PGA先質薄膜150亦是電氣級銅。
第1c圖是依據一實施例之在第1b圖中所示之無核心接腳柵格陣列基體在加工時的橫截面圖。該先質結構103包括該PGA接腳模具142,且該PGA接腳模具142已藉由蝕刻一圖案在該PGA先質薄膜150中加工以形成多數獨立之分開接腳112。加工亦將多數接腳頭114形成為該等接腳112之一部份。
第1d圖是依據一實施例之在第1c圖中所示之無核心接腳柵格陣列基體在加工時的橫截面圖。兩相對PGA基體104已藉由一連串增層形成,且該等增層包括在第1d圖中之中間加工時顯示之PGA基體110。如圖所示,該等接腳112已被一第一間層120覆蓋,且該等信號-及電力-接地通孔116與118已分別形成在該第一間層120中。該第一間層120亦一體地結合該等接腳頭114在其內。該PGA基體110更在該等接腳112及接腳頭114製造有多數第一層線路,且其中一線
路係以122表示。一第二間層124係抵靠該第一間層120製成。該PGA基體110繼續再增層直到一後續間層126(第1圖)及一焊料遮罩128為止。
在一實施例中,該PGA108之各接腳112具有一接腳長度132及一接腳頭寬度133。任兩相鄰接腳係中心分開136。該PGA基體100及該PGA108係構形為一晶片封裝體,且該晶片封裝體支持一微電子裝置138。該微電子裝置138可構形為一倒裝晶片138且藉由多數電凸塊與該無核心PGA基體110耦合,且其中一電凸塊係以符號140表示。
第2圖是包括依據一實施例之具有多數一體接腳之一無核心接腳柵格陣列基體210之一多晶片封裝體200的橫截面圖。顯示之一無核心PGA基體210具有多數接腳212。該等接腳212包括多數接腳頭214。作為一單元,該等接腳212及接腳頭214係該PGA基體210之一部份使得該PGA基體210已製成為一包括該等接腳212之一體結構。換言之,沒有使用焊料耦合該等接腳212與該無核心PGA基體210。在製造該無核心PGA基體210時,該等接腳212係製成為其一體部份。如圖所示,包括該等接腳頭214之接腳212係類似於對第1圖所示之晶片封裝體110之揭露地透過多數信號通孔216及多數電力-接地通孔218附接於該無核心PGA基體210。一第一中間層220分別封閉該等信號-及電力-接地通孔216與218,且在該無核心PGA基體210之一接腳側一體地結合該等接腳頭214於其內。該無核心PGA基體210更在該等接腳212及接腳頭214製造有多數線路,且其中一線路係以
222表示。因為該線路222與該第一間層220接觸,所以它可被稱為一第一層線路222。一第二間層224係抵靠該第一間層220製成。該PGA基體210繼續再增層直到一後續間層226及一焊料遮罩228形成其一晶粒側之一部份。一後續線路230與該後續間層226接觸。
該PGA基體210及該PGA208係構形為一晶片封裝體200,且該晶片封裝體200支持例如由加州Santa Clara之Intel公司製造之一處理器的一微電子裝置238,以及一後續微電子裝置248。在一實施例中,該微電子裝置238是一倒裝晶片238且藉由多數電凸塊與該無核心PGA基體210耦合,且其中一電凸塊係以符號240表示,並且該後續微電子裝置248是一安裝成該主動表面遠離該無核心PGA基體210之晶粒側的線接合250晶片。在一實施例中,該裝置238是一處理器且該裝置248是一射頻裝置。在一實施例中,兩晶片都類似該微電子裝置238地倒裝晶片安裝。
至此可了解的是在第1圖所示與所述之無核心基體110的無核心基體性質可適用於該多晶片封裝體無核心PGA基體210。至此可了解的是該無核心PGA基體210可與例如在第1圖中所示與所述之底基體190實施例的底基體連接。
第3圖是包括依據一實施例之具有多數一體接腳之一無核心接腳柵格陣列基體310之一堆疊晶片封裝體300的橫截面圖。顯示之一無核心PGA基體310具有多數接腳312。該等接腳312包括多數接腳頭314。作為一單元,該等接腳312及接腳頭314係該PGA基體310之一部份使得該PGA基
體310已製成為一包括該等接腳312之一體結構。換言之,沒有使用焊料耦合該等接腳312與該無核心PGA基體310。在製造該無核心PGA基體310時,該等接腳312係製成為其一體部份。如圖所示,包括該等接腳頭314之接腳312係類似於對第1圖所示之晶片封裝體310及包括第2圖所示之無核心PGA基體210之多晶片封裝體200的揭露地透過多數信號通孔316及多數電力-接地通孔318附接於該無核心PGA基體310。一第一中間層320分別封閉該等信號-及電力-接地通孔316與318,且在該無核心PGA基體310之一接腳側一體地結合該等接腳頭314於其內。該無核心PGA基體310更在該等接腳312及接腳頭314製造有多數線路,且其中一線路係以322表示。因為該線路322與該第一間層320接觸,所以它可被稱為一第一層線路322。一第二間層324係抵靠該第一間層320製成。該PGA基體310繼續再增層直到一後續間層326及一焊料遮罩328形成其一晶粒側之一部份。一後續線路330與該後續間層326接觸。
該PGA基體310及該PGA308係構形為一堆疊晶片封裝體300,且該堆疊晶片封裝體300支持例如由加州Santa Clara之Intel公司製造之一處理器的一微電子裝置338,以及一堆疊後續微電子裝置348。在一實施例中,該微電子裝置338是一貫穿矽通孔352倒裝晶片338且藉由多數電凸塊與該無核心PGA基體310耦合,且其中一電凸塊係以符號340表示,並且該後續微電子裝置354是一安裝成該主動表面面向該無核心PGA基體310之晶粒側的倒裝晶片354且與該等
TSV耦合。在一實施例中,該裝置338是一處理器且該裝置348是例如一固態磁碟機之一記憶裝置。至此可了解的是在第1與2圖所示與所述之無核心基體110與210的無核心基體性質可適用於該堆疊晶片封裝體無核心PGA基體310且反之亦然。至此可了解的是該無核心PGA基體310可與例如在第1圖中所示與所述之底基體190實施例的底基體連接。
第4圖是包括依據一實施例之具有多數一體接腳412之一無核心接腳柵格陣列基體410之一疊合式封裝體400的橫截面圖。顯示之一無核心PGA基體410具有多數接腳412。該等接腳412包括多數接腳頭414。作為一單元,該等接腳412及接腳頭414係該PGA基體410之一部份使得該PGA基體410已製成為一包括該等接腳412之一體結構。換言之,沒有使用焊料耦合該等接腳412與該無核心PGA基體410。在製造該無核心PGA基體410時,該等接腳412係製成為其一體部份。如圖所示,包括該等接腳頭414之接腳412係類似於對第1圖所示之晶片封裝體110,包括第2圖所示之無核心PGA基體210之多晶片封裝體200及第3圖所示之堆疊晶片封裝體300的揭露地透過多數信號通孔416及多數電力-接地通孔418附接於該無核心PGA基體410。一第一中間層420分別封閉該等信號-及電力-接地通孔416與418,且在該無核心PGA基體410之一接腳側一體地結合該等接腳頭414於其內。該無核心PGA基體410更在該等接腳412及接腳頭414製造有多數線路,且其中一線路係以422表示。因為該線路422與該第一間層420接觸,所以它可被稱為一第一層
線路422。一第二間層424係抵靠該第一間層420製成。該PGA基體410繼續再增層直到一後續間層426及一焊料遮罩428形成其一晶粒側之一部份。一後續線路430與該後續間層426接觸。
該PGA基體410及該PGA408係構形為一疊合式晶片封裝體(POP)400,且該疊合式晶片封裝體400支持例如由加州Santa Clara之Intel公司製造之一處理器的一微電子裝置438,以及一POP後續微電子裝置448。在一實施例中,該微電子裝置438係藉由多數電凸塊與該無核心PGA基體410耦合,且其中一電凸塊係以符號440表示,並且該POP後續微電子裝置454是一安裝成該主動表面面向一POP基體460,且該POP基體460係利用POP電凸塊462安裝在該無核心PGA基體410之晶粒側。在一實施例中,該裝置438是一處理器且該裝置448是例如一固態磁碟機之一記憶裝置。至此可了解的是在第1、2與3圖所示與所述之無核心基體110、210與310的無核心基體性質可適用於該POP無核心PGA基體410且反之亦然。至此可了解的是該無核心PGA基體410可與例如在第1圖中所示與所述之底基體190實施例的底基體連接。
第5圖是依據一實施例之一製程及方法流程圖500。
在步驟510,一製程包括在一PGA接腳模具上形成一晶種層。在一非限制實施例中,該銅晶種層146係藉由無電電鍍形成在該接腳模具142上。
在步驟520,該製程包括在該晶種層上形成一PGA先質
薄膜。在一非限制實施例中,該晶種層146是一電氣級銅且被用來作為一陰極以形成亦為電氣級銅之接腳柵格先質150。
在步驟530,該製程包括使該接腳柵格先質以形成多數獨立之分開接腳。在一非限制實施例中,該等接腳112係藉由依據一圖案蝕刻該接腳柵格先質而形成。
在步驟540,該製程包括形成一無核心接腳柵格陣列基體,且該無核心接腳柵格陣列基體結合該等分開接腳成為其一體部份。換言之,在該等無核心PGA基體中沒有使用焊料接合該等接腳與該等通孔。在一非限制實施例中,該第一間層120分別封閉該等信號-及電力-接地通孔116與118,且在該無核心接腳柵格陣列基體110之一接腳側一體地結合該等接腳頭114於其內。此外,依據這實施例之進一步加工包括形成數個間層之線路及介電體直到在該無核心接腳柵格陣列基體110之晶粒側形成後續間層126及焊料遮罩128為止。在一實施例中,該製程在步驟510開始且在步驟540結束。
在步驟550,該製程包括組裝一微電子裝置與該無核心接腳柵格陣列基體。在一非限制實施例中,該處理器138係倒裝晶片安裝在該無核心接腳柵格陣列基體110上。在一非限制實施例中,該處理器238係倒裝晶片安裝在該多晶片無核心接腳柵格陣列基體210上且該裝置248係線接合組裝在該多晶片無核心接腳柵格陣列基體210上。在一非限制實施例中,該貫穿矽通孔處理器338係倒裝晶片安裝在該無核心
接腳柵格陣列基體310上且該裝置354係藉由與一貫穿矽通孔352耦合而與該處理器338倒裝晶片結合。在一非限制實施例中,該後續裝置448係POP組裝在該無核心接腳柵格陣列基體410上。在一實施例中,該製程在步驟510開始且在步驟550結束。在一實施例中,該方法在步驟540開始且在步驟550結束。
在一方法實施例之步驟560中,組裝該無核心PGA基體與一電腦系統,例如如第6圖所示之任何電腦系統。
第6圖是依據一實施例之一電腦系統的示意圖。如圖所示之電腦系統600(亦稱為電子系統600)可以依據在這揭露中提出之數個揭露之實施例之任一實施例之一無核心接腳柵格陣列基體及其等效物來實施。包括一無核心接腳柵格陣列基體之一設備係組裝在一電腦系統600上。該電腦系統600可以是一行動裝置,例如一筆記型電腦。該電腦系統600可以是一桌上型電腦。該電腦系統600可與一汽車形成一體。該電腦系統600可與一電視形成一體。該電腦系統600可與一DVD播放器形成一體。該電腦系統600可與一數位攝錄影機形成一體。
在一實施例中,該電子系統600是一電腦系統,且該電腦系統包括一系統匯流排620以便電耦合該電腦系統600之各種組件。依據各種實施例,該系統匯流排620是單一匯流排或多數匯流排之任何組合。該電腦系統600包括一提供電力至該積體電路610之電壓源630。在某些實施例中,該電壓源630透過該系統匯流排620供應電流至該積體電路610。
該積體電路610係與該系統匯流排620電耦合且依據一實施例包括任何電路、或多數電路之組合。在一實施例中,該積體電路610包括一處理器612,且該處理器612可以是包括一無核心接腳柵格陣列基體實施例之任一種設備。如在此使用地,該處理器612可表示任一種電路,例如,但不限於:一微處理器、一微控制器、一圖形處理器、一數位信號處理器、或其他處理器。在一實施例中,SRAM實施例係在該處理器之記憶體快取中找到。可以包括在該積體電路610中之其他種類的電路係一常用電路或一特殊應用積體電路(ASIC),例如一供例如行動電話、智慧型手機、呼叫器、可攜式電腦、雙向無線電及類似電子系統之無線裝置使用的通訊電路614。在一實施例中,該處理器610包括晶粒上記憶體616,例如靜態隨機存取記憶體(SRAM)。在一實施例中,該處理器610包括埋入式晶粒上記憶體616,例如埋入式動態隨機存取記憶體(eDRAM)。
在一實施例中,該積體電路610附加有一後續積體電路611,例如如在這揭露中所述之一圖形處理器或一射頻積體電路或兩者。在一實施例中,該雙積體電路610包括埋入式晶粒上記憶體617,例如eDRAM。該雙積體電路611及雙晶粒上記憶體617,例如SRAM。在一實施例中,該雙通訊電路615係特別構形成用以進行RF處理。
在一實施例中,至少一被動裝置680係與該後續積體電路611耦合使得該積體電路611與該至少一被動裝置係包括一無核心接腳柵格陣列基體之任何設備實施例之一部份,
且該無核心接腳柵格陣列基體包括該積體電路610及該積體電路611。
在一實施例中,該電子系統600包括一天線元件682,例如在這揭露中所示之任何無核心接腳柵格陣列基體實施例。藉由使用該天線元件682,例如一電視之一遠距裝置684可藉由一設備實施例透過無線連結遠距地操作。例如,在透過一無線連結操作之一智慧型手機上之一應用程式藉由例如藍芽(Bluetooth®)技術傳送指令至一電視遠達大約30公尺。
在一實施例中,該電子系統600亦包括一外記憶體640,且該外記憶體640又可包括適於例如RAM形式之一主記憶體642的一或多個記憶體元件,一或多個硬碟644,及/或處理例如磁片、光碟(CD)、數位多功光碟(DVD)、隨身碟(flash memory drive)及其他可移除媒體之可移除媒體646的一或多個磁碟機。在一實施例中,該外記憶體640係堆疊成一TSV晶片,且該TSV晶片已組裝在依據任一揭露實施例之一無核心接腳柵格陣列基體上。在一實施例中,該外記憶體640是埋入式記憶體648使得一設備包括一TSV晶片,且該TSV晶片對接於依據任一揭露實施例之一無核心接腳柵格陣列基體。
在一實施例中,該電子系統600亦包括一顯示裝置650,及一聲音輸出660。在一實施例中,該電子系統600包括例如一控制器670之一輸入裝置,且該控制器670可為一鍵盤、滑鼠、觸控板、小鍵盤、軌跡球、遊戲控制器、麥
克風、語音辨識裝置或將資訊輸入該電子系統600之任何其他輸入裝置。在一實施例中,一輸入裝置670包括一相機。在一實施例中,一輸入裝置670包括一數位錄音機。在一實施例中,一輸入裝置670包括一相機及一數位錄音機。
一底基體690可以是該電腦系統600之一部份。在一實施例中,該底基體690是支持一設備之母板,且該設備包括一無核心接腳柵格陣列基體。在一實施例中,該底基體690是支持一設備之一刀峰型伺服器之一部份,且該設備包括一無核心接腳柵格陣列基體。在一實施例中,該底基體690是支持一設備之一微型伺服器之一部份,且該設備包括一無核心接腳柵格陣列基體。可了解的是例如一無核心接腳柵格陣列基體之一第二低成本封裝體可以是該電腦系統600之一部份及一與該第二低成本封裝體組合之母板。在一實施例中,該底基體690是支持一設備之一板,且該設備包括一無核心接腳柵格陣列基體。在一實施例中,該底基體690具有包含在該虛線690內之功能性的至少一功能性且是一無線通訊器之使用者外殼。
如在此所示,該積體電路610可以實施在多數不同實施例,包括依據數個揭露實施例之任一實施例及其等效物的一設備,一電子系統,一電腦系統,製造一積體電路之一或多個方法,及製造及組裝包括在各種實施例中在此提出之數個揭露實施例之任一實施例之一無核心接腳柵格陣列基體及領域中習知之等效物之一設備的一或多個方法中。該等元件,材料,幾何形狀,尺寸,及操作順序均可改變
以配合包括無核心接腳柵格陣列基體實施例及其等效物之多數特定I/O耦合要求。
雖然在相同句子中一晶粒可說成是一處理器晶片、一RF晶片、一RFIC晶片、IPD晶片或一記憶體晶片,但是這應解釋為它們是相等結構。在全部這揭露中所稱之“一個實施例”或“一實施例”表示關於該實施例所述之一特定特徵、結構或特性包含在本發明之至少一個實施例中。在全部這揭露中多數不同處中之片語“在一個實施例中”或“在一實施例中”的出現不一定全部指的是相同實施例。此外,該等特定特徵、結構或特性可以任何適當方式在一或多個實施例中組合。
例如“上”及“下”,“以上”及“以下”之用語可藉由參照所示之X-Z座標了解,且例如“相鄰”之用語可藉由參照X-Y座標或非Z-座標了解。
該摘要部份係提供來遵守要求可讓一讀者快速地確定該技術揭露之本質及要旨之一摘要的37 C.F.R.§1.72(b)。它係在了解它不被用來判讀或限制申請專利範圍之範圍或意義的情形下呈送。
在前述詳述說明中,各種特徵係集合在一單一實施例中以達到精簡該揭露之目的。這揭露之方法不應被解讀為表達本發明之實施例需要比在各申請專利範圍中特別列舉者更多之特徵的一意圖。相反地,如以下申請專利範圍表達地,本發明之標的物包含在少於一單一揭露實施例之所有特徵中。因此以下申請專利範圍在此加入該詳細說明,
且各申請專利範圍可獨立地作為一另外的較佳實施例。
所屬技術領域中具有通常知識者可輕易了解的是可在不偏離如在附加申請專利範圍中所述之本發明原理及範疇之情形下,在已為了解釋本發明之本質所說明及顯示之細節、材料及配置可有各種其他變化。
100‧‧‧晶片封裝體
101,102,103‧‧‧先質結構
104‧‧‧PGA基體
108‧‧‧PGA
110‧‧‧無核心接腳柵格陣列(PGA)基體
112‧‧‧接腳
114‧‧‧接腳頭;墊
116‧‧‧信號通孔
118‧‧‧電力-接地通孔
120‧‧‧第一間層
122‧‧‧線路
124‧‧‧第二間層
126‧‧‧後續間層
128‧‧‧焊料遮罩
130‧‧‧後續線路
132‧‧‧接腳長度
133‧‧‧接腳寬度
134‧‧‧接腳頭寬度
136‧‧‧接腳間距
138‧‧‧微電子裝置;倒裝晶片
140‧‧‧電凸塊
142‧‧‧PGA接腳模具
142'‧‧‧類似PGA接腳模具
144‧‧‧離型層
146‧‧‧晶種層
148‧‧‧凹部
150‧‧‧接腳柵格陣列(PGA)先質薄膜
190‧‧‧底基體
200‧‧‧多晶片封裝體
208‧‧‧PGA
210‧‧‧無核心接腳柵格陣列(PGA)基體
212‧‧‧接腳
214‧‧‧接腳頭
216‧‧‧信號通孔
218‧‧‧電力-接地通孔
220‧‧‧第一間層
222‧‧‧線路
224‧‧‧第二間層
226‧‧‧後續間層
228‧‧‧焊料遮罩
230‧‧‧後續線路
238‧‧‧微電子裝置;倒裝晶片
240‧‧‧電凸塊
248‧‧‧後續微電子裝置
250‧‧‧線接合
300‧‧‧堆疊晶片封裝體
308‧‧‧PGA
310‧‧‧無核心接腳柵格陣列(PGA)基體
312‧‧‧接腳
314‧‧‧接腳頭
316‧‧‧信號通孔
318‧‧‧電力-接地通孔
320‧‧‧第一間層
322‧‧‧線路
324‧‧‧第二間層
326‧‧‧後續間層
328‧‧‧焊料遮罩
330‧‧‧後續線路
338‧‧‧微電子裝置;倒裝晶片
340‧‧‧電凸塊
348‧‧‧堆疊後續微電子裝置
352‧‧‧貫穿矽通孔(TSV)
354‧‧‧後續微電子裝置;倒裝晶片
400‧‧‧疊合式晶片封裝體(POP)
408‧‧‧PGA
410‧‧‧無核心接腳柵格陣列(PGA)基體
412‧‧‧接腳
414‧‧‧接腳頭
416‧‧‧信號通孔
418‧‧‧電力-接地通孔
420‧‧‧第一間層
422‧‧‧線路
424‧‧‧第二間層
426‧‧‧後續間層
428‧‧‧焊料遮罩
438‧‧‧微電子裝置
440‧‧‧電凸塊
448‧‧‧疊合式(POP)後續微電子裝置
454‧‧‧疊合式(POP)後續微電子裝置;倒裝晶片
460‧‧‧POP基體
462‧‧‧POP電凸塊
500‧‧‧流程圖
510,520,530,540,550,560‧‧‧步驟
600‧‧‧電腦系統;電子系統
610,611‧‧‧積體電路
612‧‧‧處理器
613‧‧‧RFIC雙處理器
614‧‧‧通訊電路
615‧‧‧雙通訊電路
616‧‧‧晶粒上記憶體;埋入式晶粒上記憶體
617‧‧‧雙晶粒上記憶體;埋入式晶粒上記憶體
620‧‧‧系統匯流排
630‧‧‧電壓源
640‧‧‧外記憶體
642‧‧‧主記憶體
644‧‧‧硬碟
646‧‧‧可移除媒體
648‧‧‧埋入式記憶體
650‧‧‧顯示裝置
660‧‧‧聲音輸出
670‧‧‧輸入裝置;控制器
680‧‧‧被動裝置
682‧‧‧天線元件
684‧‧‧遠距裝置
690‧‧‧底基體;虛線
第1圖是依據一實施例之具有多數一體接腳之一無核心接腳柵格陣列基體的橫截面圖;第1a圖是依據一實施例之在第1圖中所示之無核心接腳柵格陣列基體在加工時的橫截面圖;第1b圖是依據一實施例之在第1a圖中所示之無核心接腳柵格陣列基體在加工時的橫截面圖;第1c圖是依據一實施例之在第1b圖中所示之無核心接腳柵格陣列基體在加工時的橫截面圖;第1d圖是依據一實施例之在第1c圖中所示之無核心接腳柵格陣列基體在加工時的橫截面圖;第2圖是包括依據一實施例之具有多數一體接腳之一無核心接腳柵格陣列基體之一多晶片封裝體的橫截面圖;第3圖是包括依據一實施例之具有多數一體接腳之一無核心接腳柵格陣列基體之一堆疊晶片封裝體的橫截面圖;第4圖是包括依據一實施例之具有多數一體接腳之一無核心接腳柵格陣列基體之一疊合式封裝體的橫截面圖;第5圖是依據一實施例之一製程及方法流程圖;及
第6圖是依據一實施例之一電腦系統的示意圖。
100‧‧‧晶片封裝體
108‧‧‧PGA
110‧‧‧無核心接腳柵格陣列(PGA)基體
112‧‧‧接腳
114‧‧‧接腳頭;墊
116‧‧‧信號通孔
118‧‧‧電力-接地通孔
120‧‧‧第一間層
122‧‧‧線路
124‧‧‧第二間層
126‧‧‧後續間層
128‧‧‧焊料遮罩
130‧‧‧後續線路
132‧‧‧接腳長度
133‧‧‧接腳寬度
134‧‧‧接腳頭寬度
136‧‧‧接腳間距
138‧‧‧微電子裝置;倒裝晶片
140‧‧‧電凸塊
190‧‧‧底基體
Claims (24)
- 一種無核心接腳柵格陣列基體,包含:一晶粒側及一焊墊側;一接腳柵格陣列(PGA)信號接腳,其設置成與該焊墊側形成一體,其中該PGA信號接腳與設置在一第一間層中之一第一通孔直接接觸,且亦與接觸該第一間層之一第一層線路直接接觸;一PGA電力-接地接腳,其設置成與該焊墊側形成一體,其中該PGA電力-接地接腳與設置在該第一間層中之一第一通孔直接接觸,且亦與接觸該第一間層之一第一層線路直接接觸;一後續間層,其設置成與該晶粒側相鄰,其中來自該PGA信號接腳與該PGA電力-接地接腳之多數電連接係透過該後續間層耦合;一後續線路,其與該後續間層接觸;多數中間間層,其設置在該第一間層與後續間層之間;多數信號中間通孔,其將該PGA信號接腳電耦合至該晶粒側;及多數電力-接地中間通孔,其將該PGA電力-接地接腳電耦合至該晶粒側。
- 如申請專利範圍第1項之無核心接腳柵格陣列基體,其中該第一間層與該後續間層之間設有1至50個之間的間層。
- 如申請專利範圍第1項之無核心接腳柵格陣列基體,其中該PGA信號接腳具有一在3kg至10kg之範圍內之接腳抗拉強度。
- 如申請專利範圍第1項之無核心接腳柵格陣列基體,其中該PGA信號接腳具有一5kg之接腳抗拉強度。
- 如申請專利範圍第1項之無核心接腳柵格陣列基體,其中該PGA信號接腳係一第一PGA信號接腳,且更包括一相鄰PGA信號接腳,並且其中該第一PGA信號接腳及該相鄰PGA信號接腳係以一由350μm(中心至中心)至800μm之範圍內的接腳間距來定位。
- 如申請專利範圍第1項之無核心接腳柵格陣列基體,其中該PGA信號接腳係一第一PGA信號接腳,且更包括一相鄰PGA信號接腳,並且其中該第一PGA信號接腳及該相鄰PGA信號接腳係以一由450μm至500μm之範圍內的接腳間距定位。
- 如申請專利範圍第1項之無核心接腳柵格陣列基體,其中該PGA信號接腳具有一在由0.6mm至1.4mm之範圍內的接腳長度。
- 如申請專利範圍第1項之無核心接腳柵格陣列基體,其中該PGA信號接腳具有一1mm之接腳長度。
- 如申請專利範圍第1項之無核心接腳柵格陣列基體,其中該接腳柵格陣列基體具有一在由0.200μm至0.8μm之範圍內的厚度。
- 如申請專利範圍第1項之無核心接腳柵格陣列基體,其 中該接腳柵格陣列基體具有一在由0.400μm至0.7μm之範圍內的厚度。
- 如申請專利範圍第1項之無核心接腳柵格陣列基體,其中該第一間層與該後續間層之間設有1至50個之間的間層,其中該PGA信號接腳具有一在3kg至10kg之範圍內之接腳抗拉強度,其中該PGA信號接腳係一第一PGA信號接腳,且更包括一相鄰PGA信號接腳,並且其中該第一PGA信號接腳及該相鄰PGA信號接腳係以一由350μm(中心至中心)至800μm之範圍內的接腳間距定位,其中該PGA信號接腳係一第一PGA信號接腳,且更包括一相鄰PGA信號接腳,並且其中該第一PGA信號接腳及該相鄰PGA信號接腳係以一由450μm至500μm之範圍內的接腳間距定位,其中該PGA信號接腳具有一在由0.6mm至1.4mm之範圍內的接腳長度,且其中該無核心接腳柵格陣列基體具有一在由0.400μm至0.8μm之範圍內的厚度。
- 一種晶片封裝體,包含:一微電子裝置,其設置在一無核心接腳柵格陣列(PGA)基體之一晶粒側上,其中該無核心PGA基體包括:該晶粒側及一焊墊側;一PGA信號接腳,其設置成與該焊墊側形成一體,其中該PGA信號接腳與設置在一第一間層中之一第一通孔直接接觸,且亦與接觸該第一間層之一第一層線路直接接觸; 一PGA電力-接地接腳,其設置成與該焊墊側形成一體,其中該PGA電力-接地接腳與設置在該第一間層中之一第一通孔直接接觸,且亦與接觸該第一間層之一第一層線路直接接觸;一後續間層,其設置成與該晶粒側相鄰,其中來自該PGA信號接腳與該PGA電力-接地接腳之多數電連接係透過該後續間層耦合;一後續線路,其與該後續間層接觸;多數中間間層,其設置在該第一間層與該後續間層之間;多數信號中間通孔,其將該PGA信號接腳電耦合至該晶粒側;及多數電力-接地中間通孔,其將該PGA電力-接地接腳電耦合至該微電子裝置。
- 如申請專利範圍第12項之晶片封裝體,其中該微電子裝置係安裝在該晶粒側之倒裝晶片。
- 如申請專利範圍第12項之晶片封裝體,其中該微電子裝置係一第一微電子裝置,以及其中該第一微電子裝置係安裝在該晶粒側之倒裝晶片,該晶片封裝體進一步包括設置在該晶粒側並且與該第一微電子裝置相鄰之一後續微電子裝置。
- 如申請專利範圍第12項之晶片封裝體,其中該微電子裝置係一第一微電子裝置,以及其中該第一微電子裝置係安裝在該晶粒側之倒裝晶片,該晶片封裝體進一步包括 堆疊在該第一微電子裝置上之一後續微電子裝置。
- 一種電腦系統,其包含一微電子裝置,其係設置在一無核心接腳柵格陣列(PGA)基體之一晶粒側,其中該無核心PGA基體包括:該晶粒側及一焊墊側;一PGA信號接腳,其設置成與該焊墊側形成一體,其中該PGA信號接腳與設置在一第一間層中之一第一通孔直接接觸,且亦與接觸該第一間層之一第一層線路直接接觸;一PGA電力-接地接腳,其設置成與該焊墊側形成一體,其中該PGA電力-接地接腳與設置在該第一間層中之一第一通孔直接接觸,且亦與接觸該第一間層之一第一層線路直接接觸;一後續間層,其設置成與該晶粒側相鄰,其中來自該PGA信號接腳與該PGA電力-接地接腳之多數電連接係透過該後續間層耦合;一後續線路,其與該後續間層接觸;多數中間間層,其設置在該第一間層與後續間層之間;多數信號中間通孔,其將該PGA信號接腳電耦合至該晶粒側;及多數電力-接地中間通孔,其將該PGA電力-接地接腳電耦合至該微電子裝置;以及一底基體,其支撐該無核心PGA基體。
- 如申請專利範圍第16項之電腦系統,其中該底基體為一行動裝置之一部分。
- 如申請專利範圍第16項之電腦系統,其中該底基體為一刀峰型伺服器之一部份。
- 如申請專利範圍第16項之電腦系統,其中該底基體為一微型伺服器之一部份。
- 如申請專利範圍第16項之電腦系統,其中該底基體為一載具之一部份。
- 如申請專利範圍第19項之電腦系統,其中該底基體為一電視之一部份。
- 一種晶片封裝體,其包含一微電子裝置,其係設置在一無核心接腳柵格陣列(PGA)基體之一晶粒側,其中該無核心PGA基體包括:該晶粒側及一焊墊側;一PGA信號接腳,其設置成與該焊墊側形成一體,其中該PGA信號接腳與設置在一第一間層中之一第一通孔直接接觸,且亦與接觸該第一間層之一第一層線路直接接觸;一PGA電力-接地接腳,其設置成與該焊墊側形成一體,其中該PGA電力-接地接腳與設置在該第一間層中之一第一通孔直接接觸,且亦與接觸該第一間層之一第一層線路直接接觸;一後續間層,其設置成與該晶粒側相鄰,其中來自該PGA信號接腳與該PGA電力-接地接腳之多數電連接 係透過該後續間層耦合;一後續線路,其與該後續間層接觸;多數中間間層,其設置在該第一間層與後續間層之間;多數信號中間通孔,其將該PGA信號接腳電耦合至該晶粒側;多數電力-接地中間通孔,其將該PGA電力-接地接腳電耦合至該微電子裝置;其中該微電子裝置為包括一貫穿矽通孔之一第一微電子裝置,且其中該第一微電子裝置係安裝在該晶粒側之倒裝晶片,該晶片封裝體進一步包括:一後續微電子裝置,其係堆疊在該第一微電子裝置上之倒裝晶片,並耦接於該貫穿矽孔。
- 如申請專利範圍第22項之晶片封裝體,其中該無核心PGA基體包括:多數個電力-接地中間通孔,其將該PGA電力-接地接腳電耦合至該微電子裝置。
- 如申請專利範圍第22項之晶片封裝體,其中該無核心PGA基體包括:多數個電力-接地中間通孔,其將該PGA電力-接地接腳電耦合至該微電子裝置,並進一步包括一底基體,其支撐該無核心PGA基體。
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TW201301465A (zh) | 2013-01-01 |
CN103620766B (zh) | 2016-12-21 |
CN103620766A (zh) | 2014-03-05 |
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DE112012002736T5 (de) | 2014-03-27 |
WO2013003651A2 (en) | 2013-01-03 |
US20130001794A1 (en) | 2013-01-03 |
US8952540B2 (en) | 2015-02-10 |
US9111916B2 (en) | 2015-08-18 |
GB201321494D0 (en) | 2014-01-22 |
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WO2013003651A3 (en) | 2013-03-21 |
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