CN101809738A - 存储器装置介接方法、设备及系统 - Google Patents
存储器装置介接方法、设备及系统 Download PDFInfo
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Abstract
本发明揭示多种设备及系统,其可包括:衬底;接口芯片,其安置于所述衬底上;具有多个存储器阵列的第一存储器裸片,其安置于所述接口芯片上,所述第一存储器裸片耦合到多个贯穿晶片互连件(TWI);以及具有多个存储器阵列的第二存储器裸片,其安置于所述第一存储器裸片上,所述第二存储器裸片包括多个通路,其中所述多个通路经配置以允许所述多个TWI穿过所述第二存储器裸片。所述第二存储器裸片可耦合到第二多个TWI。以此方式,所述接口芯片可用于使用所述第一及第二多个TWI以通信方式耦合所述第一存储器裸片与所述第二存储器裸片。本发明还揭示其它设备、系统及方法。
Description
相关申请案
本专利申请案主张2007年8月29日申请的第11/847,113号美国申请案的优先权权益,所述美国申请案以引用的方式并入本文中。
背景技术
例如个人计算机、工作站、计算机服务器、主机及包括打印机、扫描仪及硬盘驱动机的其它计算机相关设备等许多电子装置使用提供大数据存储能力的存储器装置,同时尝试获得低功率消耗。非常适用于前述装置中的一种类型的存储器装置为动态随机存取存储器(DRAM)。
对较大容量DRAM的需求继续上升且同时芯片大小限制约束着DRAM装置的容量。为了增加DRAM装置的存储器容量,已稳定地减少由个别存储器单元的组件占据的表面面积,使得半导体衬底上的存储器单元的装填密度可增加。缩小装置表面面积可导致制造产量减少,并且增加用于连接DRAM装置内的众多存储器组与其它装置的互连技术的复杂性。
附图说明
下文参看以下图式详细描述本发明的各种实施例。
图1说明根据本发明的各种实施例的存储器系统的框图。
图2A说明根据本发明的一些实施例的存储器系统的透视图。
图2B说明根据本发明的一些实施例的展示于图2A中的存储器系统的横截面图。
图3说明根据本发明的一些实施例的系统的示意性表示。
图4说明根据本发明的一些实施例的展示于图3中的系统的横截面图。
图5说明根据本发明的一些实施例的展示于图3中的系统的操作方法的流程图。
具体实施方式
可通过减小存储器单元组件的水平特征大小来实现存储器的表面面积减小及因此的装填密度增大。这可通过形成实质上是三维的存储器单元组件而在各种实施例中实现,以使得存储器单元组件除大体上延伸越过衬底的表面以外还垂直地延伸进入衬底中且在衬底上方延伸。
图1说明根据本发明的各种实施例的存储器系统100的框图。存储器系统100包括使用128位数据总线50而耦合到存储器装置110、120、130及140的接口芯片150。存储器装置110包括存储器阵列110-1、110-2及110-3,其各自具有以行及列布置的存储器单元。类似地,存储器装置120、130及140分别包括存储器阵列120-1、120-2、120-3;130-1、130-2、130-3;及140-1、140-2、140-3。接口芯片150向存储器装置110到140内的选定存储器地址提供地址及存储器命令。在一些实施例中,存储器装置110到140包括动态随机存取存储器(DRAM)装置。在一些实施例中,存储器装置110到140分别耦合到列解码器112、122、132及142。另外,存储器装置110到140分别耦合到行解码器114、124、134及144。列解码器112、122、132、142及行解码器114、124、134、144响应于使用数据总线50提供的地址命令来存取存储器装置110到140的存储器阵列内的存储器单元。接口芯片150基于在128位数据总线50(其可具有不同于128位的宽度)上提供的信号而控制存储器装置110到140。在一些实施例中,接口芯片150经配置以执行DRAM定序。
在一些实施例中,存储器装置110到140可包含快闪存储器装置。在一些实施例中,在存储器装置110到140中的存储器阵列内的存储器单元可包括以NAND快闪存储器布置来布置的快闪存储器单元。在一些实施例中,在存储器装置110到140中的存储器阵列内的存储器单元可包括以NOR快闪存储器布置来布置的快闪存储器单元。所属领域的技术人员将容易认识到,存储器装置100可包括为了更加清晰地集中于本文描述的各种实施例而从图1省略的其它部分。
向存储器装置110到140提供的存储器命令包括从128位数据总线50向存储器装置110到140内的存储器单元写入数据的编程操作、从存储器装置110到140内的存储器单元读取数据的读取操作及从存储器装置110到140内的所有或部分存储器单元擦除数据的擦除操作。
图2A说明根据本发明的一些实施例的存储器系统200的透视图。可与图1的存储器系统100类似或相同的存储器系统200包括具有焊料球矩阵244的衬底242、接口芯片150、第一存储器阵列202、第二存储器阵列204、第三存储器阵列206及第四存储器阵列208。在一些实施例中,第一存储器阵列202安置于第二存储器阵列204上,且第二存储器阵列204安置于接口芯片150上。在一些实施例中,第三存储器阵列206安置于第四存储器阵列208上,且第四存储器阵列208安置于接口芯片150上。第一存储器阵列202耦合到贯穿晶片互连件(TWI)221,TWI 221又耦合到接口芯片150。在一些实施例中,TWI 221穿过第二存储器阵列204内的一组通路222以与接口芯片150连接。在一些实施例中,TWI 221穿过接口芯片150内的一组通路223以连接到衬底242内的装置。在一些实施例中,第二存储器阵列204使用连接引脚226而耦合到接口芯片150。在一些实施例中,连接引脚230以通信方式耦合存储器阵列208与接口芯片150,且TWI225以通信方式耦合存储器阵列206与接口芯片150。在一些实施例中,连接引脚232允许接口芯片150与嵌入于衬底242内的其它装置之间的通信。在一些实施例中,衬底242可包括具有以通信方式耦合到接口芯片150的电路的电路板。
图2B说明根据本发明的一些实施例的展示于图2A中的存储器系统200的横截面图。存储器系统200包括具有焊料球矩阵244的衬底242、接口芯片150、第一存储器阵列202、第二存储器阵列204、第三存储器阵列206及第四存储器阵列208。在一些实施例中,存储器系统200包括第二存储器阵列204内的通路210、211、212及213,其允许TWI 218、219、220及221穿过第二存储器阵列204且提供第一存储器阵列202与接口芯片150之间的连接。在一些实施例中,TWI 218、219、220及221在相对于包括第二存储器裸片的平面的垂直方向(即,如图2A中展示的z方向)上延伸。在一些实施例中,TWI 218、219、220及221穿过第二存储器裸片以将第一存储器裸片耦合到接口芯片150。在一些实施例中,存储器系统200包括第四存储器阵列208内的通路214、215、216及217,其允许TWI 222、223、224及225穿过第四存储器阵列208且提供第三存储器阵列206与接口芯片150之间的连接。在一些实施例中,连接引脚226、227、228及229提供第二存储器阵列204与接口芯片150之间的通信。在一些实施例中,连接引脚230、231、232及233提供第四存储器阵列208与接口芯片150之间的通信。在一些实施例中,连接引脚232允许接口芯片与嵌入于衬底242内的其它装置之间的通信。在一些实施例中,衬底242可包括具有以通信方式耦合到接口芯片150的电路的电路板。在一些实施例中,衬底242包括集成电路封装。图3展示根据本发明的实施例的系统300的示意图。系统300包括处理单元360、接口芯片150以及存储器裸片310及320。接口芯片150包括多路复用器/多路分用器电路350、DRAM控制器330及快闪控制器340。在一些实施例中,存储器裸片310包括DRAM阵列310-1、310-2、310-3及310-4。在一些实施例中,存储器裸片320包括快闪阵列320-1、320-2、320-3及320-4。在一些实施例中,DRAM控制器330使用TWI 335而耦合到DRAM阵列310-1、310-2、310-3及310-4中的每一者。在一些实施例中,快闪控制器340使用TWI 345而耦合到快闪阵列320-1、320-2、320-3及320-4中的每一者。贯穿晶片互连件335及345穿过在存储器裸片310及320内在z方向(垂直)上延伸的通路。
在一些实施例中,接口芯片150经配置以基于存储器裸片320中所使用的DRAM的类型而操作刷新方案来控制错误率。在一些实施例中,接口芯片150经配置以基于存储器裸片310及320的信号特性而操作刷新方案来控制错误率。在一些实施例中,接口芯片150经配置以对存储器裸片320内所包括的多个存储器阵列操作不良单元恢复方案。在一些实施例中,接口芯片150是可编程的且经配置以基于安置于其之上的存储器裸片的类型而进行操作。在一些实施例中,接口芯片150经配置以对多个存储器阵列202、204、206及208操作不良单元恢复方案。在一些实施例中,接口芯片150包括模式产生器,其经配置以产生用于存储器裸片320的测试及诊断分析的测试模式信号。
系统300还可包括例如电路板等衬底242(参见图2A),系统300的一些组件可位于所述衬底242上。衬底242可包括耦合到电源(未图示)的端子244,以向包括存储器装置310及320的系统300的组件提供功率或电压。电源可提供交流到直流(AC到DC)转换电路、电池及其它。存储器装置110到140可包含易失性存储器装置、非易失性存储器装置或两者的组合。举例来说,存储器装置110可包含DRAM装置、静态随机存取存储器(SRAM)装置、快闪存储器装置或这些存储器装置的组合。在一些实施例中,接口芯片150可包括用于有线或无线通信的通信模块。在一些实施例中,系统300的组件的数目可有所不同。
处理单元360处理经由总线50传送到其它组件及从其它组件传送的数据。处理单元360可包括通用处理器或专用集成电路(ASIC)。处理单元360可包含单核心处理单元或多核心处理单元。
在一些实施例中,存储器装置310及320可包括上文中参看图1、图2A及图2B描述的存储器装置的一个或一个以上实施例。
在一些实施例中,系统300的操作方法包括在处理器360与接口芯片150之间发送及接收数据,所述接口芯片150包括多路复用器/多路分用器350及存储器控制器330、340。所述方法还可包括使用贯穿晶片互连件335、345从接口芯片150向若干个存储器裸片310、320发送及接收以上数据,其中贯穿晶片互连件335、345穿过在存储器裸片310、320内在z方向上形成的通路。所述方法还包括将以上数据存储于存储器裸片310、320中,其中存储器裸片310、320中的每一者分别包括若干个存储器阵列310-1、310-2、310-3及320-1、320-2、320-3。在一些实施例中,所述方法包括将数据存储于DRAM阵列310中。在一些实施例中,所述方法包括将数据存储于NAND快闪阵列320中。在一些实施例中,所述方法包括将数据存储于NOR快闪阵列320中。
系统300可包括于计算机(例如,桌上型计算机、膝上型计算机、手持式装置、服务器、Web器具、路由器,等等)、无线通信装置(例如,蜂窝式电话、无绳电话、寻呼机、个人数字助理,等等)、计算机相关外围设备(例如,打印机、扫描仪、监视器,等等)、娱乐装置(例如,电视、无线电、立体声、磁带播放机、压缩光盘播放机、DVD播放机、磁带录像机、DVD录像机、可携式摄影机、数码相机、MP3(运动图片专家小组音频层3)播放机、视频游戏、手表,等等)及其类似物中。
图4说明根据本发明的一些实施例的与图3中展示的系统类似的系统400的横截面图。系统400包括具有嵌入于衬底402内的接口芯片150的衬底(其还可称为封装)402、使用焊料球矩阵408附接到衬底402的处理器406、包括具有TWI 412-1、412-2(其连接存储器阵列410-1、410-2、410-3与接口芯片150)的存储器阵列410-1、410-2、410-3的存储器装置410。在一些实施例中,接口芯片150安置于处理器406上,且存储器装置410安置于接口芯片150上。在一些实施例中,封装402可包括电路板403,且接口芯片150安置于电路板403上,且存储器装置410安置于接口芯片150上。
在一些实施例中,衬底402附接到焊料球矩阵404,所述焊料球矩阵404使系统400能够安装于具有其它装置的电路板上。在一些实施例中,存储器装置410附接到焊料球矩阵414,所述焊料球矩阵414用于将存储器装置410以通信方式耦合到衬底402。
在一些实施例中,接口芯片150充当互连装置及I/O驱动器。在一些实施例中,接口芯片150包括存在于DRAM裸片内的传统功能块,例如I/O衬垫、延迟锁定回路(DLL)电路及提供读取及写入指针、存储及控制逻辑的先进先出(FIFO)电路。将所属领域的技术人员众所周知的这些功能块从DRAM裸片转移到接口芯片150中可允许DRAM裸片的存储面积增大。
在一些实施例中,接口芯片150耦合到具有例如图4中展示的TWI等独立互连件的32个不同存储器组(各自具有若干存储器阵列;其它数目的存储器组是可能的)。在一些实施例中,接口芯片150耦合到一组TWI,所述TWI经配置以基于最终用户应用而提供不同类型的互连。在一些实施例中,TWI可经配置以提供独立DRAM裸片群组与接口芯片150之间的连接性。
在一些实施例中,接口芯片150经配置以在接口芯片150与DRAM裸片之间发射及接收测试模式信号以计算用于每一互连件的最佳时序水平。在一些实施例中,接口芯片150可具有提供外部系统互连的任何数目(例如,8、16、32、64、128,等)的I/O衬垫。在一些实施例中,在接口芯片150与DRAM裸片的I/O端子之间发射及接收测试模式信号,且执行训练算法以计算用于每一输入/输出连接的最佳时序。
在一些实施例中,接口芯片150经配置以在系统400内执行功率管理,其中接口芯片150在足以防止在接口芯片150与存储器装置410之间的通信中产生错误位的电压下进行操作。
在一些实施例中,接口芯片150经配置以在存储器装置410与安置于衬底402上的处理器406之间的数据通信期间执行错误检测及/或校正。在一些实施例中,接口芯片150经配置以通过在预先确定以使得在此电压下不产生错误位的某个电压下进行操作而执行系统400的功率管理。
在一些实施例中,接口芯片150包括诊断及内建式自测试(BIST)模块152。在一些实施例中,BIST模块耦合到耦合于接口芯片150与存储器装置410之间的维护总线154。在一些实施例中,BIST模块经配置以经由维护总线154将从用户接收的命令信号及数据发送到存储器装置410。在一些实施例中,还使用维护总线154来接收诊断测试的结果。在一些实施例中,诊断及BIST模块152产生控制信号且转发用户供应的命令及数据信号以执行用户的命令。举例来说,诊断及BIST模块152可调用模式产生器程序或硬件模块以开始根据用户命令及数据产生测试模式,且还将用户提供的存储器命令转发到定序器156供转译为控制信号,控制信号将被施加到存储器装置410以用于执行存储器装置410的诊断操作。
图5说明根据本发明的一些实施例的展示于图3中的系统的操作方法500的流程图。在502处,方法500包括在处理器与接口芯片之间发送及接收数据,所述接口芯片包括多路复用器、多路分用器及存储器控制器。在504处,方法500包括使用多个贯穿晶片互连件(TWI)从接口芯片向多个存储器裸片发送及接收数据,所述多个TWI穿过形成于存储器裸片中的多个通路。在506处,方法500包括将数据存储于多个存储器裸片中,其中多个存储器裸片中的每一者包括多个存储器阵列。在一些实施例中,在506处,方法包括将数据存储于DRAM阵列中。在一些实施例中,在506处,方法包括将数据存储于NAND快闪阵列中。在一些实施例中,在506处,方法包括将数据存储于NOR快闪阵列中。
本文揭示的设备、系统及方法除了与常规设计相比实现较高的存储器阵列密度以外还可在存取存储器阵列时提供增加的速度及处理量。在一些实施例中,因而还减小了DRAM裸片大小。另外,贯穿晶片互连件的使用允许较大数目的互连件横越较短距离,且因此改进由互连件建立的每一连接的速度。此外,本文揭示的设备、系统及方法提供耦合到存储器阵列的能够在具有改进的装填密度的设计中以减少的等待时间处理较多带宽的处理器。
形成本文的一部分的附图借助于说明而非限制展示其中可实践标的物的特定实施例。充分详细地描述所说明的实施例以使所属领域的技术人员能够实践本文揭示的教示。可使用其它实施例且从其中导出其它实施例,使得可在不脱离本发明的范围的情况下作出结构及逻辑上的替代及改变。因此,此具体实施方式不应在限制性意义上加以理解,且各种实施例的范围仅由随附权利要求书及所述权利要求书所具有的等效物的完整范围界定。
发明性标的物的此些实施例可在本文中由术语“发明”个别地或共同地提及,这仅为了方便且不希望自发地将本申请案的范围限于任何单个发明或发明性概念(如果实际上揭示了一个以上发明或发明性概念的话)。因此,尽管本文已说明且描述了特定实施例,但经计划以实现相同目的的任何布置可用以替换所展示的特定实施例。本揭示内容既定涵盖各种实施例的任何及所有改编或变化。所属领域的技术人员在审阅以上描述后将容易明白上述实施例与本文未具体描述的其它实施例的组合。
提供说明书摘要以遵守37C.F.R.§1.72(b),其需要将允许读者迅速确定技术性揭示内容的性质的摘要。在不将其用于解释或限制权利要求书的范围或意义的理解下提交所述摘要。在前述具体实施方式中,为了简化揭示内容的目的,在单个实施例中将各种特征分组在一起。本发明的方法不应解释为需要比每一权利要求项中所明确叙述多的特征。相反,发明性标的物可具备比单个所揭示实施例的所有特征少的特征。因此,所附权利要求书特此并入到具体实施方式中,其中每一权利要求项独自为单独的实施例。
结论
方法、设备及系统已揭示了增大给定水平空间内的存储器容量的存储器装置连接方案。各种实施例包括衬底、安置于衬底上接口芯片、安置于接口芯片上的具有多个存储器阵列的第一存储器裸片,其中第一存储器裸片耦合到多个贯穿晶片互连件(TWI)。各种实施例包括安置于第一存储器裸片上的具有多个存储器阵列的第二存储器裸片,第二存储器裸片包括多个通路,其中多个通路经配置以允许多个TWI穿过第二存储器裸片。第二存储器裸片又可耦合到第二多个TWI,且接口芯片可用于使用第一及第二多个TWI以通信方式耦合第一存储器裸片与第二存储器裸片。
一个或一个以上实施例提供用于互连存储器装置的改进的机制。此外,本文描述的各种实施例可改进存储器装置内的一些存储器阵列的密度,且因此减小存储器装置的大小。
Claims (33)
1.一种设备,其包含:
衬底;
接口芯片,其安置于所述衬底上;
具有至少一个存储器阵列的第一存储器裸片,其安置于所述接口芯片上,所述第一存储器裸片耦合到多个贯穿晶片互连件(TWI);及
具有至少一个存储器阵列的第二存储器裸片,其安置于所述第一存储器裸片上,所述第二存储器裸片包括多个通路,其中所述多个通路经配置以允许所述多个TWI穿过所述第二存储器裸片,所述第二存储器裸片耦合到第二多个TWI,其中所述接口芯片使用所述第一及第二多个TWI以通信方式耦合所述第一存储器裸片与所述第二存储器裸片。
2.根据权利要求1所述的设备,其中所述接口芯片经配置以提供地址及命令数据以存取所述第一及第二存储器裸片内的存储器单元。
3.根据权利要求1所述的设备,其中所述至少一个存储器阵列包括DRAM阵列。
4.根据权利要求3所述的设备,其中所述接口芯片经配置以执行所述DRAM阵列的定序。
5.根据权利要求1所述的设备,其中所述接口芯片经配置以执行所述设备的功率管理,且其中所述接口芯片在足以排除错误位产生的电压下进行操作。
6.根据权利要求1所述的设备,其中所述接口芯片包含:
输入/输出驱动器电路。
7.根据权利要求3所述的设备,其中所述接口芯片经配置以基于所述第一及第二存储器裸片中所使用的DRAM阵列的类型而操作刷新方案来控制错误率。
8.根据权利要求1所述的设备,其中所述接口芯片经配置以基于所述第一及第二存储器裸片的信号特性而操作刷新方案来控制错误率。
9.根据权利要求1所述的设备,其中所述接口芯片是可编程的且经配置以基于放置于其之上的所述第一及第二存储器裸片的类型而进行操作。
10.根据权利要求1所述的设备,其中所述接口芯片经配置以相对于所述至少一个存储器阵列操作不良单元恢复方案。
11.根据权利要求2所述的设备,其中所述接口芯片经配置以在所述第一及第二存储器裸片与安置于所述衬底上的处理器之间的数据通信期间执行错误检查及校正(ECC)。
12.根据权利要求1所述的设备,所述接口芯片进一步包含:
诊断模块及内建式自测试(BIST)模块。
13.根据权利要求3所述的设备,所述接口芯片进一步包含:
模式产生器,其经配置以产生用于所述设备的测试及诊断分析的测试模式信号。
14.根据权利要求13所述的设备,其中所述测试模式信号在所述接口芯片与所述DRAM阵列的I/O端子之间发射及接收,且训练算法经执行以计算用于每一输入/输出连接的最佳时序。
15.根据权利要求1所述的设备,其中所述至少一个存储器阵列包含NAND快闪存储器阵列。
16.根据权利要求1所述的设备,其中所述至少一个存储器阵列包含NOR快闪存储器阵列。
17.根据权利要求1所述的设备,其中所述第一及第二多个TWI在相对于包括所述第二存储器裸片的平面的垂直方向上延伸穿过所述第二存储器裸片,以将所述第一存储器裸片耦合到所述接口芯片。
18.根据权利要求11所述的设备,其中所述接口芯片安置于所述处理器上,且所述处理器包含安置于所述衬底上的多核心处理器。
19.根据权利要求1所述的设备,其中所述第一及第二TWI形成数据总线的至少一部分,所述数据总线耦合所述第一及第二存储器裸片中的所述存储器阵列与所述接口芯片。
20.根据权利要求1所述的设备,其中所述第一及第二存储器裸片中的所述多个存储器阵列包括列解码器及行解码器。
21.根据权利要求1所述的设备,其进一步包含连接引脚以耦合所述第二存储器裸片与所述接口芯片。
22.一种系统,其包含:
第一存储器裸片,其具有多个存储器阵列,所述第一存储器裸片耦合到第一多个贯穿晶片互连件(TWI);
第二存储器裸片,其使所述第一存储器裸片安置于所述第二存储器裸片上方且具有多个存储器阵列,所述第二存储器裸片耦合到第二多个TWI,所述第二存储器裸片包括多个通路,所述多个通路经配置以允许所述第一多个TWI穿过所述第二存储器裸片;
接口芯片,其使用所述第一及第二多个TWI而耦合到所述第一存储器裸片及所述第二存储器裸片,所述第一及第二存储器裸片安置于所述接口芯片上;及
处理单元,其以通信方式耦合到所述接口芯片、所述第一存储器裸片及所述第二存储器裸片。
23.根据权利要求22所述的系统,其中所述多个存储器阵列包括DRAM阵列。
24.根据权利要求22所述的系统,其中所述多个存储器阵列包括NAND快闪存储器阵列。
25.根据权利要求22所述的系统,其中所述多个存储器阵列包括NOR快闪存储器阵列。
26.根据权利要求22所述的系统,其中所述接口芯片进一步包含多路复用器/多路分用器电路及存储器控制器。
27.根据权利要求26所述的系统,其中所述存储器控制器经配置以控制DRAM存储器阵列。
28.根据权利要求26所述的系统,其中所述存储器控制器经配置以控制快闪存储器阵列。
29.根据权利要求26所述的系统,进一步其中所述处理器耦合到所述多路复用器/多路分用器电路。
30.根据权利要求22所述的系统,其中所述接口芯片进一步包含通信模块以提供有线及无线通信中的至少一者。
31.根据权利要求22所述的系统,其中所述接口芯片嵌入于所述衬底内。
32.一种方法,其包含:
在处理单元与接口芯片之间进行数据发送及接收中的至少一者,所述接口芯片包括多路复用器及多路分用器电路中的至少一者及存储器控制器;
使用多个贯穿晶片互连件(TWI)从所述接口芯片向多个存储器裸片进行所述数据发送及接收中的至少一者;所述多个TWI穿过形成于所述存储器裸片中的多个通路;及
将所述数据存储于所述多个存储器裸片中,其中所述多个存储器裸片中的每一者包括至少一个存储器阵列。
33.根据权利要求32所述的方法,其中将所述数据存储于所述多个存储器裸片中包含:
将所述数据存储于DRAM阵列中。
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US11/847,113 US7623365B2 (en) | 2007-08-29 | 2007-08-29 | Memory device interface methods, apparatus, and systems |
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KR (3) | KR101382985B1 (zh) |
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2007
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- 2008-08-28 JP JP2010522950A patent/JP5354390B2/ja active Active
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- 2008-08-28 CN CN2008801087255A patent/CN101809738B/zh active Active
- 2008-08-28 KR KR1020147018063A patent/KR101460955B1/ko active IP Right Grant
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Cited By (9)
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US8593849B2 (en) | 2007-08-29 | 2013-11-26 | Micron Technology, Inc. | Memory device interface methods, apparatus, and systems |
US10468382B2 (en) | 2008-09-11 | 2019-11-05 | Micron Technology, Inc. | Signal delivery in stacked device |
US11264360B2 (en) | 2008-09-11 | 2022-03-01 | Micron Technology, Inc. | Signal delivery in stacked device |
CN102148761A (zh) * | 2011-04-11 | 2011-08-10 | 北京星网锐捷网络技术有限公司 | 通信接口芯片、通讯设备及通信接口节能的实现方法 |
CN102148761B (zh) * | 2011-04-11 | 2013-11-20 | 北京星网锐捷网络技术有限公司 | 通信接口芯片、通讯设备及通信接口节能的实现方法 |
CN103839938A (zh) * | 2012-11-20 | 2014-06-04 | 辉达公司 | 服务器处理模块 |
CN112992217A (zh) * | 2015-04-08 | 2021-06-18 | 三星电子株式会社 | 在多芯片封装中使用温度偏差来控制操作的存储器器件 |
CN110289030A (zh) * | 2018-03-19 | 2019-09-27 | 美光科技公司 | 具有可配置输入/输出接口的存储器装置 |
CN110289030B (zh) * | 2018-03-19 | 2023-08-08 | 美光科技公司 | 具有可配置输入/输出接口的存储器装置 |
Also Published As
Publication number | Publication date |
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WO2009032153A3 (en) | 2009-07-09 |
JP5354390B2 (ja) | 2013-11-27 |
US20090059641A1 (en) | 2009-03-05 |
US20120218803A1 (en) | 2012-08-30 |
KR101382985B1 (ko) | 2014-04-08 |
TWI470740B (zh) | 2015-01-21 |
US9001548B2 (en) | 2015-04-07 |
TW200921852A (en) | 2009-05-16 |
EP2195841A2 (en) | 2010-06-16 |
JP5643884B2 (ja) | 2014-12-17 |
US20140063942A1 (en) | 2014-03-06 |
US8339827B2 (en) | 2012-12-25 |
US7623365B2 (en) | 2009-11-24 |
US20130083585A1 (en) | 2013-04-04 |
KR101460955B1 (ko) | 2014-11-13 |
JP2013242922A (ja) | 2013-12-05 |
WO2009032153A2 (en) | 2009-03-12 |
JP2010538358A (ja) | 2010-12-09 |
KR101460936B1 (ko) | 2014-11-12 |
US8593849B2 (en) | 2013-11-26 |
KR20140100554A (ko) | 2014-08-14 |
KR20140018383A (ko) | 2014-02-12 |
CN101809738B (zh) | 2012-07-04 |
US8174859B2 (en) | 2012-05-08 |
US20100061134A1 (en) | 2010-03-11 |
KR20100058605A (ko) | 2010-06-03 |
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