CN101802993B - 半导体装置及引线接合方法 - Google Patents

半导体装置及引线接合方法 Download PDF

Info

Publication number
CN101802993B
CN101802993B CN2008801082514A CN200880108251A CN101802993B CN 101802993 B CN101802993 B CN 101802993B CN 2008801082514 A CN2008801082514 A CN 2008801082514A CN 200880108251 A CN200880108251 A CN 200880108251A CN 101802993 B CN101802993 B CN 101802993B
Authority
CN
China
Prior art keywords
lead
wire
pad
capillary
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2008801082514A
Other languages
English (en)
Other versions
CN101802993A (zh
Inventor
三井竜成
木内逸人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinkawa Ltd
Arakawa Co Ltd
Original Assignee
Arakawa Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Arakawa Co Ltd filed Critical Arakawa Co Ltd
Publication of CN101802993A publication Critical patent/CN101802993A/zh
Application granted granted Critical
Publication of CN101802993B publication Critical patent/CN101802993B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4846—Connecting portions with multiple bonds on the same bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4941—Connecting portions the connecting portions being stacked
    • H01L2224/49425—Wedge bonds
    • H01L2224/49426—Wedge bonds on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4941—Connecting portions the connecting portions being stacked
    • H01L2224/49429—Wedge and ball bonds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H01L2224/85051—Forming additional members, e.g. for "wedge-on-ball", "ball-on-wedge", "ball-on-ball" connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518—Translational movements
    • H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/859—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving monitoring, e.g. feedback loop
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/85951—Forming additional members, e.g. for reinforcing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

本发明涉及半导体装置及引线接合方法。在半导体装置中，包括第一层挤压部(100)，第一引线(25)，以及第二引线(26)。第一层挤压部(100)系将初始球焊接在第一层半导体芯片(11)的第一层焊接点(14)上，形成球颈，压碎该球颈，引线折返在该压碎球颈上，使得该引线侧面挤压在上述压碎的球颈上形成。第一引线(25)从第一层挤压部(100)向着引脚(16)方向延伸。第二引线(26)从第二层半导体芯片(12)的第二层焊接点(15)向着第一层挤压部(100)成环，与第一层挤压部(100)的第二层焊接点(15)侧接合。这样，一边减少给与半导体芯片的损伤，一边以少的接合次数进行引线连接。

Description

半导体装置及引线接合方法
技术领域
本发明涉及半导体装置的结构及引线接合(wire bonding)方法。
背景技术
近年，根据半导体装置的大容量化的要求，大多使用将多个半导体芯片叠层在引脚框上构成的叠层型半导体装置。又，在这种叠层型半导体装置中，同时要求薄型化，小型化，因此，例如日本专利第3573133号说明书记载，并不是各层的半导体芯片的焊接点(pad)和引脚框分别连接，而是使用通过引线顺序连接邻接的各半导体芯片的焊接点之间或半导体芯片的焊接点和引脚框的引脚之间的引线接合方法，在该方法中，为了使得当引线接合时不给与半导体芯片损伤，采用以下方法：首先，在各半导体芯片的焊接点上形成凸出部(bump)，此后，从引脚框的引脚向着半导体芯片的焊接点上进行逆接合，再从被接合的凸出部向着邻接的半导体芯片的凸出部上进行下次逆接合，从引脚框向着最上层的半导体芯片的凸出部，顺序连接引线。
另外，例如日本专利第3869562号说明书所记载那样，提出以下连接引线方法：仅仅在叠层型半导体装置的位于中间层的焊接点面上，形成用于减少接合时对半导体芯片损伤的凸出部，在最上层的半导体芯片的凸出部进行接合，使得引线在中间层的焊接点上形成的凸出部上形成环，接合在凸出部上，此后，再使得引线连续成环，在邻接的中间层的焊接点上或引脚上，进行断续接合，但是，日本专利第3573133号说明书记载的以往技术系在各半导体芯片的焊接点形成凸出部后，进行引线接合，因此，工序多，接合存在化费时间、成本贵的问题。例如，叠层为二层的叠层型半导体的各焊接点和引脚的连接，需要在二层的各半导体芯片的焊接点上形成各自的凸出部的工序(二个工序)，引脚和第一层的半导体芯片的焊接点上的凸出部之间的接合，以及第一层的凸出部和第二层的半导体芯片的焊接点上的凸出部之间的接合，共计四个工序。又，在日本专利第3869562号说明书所记载的以往技术中，仅仅在位于中间层的半导体芯片的焊接点上形成凸出部后，进行接合，因此，工序数比日本专利第3573133号说明书记载的以往技术少，但是，除了接合工序，需要另外设置凸出部形成工序，没有解决工序数多的问题。
发明内容
本发明的目的在于，在半导体装置中，一边减少给与半导体芯片的损伤，一边以少的接合次数进行引线连接。
本发明的半导体装置系通过各引线连接至少三个焊接点之中、各两个焊接点之间，其特征在于，包括：
挤压部，将插入穿通毛细管从其下端突出的引线前端形成的初始球焊接在第一焊接点上，形成球颈，压碎该球颈，挤压在上述压碎球颈上折返的引线的侧面形成；
第一引线，从挤压部向第二焊接点延伸；
各第二引线，至少一个第三焊接点位于与从第一焊接点向着第二焊接点方向不同的方向，从该第三焊接点向着挤压部成环，与挤压部的各第三焊接点侧接合。
本发明的半导体装置系在引脚框上叠层半导体芯片，通过各引线顺序连接邻接的各半导体芯片的焊接点之间，或半导体芯片的焊接点和引脚框的引脚之间，其特征在于，包括：
挤压部，将插入穿通毛细管从其下端突出的引线前端形成的初始球焊接在第一半导体芯片的焊接点上，形成球颈，压碎该球颈，挤压在上述压碎球颈上折返的引线的侧面形成；
第一引线，从挤压部向引脚或与引脚框侧邻接的第二半导体芯片的焊接点的方向延伸；
第二引线，第三半导体芯片与第一半导体芯片的引脚框侧的相反侧邻接，从该第三半导体芯片的焊接点向着挤压部成环，与挤压部的第三半导体芯片的焊接点侧接合。
在本发明的半导体装置中，较好的是，第二引线通过毛细管下降用毛细管的面部与挤压部接合，同时，因毛细管的挤压力变形，被夹入进入毛细管中心孔的凸部和毛细管的内倒角部之间被压缩。又，在本发明的半导体装置中，合适的是，因毛细管的挤压力，凸部变形为沿毛细管的中心孔的形状，第二引线沿上述凸部具有切断面。
本发明的引线接合方法系通过各引线连接至少三个焊接点之中、各两个焊接点之间，其特征在于，包括：
球焊工序，将插入穿通毛细管从其下端突出的引线前端形成的初始球焊接在焊接点上；
压碎工序，用毛细管前端压碎由上述球焊工序形成的球颈；
挤压工序，将引线折返在由毛细管压碎的球颈上，使得该引线侧面挤压在上述压碎的球颈上；
第一引线形成工序，通过毛细管输出引线后，向着第二焊接点成环，形成向着第二焊接点的第一引线；
第二引线接合工序，至少一个第三焊接点位于与从第一焊接点向着第二焊接点方向不同的方向，从该第三焊接点向着挤压部成环，使得各第二引线与挤压部的各第三焊接点侧接合。
本发明的引线接合方法系在引脚框上叠层半导体芯片，通过各引线顺序连接邻接的各半导体芯片的焊接点之间，或半导体芯片的焊接点和引脚框的引脚之间，其特征在于，包括：
球焊工序，将插入穿通毛细管从其下端突出的引线前端形成的初始球焊接在第一半导体芯片的焊接点上；
压碎工序，用毛细管前端压碎由上述球焊工序形成的球颈；
挤压工序，将引线折返在由毛细管压碎的球颈上，使得该引线侧面挤压在上述压碎的球颈上；
第一引线形成工序，通过毛细管输出引线后，通过向着引脚或与引脚框邻接的第二半导体芯片的焊接点方向成环，形成向着引脚或第二半导体芯片的焊接点的方向的第一引线；
第二引线连接工序，第三半导体芯片与第一半导体芯片的引脚框侧的相反侧邻接，从该第三半导体芯片的焊接点向着挤压部成环，使得第二引线与挤压部的第三半导体芯片的焊接点侧接合。
在本发明的引线焊接方法中，合适的是，在第二引线连接工序中，使得毛细管下降，通过毛细管的面部使得第二引线与挤压部接合，同时，用毛细管的挤压力，使得外径比毛细管中心孔内径大的挤压部变形为进入毛细管中心孔的凸部，将第二引线夹入进入毛细管中心孔的凸部和毛细管的内倒角部之间被压缩。
本发明具有在半导体装置中能一边减少给与半导体芯片的损伤一边以少的接合次数进行引线连接的效果。
附图说明
图1是表示本发明实施形态的半导体装置的侧面图。
图2是表示本发明实施形态的半导体装置的挤压部、从挤压部延伸的第一引线、以及焊接在挤压部的第二引线的立体图。
图3是表示本发明实施形态的半导体装置的挤压部、从挤压部延伸的第一引线、以及焊接在挤压部的第二引线的立体图。
图4是表示本发明实施形态的半导体装置的球焊的说明图。
图5是表示本发明实施形态的半导体装置的接合工序之中，压碎工序和挤压工序的说明图。
图6是表示本发明实施形态的半导体装置的接合工序之中引线输出的说明图。
图7是表示本发明实施形态的半导体装置的接合工序之中引线输出的说明图。
图8是表示本发明实施形态的半导体装置的接合工序之中引线向引脚成环的说明图。
图9是表示本发明实施形态的半导体装置的接合工序之中向引脚的焊接的说明图。
图10是表示本发明实施形态的半导体装置的球焊的说明图。
图11是表示本发明实施形态的半导体装置的接合工序之中引线输出的说明图。
图12是表示本发明实施形态的半导体装置的接合工序之中引线输出的说明图。
图13是表示本发明实施形态的半导体装置的接合工序之中引线向挤压部成环的说明图。
图14是表示本发明实施形态的半导体装置的接合工序之中向挤压部焊接的说明图。
图15是表示本发明实施形态的半导体装置的接合工序之中向挤压部焊接的说明图。
图16是表示本发明实施形态的半导体装置的接合工序之中向挤压部焊接的说明图。
图17是表示本发明实施形态的半导体装置的接合工序之中切断引线动作的说明图。
图18是表示本发明实施形态的三层叠层半导体装置的接合工序之中第一层和第二层的焊接的说明图。
图19是表示本发明实施形态的三层叠层半导体装置的接合工序之中第二层和第三层的焊接的说明图。
图20是表示本发明另一实施形态的半导体装置的立体图。
图21是表示本发明另一实施形态的半导体装置的挤压部、从挤压部延伸的第一引线、以及焊接在挤压部的多条第二引线的立体图。
具体实施方式
下面边参照附图边说明本发明的较佳实施形态。图1表示将本发明适用于叠层型半导体装置10场合的实施形态。如图1所示，半导体装置10成为在引脚框13上叠层接合作为第一半导体芯片的第一层半导体芯片11，和尺寸大小比第一层半导体芯片11小的、作为第三半导体芯片的第二层半导体芯片12的二层叠层结构。第一层半导体芯片11在表面设有作为第一接合点的第一层焊接点14，第二层半导体芯片12在表面设有作为第三接合点的第二层焊接点15，引脚框13在表面设有作为第二接合点的引脚16。
在设在各半导体芯片11、12表面的各焊接点14、15之间，具有相当于第二层半导体芯片12厚度的阶梯差，在第一层半导体芯片11和引脚16之间，具有相当于第一层半导体芯片11厚度的阶梯差。又，第二层半导体芯片12比第一层半导体芯片11小，因此，各焊接点14、15和引脚16在沿各焊接点14、15或引脚16的面中，从第二层焊接点15向着引脚16，以第二层焊接点15、第一层焊接点14、引脚16顺序配置，又，各焊接点14、15和引脚16在各半导体芯片11、12的厚度方向，也从第二层焊接点15向着引脚16，以第二层焊接点15、第一层焊接点14、引脚16顺序配置。即，各焊接点14、15和引脚16从第二层焊接点15向着引脚16，配置成阶梯状。并且，作为第三接合点的第二层焊接点15，配置在与从作为第一接合点的第一层焊接点14向着作为第二接合点的引脚16方向不同的方向。
在第一层焊接点14上设有第一层挤压部100。第一层挤压部100包括通过球焊形成的压焊球17，压碎部(压塌部)21，以及变形折返部19。压碎(压塌)球焊时形成的球颈，形成所述压碎部21，在其上使得引线折返形成后，因第二引线的焊接，发生变形，形成变形折返部19。第一引线25从第一层挤压部100向着引脚16方向延伸。第一引线25从第一层挤压部100到第一弯折(kink)部37在沿焊接点14表面的面沿水平延伸，在第一弯折部37朝第一层半导体芯片11的厚度方向折曲，在接合面36与引脚16接合。
在第二层焊接点15上设有第二层挤压部200。第二层挤压部200包括通过球焊形成的压焊球18，压碎部22，以及折返部20。压碎球焊时形成的球颈，形成所述压碎部22，在其上使得引线折返形成所述折返部20。第二引线26从第二层挤压部200向着第一层焊接点14方向延伸。第二引线26从第二层挤压部200到第二弯折部39在沿焊接点15表面的面沿水平延伸，在第二弯折部39朝第二层半导体芯片12的厚度方向折曲，在接合面29与第一层挤压部100接合。所述接合面29位于第一层挤压部100的第二层焊接点15侧的变形折返部19上。
这样，第一层焊接点14和引脚16之间，以及第一层焊接点14和第二层焊接点15之间，分别由第一引线25及第二引线26顺序连接。又，第一层挤压部100、第二层挤压部200、第一引线、第二引线全部由金引线形成。
如图2、图3所示，第一层挤压部100在中央具有凸部23，当焊接第二引线26时，因毛细管的挤压力形成该凸部23。凸部23在第一引线25侧具有形成朝向上侧直径变小的圆锥体形状的锥面24b，以及与锥面24b连续、朝上方延伸的圆筒面24d，而在第二引线26侧具有形成朝向上侧直径变小的圆锥体形状的锥面24a，以及与锥面24a连续、朝上方延伸的圆筒面24c。又，与凸部23连续，在第一引线25上面，具有因毛细管前端的平面部挤压形成的平面部27，在第二引线26上面，具有因毛细管前端的平面部挤压形成的平面部28。
如图2所示，形成在第一层焊接点14上的压焊球17为圆板形状。如图3所示，在压焊球17的第一引线25侧上形成压碎部21，在与第一引线25相反侧上形成变形折返部19。又，凸部23的沿第一引线25方向的侧面50与第一引线25侧面相同，大致呈圆筒状。在凸部23和压碎部21之间，具有微小间隙55，其是折返引线形成第一层挤压部100时产生的。
如图3所示，在凸部23的根部，沿着锥面24a形成第二引线26的切断面31。
下面，边参照图4-图17，边说明半导体装置10的第一层焊接点14和引脚16之间以及第一层焊接点14和第二层焊接点15之间的焊接方法。
如图4所示，在从毛细管41下端突出的第一引线25的前端，通过放电或焊枪等形成初始球33。接着，使得毛细管41下降，使得初始球33压焊在第一层焊接点14上，实行如图5(a)所示那样的形成圆板状的压焊球17和球颈51的球焊工序。
如图5(a)-5(c)所示，通过球焊工序形成压焊球17以及球颈51后，开始通过毛细管41挤压球颈51的挤压工序。在挤压工序中，如图5(a)所示，输出与球颈51连续的引线52，同时，使得毛细管41上升后，如图5(b)所示，毛细管41的引脚16侧的面部44来到球颈51的上部，使得毛细管41朝与引脚16相反方向移动。此时，引线52成为从球颈51朝与引脚16相反方向倾斜的状态。接着，如图5(c)所示，使得毛细管41下降，用毛细管41的面部44压碎球颈51，在压焊球17上形成压碎部21。压碎部21的上面由毛细管41的面部44压碎，因此，成为沿面部44形状的平面状。又，引线52朝着压碎部21的与引脚16相反侧折曲，同时，成为沿毛细管41的直孔42的与引脚16相反侧的内面，朝第一焊接点14的垂直方向延伸的状态。这样，若通过毛细管41挤压球颈51，则挤压工序结束。
然后，如图5(d)-5(f)所示，开始挤压工序。在挤压工序中，如图5(d)所示，再次输出引线52，同时，使得毛细管41上升。于是，引线52沿毛细管41的直孔42按直线输出。接着，如图5(e)所示，使得毛细管41朝引脚16方向移动。于是，通过毛细管41的内倒角部43，引线52朝着引脚16方向被推压，在与挤压部21连续的弯曲部53被折曲。接着，在毛细管41的位于与引脚16相反侧的面部44来到压焊球17上位置之前，使得毛细管41朝引脚16方向移动。然后，如图5(f)所示，使得毛细管41下降，将引线52侧面挤压到挤压球颈51形成的压碎部21上。通过该引线52的挤压，引线52的弯曲部53朝着压碎部21的方向被折返，形成折返部34，挤压工序结束。第一层挤压部100的上面因毛细管41的面部44形成平面。在挤压部形成工序结束状态下，毛细管41成为比第一层焊接点14焊接中心线91靠近引脚16的位置。
若挤压工序结束，则开始第一引线形成工序。如图6所示，一边从毛细管下端输出第一引线25，一边使得毛细管41上升后，进行使得毛细管41朝与引脚16相反方向移动的逆向动作。因该逆向动作，毛细管41的位置成为从第一层焊接点14上的焊接中心线91靠向与引脚16相反方向的位置。在逆向动作结束状态下，第一引线25从第一层焊接点14朝与引脚16相反方向倾斜。另一方面，通过毛细管41，第一引线25保持在与第一层焊接点14的面大致垂直方向，因此，在逆向动作结束状态的毛细管41的前端附近的第一引线25，形成朝着与引脚16相反方向凸的弯曲。
逆向动作之后，进行弯折形成动作。如图7所示，若一边输出第一引线25，一边使得毛细管41上升，则在第一引线25因上述逆向动作形成朝着与引脚16相反方向凸的弯曲，因此，因毛细管41上升形成弯曲部35。通过毛细管41上升输出的第一引线25的长度比上述逆向动作时引线输出长度长。
接着，如图8所示，使得毛细管41越过第一层焊接点14上的焊接中心线91朝着引脚16成环(looping)。通过该成环，第一引线25从第一层焊接点14朝着引脚16方向延伸，第一引线形成工序结束。
接着，如图9所示，使得毛细管41移动到引脚16上之后，使得毛细管41向引脚16下降，将第一引线25点焊在引脚16上。通过该点焊，第一引线25在接合面36与引脚16接合，在第一引线25的第一层焊接点14和引脚16之间，形成从第一层焊接点14的面朝着引脚16向下弯曲的第一弯折部37。又，第一层焊接点14和第一弯折部37之间的第一引线25在沿第一层焊接点14的面形成。
若第一层焊接点14和引脚16之间的焊接结束，则开始作为第二层焊接点15和第一层焊接点14之间的焊接的第二引线接合工序。如图10所示，在朝毛细管41下端延伸的第二引线26的前端，通过放电或焊枪等形成初始球33。接着，使得毛细管41下降，使得初始球33压焊在第二层焊接点15上，与向第一层焊接点14焊接相同，实行如图5(a)所示那样的形成圆板状的压焊球17和球颈51的球焊工序。
球焊后，与上述参照图5(a)-5(f)说明的向第一层焊接点14焊接同样，使得毛细管41动作，形成压碎部及挤压部，如图11所示，在第二层焊接点15上的压焊球18上形成包含折返部20的第二层挤压部200。
若形成第二层挤压部200，则与从第一层焊接点14向引脚16的第一引线25焊接相同，如图11所示，一边从毛细管41下端输出第二引线26，一边使得毛细管41上升后，进行使得毛细管41朝与第一层焊接点14相反方向移动的逆向动作，在毛细管41的前端附近的第二引线26，形成朝着与第一层焊接点14相反方向凸的弯曲。
接着，如图12所示，与上述说明的第一引线25的焊接相同，一边输出第二引线26一边使得毛细管41上升，在第二引线26形成弯曲部38，如图13所示，越过第二层焊接点15上的焊接中心线92朝着第一层焊接点14，使得毛细管41成环。通过该成环，第二引线26从第二层焊接点15朝着第一层焊接点14方向延伸。
接着，如图14所示，使得毛细管41移动到第一层焊接点14上，毛细管41中心来到第一层焊接点14的焊接中心线91之后，使得毛细管41向第一层焊接点14下降，将第二引线26焊接在折返部34上，该折返部34位于形成在第一层焊接点14上的第一层挤压部100的第二层焊接点15侧。
关于第二引线26向第一层挤压部100的焊接，参照图15、图16进行详细说明。图15表示毛细管41移动，使得毛细管41的中心成为第一层焊接点14的焊接中心线91位置，毛细管41为了焊接下降前的状态。如图15所示，第二引线26从第二层焊接点15方向沿毛细管41的下面的面部44、内倒角部43，在直孔42中延伸，沿直孔42的第一层焊接点14侧的内面，朝上方向延伸。在第一层焊接点14上，在压焊球17上形成包含压碎部21及折返部34的第一层挤压部100，在沿第一层焊接点14的面，第一引线25从第一层挤压部100朝着引脚16方向延伸。
如图16所示，若从图15所示状态，使得毛细管41下降，则最初毛细管41的第二层焊接点15侧的面部44将从第二层焊接点15延伸的第二引线26夹入该面部44和第一层挤压部100的折返部34的上面之间。接着，若使得毛细管41进一步下降，对第二引线26施加挤压力，则第二引线26被压焊在面部44和折返部34之间。因此时的毛细管41的挤压力，折返部34上面变形，折返部34成为变形折返部19。接着，若进一步施加毛细管41的挤压力，则第二引线26接合在变形折返部19上面，形成接合面29。接合面29成为从变形折返部19的前端向着第一层挤压部100的中央斜向延伸的斜面。又，第二引线26上面与面部44相碰部分因毛细管41的挤压力变形为沿面部44形状的平面形状，形成平面部28。平面部28的第二层焊接点15侧因毛细管41的外圆角部45形成弯曲形状，与第二引线26的侧面相连。
又，若毛细管41将第二引线26挤压在第一层挤压部100的上面，则第二引线26被夹入毛细管41的内倒角部43和第一层挤压部100之间。第一层挤压部100系折返引线形成，因加工硬化，比第二引线26硬。即，第二引线26比第一层挤压部100柔软。又，内倒角部43系锥面，从毛细管41下端向着上方的直孔42直径变小形成，其面成为比面部44小的面积。因此，在因毛细管41的挤压力被夹于内倒角部43和第一层挤压部100之间的第二引线26，与夹于面部44和第一层挤压部100之间的第二引线26相比，受到大的压缩力，比第一层挤压部100柔软的第二引线26被压缩在内倒角部43和第一层挤压部100之间，形成为其截面积变小。
再有，第一层挤压部100由金引线形成，因此，比由陶瓷等构成的毛细管41柔软。因此，若毛细管41沿第一层焊接点14的焊接中心线91下降，则内倒角部43咬入第一层挤压部100的上面，第一层挤压部100的上面变形，挤入内倒角部43上部的直孔42中，成为凸部23，在凸部23的侧面，成形为沿内倒角部43形状的锥面24a、24b。第二引线26因进入内倒角部43及直孔42中的凸部23的第二层焊接点15侧的锥面24a以及内倒角部43，不能退避，被夹而压缩，有效地被压缩，其截面积变小。尤其，在与内倒角部43和面部44之间的角部相碰的凸部23的根部，压缩力集中，因此，被凸部23的根部夹入的第二引线26被压缩为截面积最小。
接着，因从内倒角部43的面施加的斜向力，在第一层挤压部100的中央产生朝着焊接中心线91方向的力。因该力凸部23进一步变形朝着毛细管41的直孔42被挤向上方，在凸部23的侧面形成沿直孔42形状的圆筒面24c、24d。
第二层焊接点15侧的圆筒面24c形成为与毛细管41的直孔42大致平行的方向，因此，不施加因毛细管41引起的挤压力。因此，第二引线26尽管在与第二层焊接点15侧的圆筒面24c之间被某种程度压缩，但成为在与圆筒面24c之间不接合的状态。
因毛细管41下降引起第二引线26接合，同时，毛细管41的引脚16侧的面部44挤压第一引线25的上面，在第一引线25上面形成沿面部44形状的呈平面状的平面部。
这样，在第二引线26的向第一层挤压部100的焊接结束状态下，第二引线26在接合面29与第一层挤压部100的第二层焊接点15侧接合，在第一层挤压部100的中央形成凸部23，夹在毛细管41的内倒角部43和凸部23的第二层焊接点15侧的锥面24a之间的第二引线26被压缩，在第一引线25上面形成平面部27，在第二引线26上面形成平面部28。并且，被压缩的第二引线26沿着直孔42朝上方向延伸。
如图17所示，若第二引线连接工序结束，则使得毛细管41上升，在毛细管41下端使得第二引线26延伸，形成尾端引线40后，使得毛细管41和第二引线26一起上升。于是，第二引线26在截面积最小的、由内倒角部43和面部44的角部以及凸部23的根部所夹的压缩部分被切断，成为在毛细管41下端延伸出尾端引线40的状态。因此，如图2、图3所示，在凸部23的根部分，沿着锥面24a形成第二引线26的切断面31。
如上所述的本实施形态的半导体装置10系在第一层焊接点14上通过金引线形成第一层挤压部100，在该第一层挤压部100上焊接第二引线26，因此，具有能缓和因第一层挤压部100变形引起的对接合的冲击，能减少因焊接而引起的第一层半导体芯片11所受到的损伤的效果。又，本实施形态具有以下效果：本发明的叠层型的半导体装置10通过由第一引线25连接第一层焊接点14和引脚16的工序，以及由第二引线26连接第二层焊接点15和第一层焊接点14的工序实行，焊接工序数少，顺序连接半导体装置10的各焊接点14、15和引脚16，能减少焊接工序数，缩短焊接时间。再有，第二引线26因进入内倒角部43及直孔42中的凸部23的第二层焊接点15侧的锥面24a以及内倒角部43，不能退避，被夹而压缩，有效地被压缩，其截面积与第二引线26的截面积相比非常小。因此，当切断引线时，能以小的拉引力切断第二引线26，具有能减少尾端引线变形、减少焊接不良的效果。再有，在本实施形态的半导体装置10中，还在第二层焊接点15上形成第二层挤压部200，能降低半导体装置10整体的高度，具有能使得半导体装置10为薄型的效果。
在上述说明的本实施形态的半导体装置10中，说明还在第二层半导体芯片12的第二层焊接点15上形成第二层挤压部200，但是，也可以在第二层焊接点15上进行球焊，在该状态下将第二引线26成环在第一层挤压部100上，在第一层挤压部100的第二层焊接点15侧进行焊接。这种场合，因不构成第二层挤压部200，具有能缩短整体焊接时间的效果。
又，在本实施形态中，半导体装置10系在引脚框13上叠层接合作为第一半导体芯片的第一层半导体芯片11，和尺寸大小比第一层半导体芯片11小的、作为第三半导体芯片的第二层半导体芯片12的二层叠层结构，第一层半导体芯片11在表面设有作为第一接合点的第一层焊接点14，第二层半导体芯片12在表面设有作为第三接合点的第二层焊接点15，引脚框13在表面设有作为第二接合点的引脚16，各焊接点14、15以及引脚框16配置成阶梯状，但是，也可以适用于例如以下半导体装置：焊接点为三个或三个以上，若第三焊接点位于与从第一焊接点向第二焊接点方向相反的方向，则在引脚框叠层三层或三层以上的半导体芯片。
参照图18、图19说明在三层叠层的半导体装置上进行焊接场合。与参照图4-图17说明的实施形态相同工序，说明省略。如图18所示，三层叠层的半导体装置400从引脚框410侧叠层第一层半导体芯片411，第二层半导体芯片412，第三层半导体芯片413，三层叠层。在焊接工序中，最初，在第一层半导体芯片411的第一层焊接点414上形成第一层挤压部401，用引线425焊接第一层焊接点414和引脚框410的引脚416之间，接着，在第二层半导体芯片412的第二层焊接点415上形成第二层挤压部402，使得引线426成环在第一层挤压部401上，焊接在第一层挤压部401的第二层半导体芯片412侧。在该焊接中，第一层半导体芯片411是第一半导体芯片，第一层焊接点414是第一焊接点，第二层半导体芯片是第三半导体芯片，引脚416是第二焊接点，第三层半导体芯片412的第二层焊接点415是第三焊接点。又，引线425是对于第一层挤压部401的第一引线，引线426是对于第一层挤压部的第二引线。
如图19所示，若引脚框410和第一层半导体芯片411和第二层半导体芯片412之间的焊接结束，则进行第二层半导体芯片412和第三层半导体芯片413的焊接。在第二层焊接点415上已经形成第二层挤压部402，通过引线426连接第二层挤压部402和第一层挤压部401之间。在该状态下，第二层半导体芯片412是第一半导体芯片，第二层半导体芯片412的第二焊接点415是第一焊接点，引线426成为对于第二层挤压部402的第一引线，第一层半导体芯片411成为第二层半导体芯片412的与引脚框410侧邻接的第二半导体芯片，第一层半导体芯片411的第一层焊接点414成为第二焊接点。
接着，在第三层半导体芯片413的第三层焊接点417上形成第三层挤压部403，将引线427从第三层挤压部403成环到第二层挤压部402上，焊接在第二层挤压部402的第三层半导体芯片413侧。在该焊接中，第三层半导体芯片413是第三半导体芯片，第三层半导体芯片413的第三层焊接点417是第三焊接点，引线427成为对于第二层挤压部402的第二引线。
在图18和图19中，说明三层叠层的半导体装置400的焊接，但是，只要有至少三个焊接点，即使各焊接点不配置为阶梯状，例如配置为平面状场合，本发明也同样适用。又，与焊接点数多例如专利文献1记载的以往技术相比，具有能大幅度减少焊接工序数、时间的效果。
下面，参照图20、图21说明本发明另一实施形态。如图20所示，本实施形态的半导体装置500系在引脚框313上安装半导体芯片311，用第一引线325连接设在半导体芯片311表面的焊接点314和设在引脚框313上的引脚316，用第二引线326a连接设在半导体芯片311表面的焊接点314和315a，用第二引线326b连接设在半导体芯片311表面的焊接点314和315b，用第二引线326c连接设在半导体芯片311表面的焊接点314和315c，各第二引线326a、326b、326c焊接在形成在焊接点314上的挤压部300上。
在本实施形态中，与上述说明的实施形态相同，用以下那样的方法进行焊接。首先，与参照图4和图5说明相同的方法，在作为第一焊接点的半导体芯片311的焊接点314上，形成包含如图1所示压焊球317、折返部319、以及压碎部321的挤压部300，采用与参照图6-图9说明相同的方法，将第一引线325成环在作为第二焊接点的引脚316上，从挤压部300向着引脚316使得第一引线延伸，将第一引线焊接在引脚316上。接着，进行向作为第三焊接点的三个焊接点315a、315b、315c的焊接点315a上的焊接，所述第三焊接点配置在与从作为第一焊接点的焊接点314朝着作为第二焊接点的引脚316的方向不同的方向，形成压焊球318a后，使得第二引线326a朝着挤压部300成环，焊接在挤压部300的焊接点315a侧。同样，在焊接点315b上形成压焊球318b，在焊接点315c上形成压焊球318c，将第二引线326b、326c分别朝着挤压部300成环，分别焊接在挤压部300的焊接点315b侧、315c侧。这种场合，各第二引线326b、326c的接合部可以重合在上述先焊接的第二引线326a上。这样，各第二引线326a、326b、326c从作为第三焊接点的三个焊接点315a、315b、315c成环焊接在挤压部300。各第二引线326a、326b、326c和挤压部300的焊接与上述参照图15和图16所说明的方法相同。
在挤压部300的中央通过焊接形成凸部323，其在周围具有锥面324，在锥面324和形成在各第二引线326a、326b、326c上的平面部328a、328b、328c之间，形成各第二引线326a、326b、326c的各切断面331a、331b、331c。
在本实施形态中，除了具有上述说明的实施形态同样效果之外，由于将各第二引线326a、326b、326c从一个挤压部300的周向不同角度焊接，因此，即使各第二引线326a、326b、326c的接合部重合，焊接后的挤压部300的高度不大变化，具有能抑制半导体装置500的整体高度，能从多个焊接点向一个焊接点连接的效果。

Claims (10)

1.一种半导体装置，通过各引线连接至少三个焊接点之中、各两个焊接点之间，其特征在于，包括：
挤压部，将插入穿通毛细管从其下端突出的引线前端形成的初始球焊接在第一焊接点上，形成球颈，压碎该球颈，挤压在上述压碎球颈上折返的引线的侧面形成；
第一引线，从挤压部向第二焊接点延伸；
各第二引线，至少一个第三焊接点位于与从第一焊接点向着第二焊接点方向不同的方向，从该第三焊接点向着挤压部成环，与挤压部的各第三焊接点侧接合。
2.根据权利要求1所述的半导体装置，其特征在于：
第二引线通过毛细管下降用毛细管的面部与挤压部接合，同时，因毛细管的挤压力变形，被夹入进入毛细管中心孔的凸部和毛细管的内倒角部之间被压缩。
3.根据权利要求2所述的半导体装置，其特征在于：
因毛细管的挤压力，凸部变形为沿毛细管的中心孔的形状，第二引线沿上述凸部具有切断面。
4.一种半导体装置，在引脚框上叠层半导体芯片，通过各引线顺序连接邻接的各半导体芯片的焊接点之间，或半导体芯片的焊接点和引脚框的引脚之间，其特征在于，包括：
挤压部，将插入穿通毛细管从其下端突出的引线前端形成的初始球焊接在第一半导体芯片的焊接点上，形成球颈，压碎该球颈，挤压在上述压碎球颈上折返的引线的侧面形成；
第一引线，从挤压部向引脚或与引脚框侧邻接的第二半导体芯片的焊接点的方向延伸；
第二引线，第三半导体芯片与第一半导体芯片的引脚框侧的相反侧邻接，从该第三半导体芯片的焊接点向着挤压部成环，与挤压部的第三半导体芯片 的焊接点侧接合。
5.根据权利要求4所述的半导体装置，其特征在于：
第二引线通过毛细管下降用毛细管的面部与挤压部接合，同时，因毛细管的挤压力变形，被夹入进入毛细管中心孔的凸部和毛细管的内倒角部之间被压缩。
6.根据权利要求5所述的半导体装置，其特征在于：
因毛细管的挤压力，凸部变形为沿毛细管的中心孔的形状，第二引线沿上述凸部具有切断面。
7.一种引线接合方法，通过各引线连接至少三个焊接点之中、各两个焊接点之间，其特征在于，包括：
球焊工序，将插入穿通毛细管从其下端突出的引线前端形成的初始球焊接在焊接点上；
压碎工序，用毛细管前端压碎由上述球焊工序形成的球颈；
挤压工序，将引线折返在由毛细管压碎的球颈上，使得该引线侧面挤压在上述压碎的球颈上；
第一引线形成工序，通过毛细管输出引线后，向着第二焊接点成环，形成向着第二焊接点的第一引线；
第二引线接合工序，至少一个第三焊接点位于与从第一焊接点向着第二焊接点方向不同的方向，从该第三焊接点向着挤压部成环，使得各第二引线与挤压部的各第三焊接点侧接合。
8.根据权利要求7所述的引线接合方法，其特征在于：
在第二引线连接工序中，使得毛细管下降，通过毛细管的面部使得第二引线与挤压部接合，同时，用毛细管的挤压力，使得外径比毛细管中心孔内径大的挤压部变形为进入毛细管中心孔的凸部，将第二引线夹入进入毛细管中心孔的凸部和毛细管的内倒角部之间被压缩。
9.一种引线接合方法，在引脚框上叠层半导体芯片，通过各引线顺序连接邻接的各半导体芯片的焊接点之间，或半导体芯片的焊接点和引脚框的引脚之间，其特征在于，包括：
球焊工序，将插入穿通毛细管从其下端突出的引线前端形成的初始球焊 接在第一半导体芯片的焊接点上；
压碎工序，用毛细管前端压碎由上述球焊工序形成的球颈；
挤压工序，将引线折返在由毛细管压碎的球颈上，使得该引线侧面挤压在上述压碎的球颈上；
第一引线形成工序，通过毛细管输出引线后，通过向着引脚或与引脚框邻接的第二半导体芯片的焊接点方向成环，形成向着引脚或第二半导体芯片的焊接点的方向的第一引线；
第二引线连接工序，第三半导体芯片与第一半导体芯片的引脚框侧的相反侧邻接，从该第三半导体芯片的焊接点向着挤压部成环，使得第二引线与挤压部的第三半导体芯片的焊接点侧接合。
10.根据权利要求9所述的引线接合方法，其特征在于：
在第二引线连接工序中，使得毛细管下降，通过毛细管的面部使得第二引线与挤压部接合，同时，用毛细管的挤压力，使得外径比毛细管中心孔内径大的挤压部变形为进入毛细管中心孔的凸部，将第二引线夹入进入毛细管中心孔的凸部和毛细管的内倒角部之间被压缩。 
CN2008801082514A 2007-09-21 2008-03-25 半导体装置及引线接合方法 Expired - Fee Related CN101802993B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2007-246033 2007-09-21
JP2007246033A JP4397408B2 (ja) 2007-09-21 2007-09-21 半導体装置及びワイヤボンディング方法
PCT/JP2008/055484 WO2009037878A1 (ja) 2007-09-21 2008-03-25 半導体装置及びワイヤボンディング方法

Publications (2)

Publication Number Publication Date
CN101802993A CN101802993A (zh) 2010-08-11
CN101802993B true CN101802993B (zh) 2011-09-28

Family

ID=40467703

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2008801082514A Expired - Fee Related CN101802993B (zh) 2007-09-21 2008-03-25 半导体装置及引线接合方法

Country Status (6)

Country Link
US (1) US7821140B2 (zh)
JP (1) JP4397408B2 (zh)
KR (1) KR100967544B1 (zh)
CN (1) CN101802993B (zh)
TW (1) TW200915450A (zh)
WO (1) WO2009037878A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103177979A (zh) * 2011-12-26 2013-06-26 富士电机株式会社 引线键合装置、工具及主体、半导体装置制造及键合方法

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5481769B2 (ja) * 2006-11-22 2014-04-23 日亜化学工業株式会社 半導体装置及びその製造方法
JP5062283B2 (ja) * 2009-04-30 2012-10-31 日亜化学工業株式会社 半導体装置及びその製造方法
JP5692081B2 (ja) * 2009-10-09 2015-04-01 日亜化学工業株式会社 半導体装置及びその製造方法
JP4787374B2 (ja) * 2010-01-27 2011-10-05 株式会社新川 半導体装置の製造方法並びにワイヤボンディング装置
TWI409933B (zh) * 2010-06-15 2013-09-21 Powertech Technology Inc 晶片堆疊封裝結構及其製法
JP2012004464A (ja) * 2010-06-18 2012-01-05 Toshiba Corp 半導体装置、半導体装置の製造方法及び半導体装置の製造装置
US8609525B2 (en) * 2011-03-21 2013-12-17 Stats Chippac Ltd. Integrated circuit packaging system with interconnects and method of manufacture thereof
KR20130042210A (ko) 2011-10-18 2013-04-26 삼성전자주식회사 멀티-칩 패키지 및 그의 제조 방법
KR101917331B1 (ko) * 2012-02-08 2018-11-13 삼성전자주식회사 반도체 패키지 및 이를 제조하는 방법
JP2013191738A (ja) * 2012-03-14 2013-09-26 Toshiba Corp 半導体装置およびその製造方法
KR101963314B1 (ko) 2012-07-09 2019-03-28 삼성전자 주식회사 반도체 패키지 및 이의 제조 방법
CN103579063B (zh) * 2012-08-07 2016-05-11 无锡华润安盛科技有限公司 引线键合线夹及其设备和方法
TWI518814B (zh) * 2013-04-15 2016-01-21 新川股份有限公司 半導體裝置以及半導體裝置的製造方法
KR20140135319A (ko) * 2013-05-15 2014-11-26 삼성전자주식회사 와이어 본딩 방법 및 이를 이용하여 제조된 반도체 패키지
JP2015173235A (ja) 2014-03-12 2015-10-01 株式会社東芝 半導体装置及びその製造方法
JP2014140074A (ja) * 2014-04-17 2014-07-31 Toshiba Corp 半導体装置
WO2018225571A1 (ja) * 2017-06-09 2018-12-13 富士電機株式会社 半導体装置および半導体装置の製造方法
KR102460014B1 (ko) * 2018-08-24 2022-10-26 삼성전자주식회사 반도체 패키지
US11581285B2 (en) * 2019-06-04 2023-02-14 Kulicke And Soffa Industries, Inc. Methods of detecting bonding between a bonding wire and a bonding location on a wire bonding machine

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005116961A (ja) * 2003-10-10 2005-04-28 Denso Corp 半導体装置
CN1230884C (zh) * 2002-08-08 2005-12-07 株式会社海上 引线键合方法以及凸点形成方法和凸点
JP2005340777A (ja) * 2004-04-26 2005-12-08 Kaijo Corp ボンディングワイヤのループ形状及びそのループ形状を備えた半導体装置並びにワイヤボンディング方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5172851A (en) * 1990-09-20 1992-12-22 Matsushita Electronics Corporation Method of forming a bump electrode and manufacturing a resin-encapsulated semiconductor device
JP3178567B2 (ja) * 1993-07-16 2001-06-18 株式会社カイジョー ワイヤボンディング装置及びその方法
US6835898B2 (en) * 1993-11-16 2004-12-28 Formfactor, Inc. Electrical contact structures formed by configuring a flexible wire to have a springable shape and overcoating the wire with at least one layer of a resilient conductive material, methods of mounting the contact structures to electronic components, and applications for employing the contact structures
JP3869562B2 (ja) 1998-10-16 2007-01-17 三洋電機株式会社 半導体装置の製造方法
JP2001127246A (ja) * 1999-10-29 2001-05-11 Fujitsu Ltd 半導体装置
JP3573133B2 (ja) * 2002-02-19 2004-10-06 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
JP3935370B2 (ja) * 2002-02-19 2007-06-20 セイコーエプソン株式会社 バンプ付き半導体素子の製造方法、半導体装置及びその製造方法、回路基板並びに電子機器
JP3584930B2 (ja) 2002-02-19 2004-11-04 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
US7229906B2 (en) * 2002-09-19 2007-06-12 Kulicke And Soffa Industries, Inc. Method and apparatus for forming bumps for semiconductor interconnections using a wire bonding machine
JP4298665B2 (ja) * 2005-02-08 2009-07-22 株式会社新川 ワイヤボンディング方法
JP4881620B2 (ja) * 2006-01-06 2012-02-22 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
JP2008066331A (ja) * 2006-09-04 2008-03-21 Renesas Technology Corp 半導体装置の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1230884C (zh) * 2002-08-08 2005-12-07 株式会社海上 引线键合方法以及凸点形成方法和凸点
JP2005116961A (ja) * 2003-10-10 2005-04-28 Denso Corp 半導体装置
JP2005340777A (ja) * 2004-04-26 2005-12-08 Kaijo Corp ボンディングワイヤのループ形状及びそのループ形状を備えた半導体装置並びにワイヤボンディング方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103177979A (zh) * 2011-12-26 2013-06-26 富士电机株式会社 引线键合装置、工具及主体、半导体装置制造及键合方法

Also Published As

Publication number Publication date
US20100237480A1 (en) 2010-09-23
US7821140B2 (en) 2010-10-26
CN101802993A (zh) 2010-08-11
TWI370499B (zh) 2012-08-11
JP4397408B2 (ja) 2010-01-13
KR20100028125A (ko) 2010-03-11
TW200915450A (en) 2009-04-01
JP2009076783A (ja) 2009-04-09
KR100967544B1 (ko) 2010-07-05
WO2009037878A1 (ja) 2009-03-26

Similar Documents

Publication Publication Date Title
CN101802993B (zh) 半导体装置及引线接合方法
US7276437B2 (en) Semiconductor device and manufacturing method thereof
US7033859B2 (en) Flip chip interconnection structure
US20180114782A1 (en) Manufacturing method of package-on-package structure
CN102187443B (zh) 引线焊接方法以及半导体装置及其制造方法
CN101335252A (zh) 半导体装置及引线接合方法
KR20070044812A (ko) 낮은 루프 와이어 접합을 위한 방법 및 시스템
JP5002329B2 (ja) 半導体装置及びワイヤボンディング方法
WO2014171160A1 (ja) 半導体装置および半導体装置の製造方法
CN101281876A (zh) 半导体器件的制造方法以及半导体器件
JP2001015541A (ja) 半導体装置および半導体装置の製造方法
US20100133671A1 (en) Flip-chip package structure and the die attach method thereof
US20220165709A1 (en) Stacked semiconductor package and packaging method thereof
US9780053B2 (en) Method of forming a bondpad and bondpad
US20090020872A1 (en) Wire bonding method and semiconductor device
US20110068469A1 (en) Semiconductor package with pre-formed ball bonds
CN102556938B (zh) 芯片叠层封装结构及其制造方法
CN111933605A (zh) 芯片焊接结构及焊接方法
CN217983331U (zh) 一种带有预成型高铜柱结构的Hybrid芯片封装结构
JP2004235411A (ja) 電子部品のボンディング方法及び装置
KR101800619B1 (ko) 반도체 패키지 제조방법
CN115020257A (zh) 芯片堆叠的互连方法
JP2009044115A (ja) ワイヤボンディング方法及び半導体装置
US20090294939A1 (en) Lead frame and semiconductor device utilizing the same

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20110928

Termination date: 20130325