CN101335252A - 半导体装置及引线接合方法 - Google Patents

半导体装置及引线接合方法 Download PDF

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CN101335252A
CN101335252A CNA2008101292020A CN200810129202A CN101335252A CN 101335252 A CN101335252 A CN 101335252A CN A2008101292020 A CNA2008101292020 A CN A2008101292020A CN 200810129202 A CN200810129202 A CN 200810129202A CN 101335252 A CN101335252 A CN 101335252A
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pin
lead
wire
towards
capillary
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三井竜成
木内逸人
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Shinkawa Ltd
Arakawa Co Ltd
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Arakawa Co Ltd
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Abstract

本发明涉及半导体装置及引线接合方法。引线(21)焊接在半导体芯片(11)表面的焊接点(13)上后,边从毛细管输送引线(21),边使得毛细管朝引脚(17)方向以及与引脚(17)相反方向移动,形成使得引线(21)朝与引脚(17)相反方向凸出的第一扭折,朝引脚(17)方向凸出的第二扭折,以及与第二扭折连续的直线部之后,将毛细管闭环处理接合引线(21)和引脚(17),接合时,使得直线部作为沿引脚(17)表面方向的直线部(31)成形,同时,使得直线部(31)推压引脚(17)表面。在本半导体装置中,能抑制焊接时因超声波励振对其他已焊接完的引线造成损伤。

Description

半导体装置及引线接合方法
技术领域
本发明涉及半导体装置的结构及半导体装置的引线接合方法。
背景技术
在IC等半导体装置的组装工序中有用引线连接半导体芯片和引脚框之间的引线接合工序。引线接合工序一般使用以下方法:引线插入穿通毛细管,使用该毛细管,通过焊枪电极放电,在从毛细管突出的引线前端形成球,使得毛细管位于半导体芯片的焊接点(pad)上,进行一次焊接后,使得毛细管移动到引脚框的引脚上,进行二次焊接,通过引线连接半导体芯片和引脚框之间(例如,参照专利文献1)。
在上述那样的引线接合方法中,二次焊接的引线与引脚间的接合面积是夹在毛细管的面部和引脚间的引线面积,其小于通过球焊接合的一次焊接的引线和焊接点间的接合面积,接合强度变低,焊接可靠性变差。
于是,作为提高上述那样的二次焊接中接合部的强度从而改善焊接可靠性的方法,专利文献1提出了以下方法:对引脚进行二次焊接后,将引线折返再次与引脚焊接。专利文献2则提出了以下方法:使得引线与引脚连接的同时移动毛细管,形成二次焊接的带状接合部以增加接合面积,从而提高二次焊接中接合部的强度。
另一方面,在半导体装置中,半导体芯片和引脚间通过引线接合后,整体以树脂密封进行半导体封装是比较常见的方法。然而,在半导体封装的实际工序中,若被树脂密封的半导体封装的温度上升,可能会因树脂热膨胀而在引线中产生应力。这种场合,二次焊接的接合部与引脚的接合部的厚度会变薄,因热膨胀引起的应力集中,可能会在接合部产生裂缝。因此,在专利文献3中提出了以下方法:与二次焊接的接合部的半导体芯片侧邻接设置比引线连接用的接合部厚度厚的接合部,减少因树脂热膨胀引起裂缝的现象。而专利文献4则提出了以下方法:为了避免树脂进入引脚和引线之间,二次焊接时,使得毛细管从引脚端部沿引脚面平行移动,使引线与引脚紧密连接。
[专利文献1]日本特公平3-63814号公报
[专利文献2]日本特开昭52-67262号公报
[专利文献3]日本特开平2-30153号公报
[专利文献4]日本特开平8-293512号公报
近年来,在半导体装置制造中,大多使用将复数个半导体芯片作为整体用树脂密封的整体封装法,代替将各半导体芯片分别用树脂密封的个别封装法。使用该整体封装法场合,使用以下引脚框:将安装半导体芯片的复数个岛(island)及与之对应的复数个引脚密集作为一个区段(block)配置,在背面粘贴防止密封剂泄漏用的带。当将上述那样的引脚框为了接合固定在焊接台上场合,通过背面的带真空吸附在焊接台上,而且在密集复数个半导体芯片的区段周边,从上方推压引脚框,因此,引脚框在焊接台上的固定状态并不好,引线接合时会产生引线振动的问题。
尤其,对某引线进行接合时,对该引线施加超声波励振,会使得已完成焊接的其他引线与引脚的接合部或者焊接点侧的球颈产生裂缝,成为断线的原因。
然而,在专利文献1至4中,并没有关于上述那样接合时施加超声波励振对其他已完成焊接的引线产生损伤的内容,在专利文献1至4记载的现有技术中,无法解决上述问题。
发明内容
本发明就是为解决上述现有技术所存在的问题而提出来的,本发明的目的在于,抑制接合时施加超声波励振对其他已完成焊接的引线造成的损伤。
为了达到上述目的,本发明提出以下技术方案:
(1)一种半导体装置,半导体芯片表面的焊接点与引脚通过引线连接,在与引脚框的半导体芯片安装面相反侧的面粘贴带,进行制造,其特征在于:
该半导体装置包括:
球焊部,引线插入穿通毛细管,从其下端凸出,在该引线前端形成初始压焊球,将该初始压焊球焊接在焊接点上;
引线,从球焊部向引脚延伸,与引脚接合;
引线在球焊后的引线输送工序中,形成朝与引脚相反方向凸出的第一扭折以及朝引脚方向凸出的第二扭折,此后经闭环处理与引脚接合;
引线由以下各部分形成:从焊接点朝引脚延伸、朝半导体芯片厚度方向弯曲的第一弯曲部,朝与第一弯曲部相反方向弯曲的第二弯曲部,从第二弯曲部朝引脚、沿引脚表面方向延伸的直线部,以及焊接在引脚上的直线部侧端部;
直线部的引脚侧面朝引脚表面被推压。
(2)一种半导体装置,半导体芯片表面的焊接点与引脚通过引线连接,在与引脚框的半导体芯片安装面相反侧的面粘贴带,进行制造,其特征在于:
该半导体装置包括:
挤压部,引线插入穿通毛细管,从其下端凸出,在该引线前端形成初始压焊球,将该初始压焊球焊接在焊接点上,成为球焊部,压碎形成在球焊部上的球颈,挤压在压碎的球颈上折返的引线侧面形成该挤压部;
引线,从挤压部向引脚延伸并与引脚接合;
引线在挤压部形成后的引线输送工序中,形成朝与引脚相反方向凸出的第一扭折以及朝引脚方向凸出的第二扭折,此后经闭环处理与引脚接合;
引线由以下各部分形成:从挤压部朝引脚延伸、朝半导体芯片厚度方向弯曲的第一弯曲部,朝与第一弯曲部相反方向弯曲的第二弯曲部,从第二弯曲部朝引脚、沿引脚表面方向延伸的直线部,以及焊接在引脚上的直线部侧端部;
直线部的引脚侧面朝引脚表面被推压。
(3)一种引线接合方法,系半导体装置的引线接合方法,半导体芯片表面的焊接点与引脚通过引线连接,引线插入穿通毛细管,从其下端突出,在该引线前端形成初始压焊球,将该初始压焊球焊接在焊接点上,形成球焊部,从该球焊部向引脚延伸,形成朝半导体芯片厚度方向弯曲的第一弯曲部,朝与第一弯曲部相反方向弯曲的第二弯曲部,从第二弯曲部朝引脚、沿引脚表面方向延伸的直线部,以及焊接在引脚上的直线部侧端部,直线部的引脚侧面朝引脚表面被推压,在与引脚框的半导体芯片安装面相反侧的面粘贴带,进行制造,其特征在于,该引线接合方法包括:
第一焊接工序,引线插入穿通毛细管,从其下端突出,在该引线前端形成初始压焊球,将该初始压焊球推压至焊接点上进行接合;
反向工序,边输送引线,边使得毛细管上升后,使得毛细管朝与引脚相反方向移动;
第一扭折形成工序,边输送比上述反向工序长的引线,边使得毛细管上升后,使得毛细管朝引脚方向移动直到超过焊接点的接合中心的位置,在引线上形成朝与引脚相反方向凸出的第一扭折;
第二扭折形成工序,边输送引线,边使得毛细管上升后,使得毛细管朝与引脚相反方向移动直到焊接点的接合中心位置,形成朝引脚方向凸出的第二扭折以及与该第二扭折连续的直线部;
第二焊接工序,使得毛细管朝引脚进行闭环处理,将毛细管推压在引脚上,使引线与引脚接合。
(4)一种引线接合方法,系半导体装置的引线接合方法,半导体芯片表面的焊接点与引脚通过引线连接,引线插入穿通毛细管,从其下端突出,在该引线前端形成初始压焊球,将该初始压焊球焊接在焊接点上,形成球焊部,在球焊部上形成球颈,引线包括压碎所述球颈、挤压在压碎的球颈上折返的引线侧面形成的挤压部,从该挤压部向引脚延伸、朝半导体芯片厚度方向弯曲的第一弯曲部,朝与第一弯曲部相反方向弯曲的第二弯曲部,从第二弯曲部朝引脚、沿引脚表面方向延伸的直线部,以及焊接在引脚上的直线部侧端部,直线部的引脚侧面朝引脚表面被推压,在与引脚框的半导体芯片安装面相反侧的面粘贴带,进行制造,其特征在于,该引线接合方法包括:
第一焊接工序,引线插入穿通毛细管,从其下端突出,在该引线前端形成初始压焊球,将该初始压焊球推压至焊接点上进行接合;
挤压部形成工序,输送引线,同时边提升毛细管,边使得毛细管朝与引脚相反方向移动后,降低毛细管,用毛细管面部压碎球颈,再次输送引线,同时边提升毛细管,边朝引脚方向移动后,再次降低毛细管,将引线侧面推压在被压碎的球颈上形成挤压部;
反向工序,边输送引线,边使得毛细管上升后,使得毛细管朝与引脚相反方向移动直到超过焊接点的接合中心的位置;
第一扭折形成工序,边输送比上述反向工序长的引线,边使得毛细管上升后,使得毛细管朝引脚方向移动直到超过焊接点的接合中心的位置,在引线上形成朝与引脚相反方向凸出的第一扭折;
第二扭折形成工序,边输送引线,边使得毛细管上升后,使得毛细管朝与引脚相反方向移动直到焊接点的接合中心位置,形成朝引脚方向凸出的第二扭折以及与该第二扭折连续的直线部;
第二焊接工序,使得毛细管朝引脚进行闭环处理,将毛细管推压在引脚上,使引线与引脚接合。
下面说明本发明的效果。
本发明具有抑制接合时施加超声波励振对其他已完成焊接的引线造成损伤的效果。
附图说明
图1是在整体封装法中使用的引脚框的平面图。
图2是表示在整体封装法中使用的引脚框被固定至焊接台的状态的截面图。
图3是表示在整体封装法中使用的引脚框实行引线焊接状态的局部平面图。
图4表示本发明实施形态的半导体装置的用于连接半导体芯片和引脚的引线。
图5是表示本发明实施形态的半导体装置的引脚侧的引线的立体图。
图6是表示本发明实施形态的半导体装置的引线接合工序的说明图。
图7表示本发明另一实施形态的半导体装置的用于连接半导体芯片和引脚的引线。
图8是表示本发明另一实施形态的半导体装置的焊接点侧的挤压部的立体图。
图9是表示本发明另一实施形态的半导体装置的用于形成挤压部的引线接合工序的说明图。
图10是表示本发明另一实施形态的半导体装置的挤压部形成之后的引线接合工序的说明图。
符号说明如下:
10半导体装置、11半导体芯片、12引脚框、13焊接点、15岛、16带、17引脚、21引线、23压焊球、25球颈、25a压碎部、25b弯曲部、26挤压部、26a折返部、26b平面部、27第一弯曲部、28接合中心线、29第二弯曲部、31直线部、33直线部侧端部、34弯曲部、35第一扭折、37第二扭折、38直线部、41毛细管、43面部、45内倒角部、47直孔、50段组、53焊接台、55真空吸附孔、60切断区域、70区段、71压框。
具体实施方式
下面参照附图说明本发明的半导体装置的实施形态。如图1所示,使用整体封装法制造半导体装置时,引脚框12上设有复数个安装半导体芯片的岛15以及复数个与安装在岛15上的半导体芯片表面焊接点相对应的引脚17。各岛15以及与其对应的引脚形成一组,构成一个段组(segment)50。各段组50是指以下区域:在安装半导体芯片,进行引线接合和树脂密封之后,通过切断设置在各段组之间的切断区域60,各自成为一个半导体装置。引脚框12上密集设置段组50,由复数个段组50构成一个区段70。区段70为树脂密封时整体化封装的范围。另外,各区段70周围设有空间,引线接合时,通过压框71从上方推压固定区段70外周。
如图2所示,在引脚框12背面贴有可再次剥离的带16,该带16使得封装用树脂不从岛15和引脚17间泄漏。上述那样的引脚框12在岛15上安装半导体芯片11后,被传送至焊接台53上,由焊接台53的真空吸附孔55通过带16,该引脚框12被真空吸附在焊接台53上,同时,通过压框71从上方推压各区段70的外围,固定至焊接台53上。并且,各半导体芯片11的各焊接点与各引脚17间通过引线21连接。
若引脚框12固定至焊接台53上,则如图3所示,安装在各岛15上的半导体芯片11表面的各焊接点13和与之对应的各引脚17间依次通过引线21连接。因此,在引线接合工序中,在与已完成焊接的引线21邻接的位置对下一焊接点13或引脚17进行焊接。接着,若引脚框12上的所有半导体芯片11的焊接点13与对应的引脚17间的连接完成,则在下一道工序中将引脚框12按每个区段70通过树脂整体密封,之后切断所述切断区域60,制造各半导体装置10。
这种半导体装置的外部连接电极不从树脂密封后的封装凸出,在封装背面形成外部连接电极,因此,被称作四面扁平无引脚封装(Quad FladNon-1eaded Package,以下简记为“QFN”)。
如图4所示,在半导体装置10中,背面贴有带16的引脚框12的岛15上安装有半导体芯片11,其表面上的焊接点13与引脚框12上的引脚17间通过引线21相连接。引线21由以下部分形成:焊接在半导体芯片11表面焊接点13上的压焊球23;从压焊球23向引线21截面积变化的球颈25;从球颈25沿半导体芯片11厚度方向立起,朝引脚17延伸,沿半导体芯片11厚度方向朝下弯曲的第一弯曲部27;朝与第一弯曲部27相反方向即向上方向弯曲的第二弯曲部29;从第二弯曲部29朝引脚17、沿引脚17表面方向延伸的直线部31;以及焊接在引脚17上的直线部侧端部33。
如图5所示,焊接时通过毛细管向引线21的直线部侧端部33施加超声波励振,同时将其推压到引脚17上,与引脚17相接合。焊接时直线部侧端部33按照毛细管前端形状发生变形,从棒状的直线部31朝着直线部侧端部33方向,引线厚度逐渐变薄。
引线21的两侧被焊接点侧的压焊球23和引脚侧的直线部侧端部33这两点所固定,其直线部31的引脚侧面朝着引脚17表面被推压。由图6所示那样的焊接工序,通过焊接引线21带来该推压力。
如图6(a)所示,通过毛细管41对形成在引线21前端的没有图示的初始压焊球实行超声波励振,并将其推压在焊接点13上接合,与此同时,在焊接点13上形成压焊球23和球颈25的第一焊接工序后,一边从毛细管41前端输送引线21,一边使得毛细管41上升后,进行使引线21朝与引脚17相反方向移动的反向工序。通过该反向工序,毛细管41的位置成为相对焊接点13的接合中心线28偏向引脚17的相反侧。在反向工序结束状态下,引线21从焊接点13朝引脚17的相反侧倾斜。另一方面,引线21通过毛细管41保持在与焊接点13面大致垂直方向,因此,在反向工序结束状态的毛细管41前端附近的引线21上,有朝引脚17的相反方向凸出的弯曲部分。
反向工序之后进行第一扭折(kink)形成工序。如图6(b)所示,若边输送引线21边使得毛细管41上升,则在上述反向工序中在引线21上朝与引脚17相反方向形成凸出的弯曲部分,因此,通过毛细管41上升形成弯曲部34。通过毛细管41上升输送的引线21的长度比上述反向工序中引线输送长度长。接着,如图6(c)所示,若使得毛细管41越过焊接点13的接合中心线28,朝引脚17方向移动,则弯曲部34的弯曲程度更大,形成朝与引脚17的相反方向凸出的第一扭折35。毛细管41相对焊接点13的接合中心线28偏向引脚17侧,第一扭折35相对焊接点13的接合中心线28形成在引脚17的相反侧,因此,引线21在第一扭折35和毛细管41之间,成为从与引脚17相反方向朝着引脚17方向倾斜的状态。另一方面,引线21通过毛细管41保持在与焊接点13面大致垂直的方向,因此,在第一扭折形成工序结束状态的毛细管41前端附近的引线21,有朝引脚17方向凸出的弯曲部分。
第一扭折形成工序之后进行第二扭折形成工序。如图6(d)所示,边输送引线21边使得毛细管41上升后,使得毛细管41朝与引脚17相反方向移动,使得毛细管41中心位置成为焊接点13的接合中心线28的位置。在之前的第一扭折形成工序中,在引线21上形成朝引脚17方向凸出的弯曲部分,因此,通过毛细管41上升以及朝与引脚17相反侧的移动,引线21上形成朝引脚17方向凸出的第二扭折37。另外,在第二扭折37与毛细管41之间,形成引线21直线状延伸的直线部38。
第二扭折37形成工序之后进行第二焊接工序。如图6(e)所示,第二扭折形成工序之后,将毛细管41从焊接点13的接合中心线28朝引脚17进行闭环处理。通过闭环处理,第一扭折35的弯曲程度更大,成为从球颈25沿半导体芯片11厚度方向立起,朝引脚17延伸,再沿半导体芯片11厚度方向向下弯曲的第一弯曲部27。第二扭折37成为沿与第一弯曲部27相反方向即上方向弯曲的第二弯曲部29。并且,在第二扭折形成工序中,在第二扭折37与毛细管41间形成的直线部38成为从第二弯曲部29沿引脚17表面延伸的直线部31。直线部31的端部成为焊接在引脚17上的直线部侧端部33。
如上所述,在本实施形态中,将引线21焊接在半导体芯片11表面的焊接点13上后,边输送引线21边使得毛细管41朝着引脚17方向和与引脚17相反方向移动,使得引线21形成朝与引脚17相反方向凸出的第一扭折35,朝引脚17方向凸出的第二扭折37,以及与第二扭折37连续的直线部38之后,使毛细管41构成环,将引线21接合到引脚17上,因此,接合时,能使得直线部38成形为沿引脚17表面方向的直线部31,同时,在将直线部31推压在引脚17表面状态下接合引线21。
用上述那样方法接合的引线21,成为直线部31由引脚17沿着半导体芯片11厚度方向支承状态。因此,即使对其他引线21进行接合时施加超声波励振,由于已焊接完的引线21的直线部31可以抑制引线21沿半导体芯片11厚度方向的振动或沿相对引脚17表面垂直方向的振动,具有能抑制已焊接完的引线21因其他引线21的超声波励振引起损伤的效果。
另外,直线部31被推压在引脚17上,因此,即使由于其他引线21在接合时超声波励振,已焊接完的引线21沿引脚17表面方向产生振动场合,该振动能量作为直线部31与引脚17间的摩擦而消耗,即,由于直线部31与引脚17间的摩擦,能抑制沿引脚17表面方向的振动,具有能抑制引线21损伤的效果。
这样,引线21的直线部31被推压在引脚17上,因此,具有可以同时抑制相对引脚17表面垂直方向及沿引脚17表面方向两方向振动的效果。
在本实施形态中,通过如图1至图3所说明那样的整体封装法制造半导体装置10的场合,引脚框12通过带16吸附在焊接台53上,从上方推压在各区段70的外周,即使上述这样的引脚框12的固定状态不佳场合,也能通过直线部31的支承作用以及摩擦力减弱振动,具有以下效果:减弱其他引线21因超声波励振损伤已焊接完的引线21与引脚17的接合部。
下面参照图7至10说明本发明半导体装置的另一实施形态。与上述实施形态相同部分标以相同符号,说明省略。如图7所示,在半导体装置10中,背面贴有带16的引脚框12的岛15上安装有半导体芯片11,其表面上的焊接点13与引脚框12的引脚17间通过引线21相连接。引线21由以下部分形成:通过焊接接合在位于半导体芯片11表面的焊接点13上的压焊球23;挤压部26,压碎从压焊球23向引线21截面积变化的球颈25,挤压在压碎的球颈25上折返的引线21的侧面形成;从挤压部26朝着引脚17延伸沿半导体芯片11厚度方向向下弯曲的第一弯曲部27;朝着与第一弯曲部27相反方向即向上方向弯曲的第二弯曲部29;从第二弯曲部29朝引脚17,沿引脚17表面方向延伸的直线部31;以及与引脚17焊接的直线部侧端部33。
如图8所示,半导体芯片11表面焊接点13上形成的挤压部26由压碎部25a,折返部26a,及平面部26b构成。焊接点13上的压焊球23上,球颈25被压碎,形成压碎部25a,其上面成形为平面状。从该压碎部25a向与引脚17相反侧凸出,引线21被折返,形成折返部26a。与折返部26a连续的引线21侧面朝着压碎部25a被挤压,挤压时,上侧的面因毛细管形成平面状,成为平面部26b。该平面部26b的焊接点13侧的面受压碎部25a的上侧的面挤压。另外,引线21的直线部31和直线部侧端部33的构成与上述参照图5所示的实施形态相同。
引线21的两侧被焊接点侧的压焊球23和引脚17侧的直线部侧端部33这两点固定,挤压部26的焊接点13侧面被压碎部25a挤压,直线部31的引脚侧面朝着引脚17表面被推压。由图9及图10所示那样的焊接工序,通过焊接引线21带来该推压力。
与上述实施形态相同,通过毛细管41对形成在引线21前端的没有图示的初始压焊球实行超声波励振,并将其推压在焊接点13上接合,与此同时,在焊接点13上实行形成压焊球23和球颈25的第一焊接工序。
第一焊接工序后,进行如图9(a)至图9(f)所示那样的挤压部形成工序。在图9(a)至图9(f)中省略引脚17,实际情况下图中右侧是引脚17侧。在挤压部形成工序中,如图9(a)所示,输送引线21同时使得毛细管41上升后,如图9(b)所示,朝与引脚17相反方向移动毛细管41,直到毛细管41的引脚17侧的面部43移至球颈25的上部。此时引线21成为从球颈25朝与引脚17相反方向倾斜的状态。接着,如图9(c)所示,使得毛细管41下降,利用毛细管41的面部43压碎球颈25,在压焊球23上形成压碎部25a。压碎部25a的上面由于被毛细管41的面部43压碎,成为按面部43形状的平面状。另外,引线21朝压碎部25a的与引脚17相反侧弯曲,同时,沿着毛细管41的直孔47的与引脚17相反侧的内面,成为朝焊接点13的垂直方向延伸状态。
接着,如图9(d)所示,再次输送引线21同时提升毛细管41。于是,引线21沿着毛细管41的直孔47直线输出。然后,如图9(e)所示,使得毛细管41朝引脚17方向移动。于是引线21被毛细管41的内倒角部45朝引脚17方向推压,在与压碎部25a连续的弯曲部25b被弯曲。接着,使得毛细管41朝引脚17方向移动,直到毛细管41的位于与引脚17相反侧的面部43移至压焊球23上方的位置。接着,如图9(f)所示,下降毛细管41,将引线21的侧面挤压在压碎球颈25形成的压碎部25a上。通过该引线21的挤压,引线21的弯曲部分朝压碎部25a方向被折返,形成折返部26a。引线21的挤压部26的焊接点13侧因挤压被挤压在压碎部25a的上面,挤压部26的上面因毛细管41的面部43形成平面。在挤压部形成工序结束状态下,毛细管41成为相对焊接点13的接合中心线28偏向引脚17侧的位置。
通过上述那样的接合方法,在焊接点13表面,形成引线21被折返挤压的挤压部26。该挤压部26下面向焊接点13的压焊球23上形成的压碎部25a挤压,沿半导体芯片11的厚度方向或相对焊接点13的垂直方向被支承,同时,因挤压力朝压碎部25a被挤压。
因此,即使其他引线21在接合时实行超声波励振,也能抑制已焊接完的引线21的挤压部26沿半导体芯片11厚度方向的振动或沿相对焊接点13表面垂直方向的振动,因此,具有抑制已焊接完的引线21因其他引线21的超声波励振受到损伤的效果。
另外,挤压部26被挤压在焊接点13上形成的压碎部25a的上面,因此,即使其他引线21接合时因超声波励振,已焊接完的引线21沿焊接点13表面方向产生振动场合,该振动能量可以作为挤压部26下面与压碎部25a上面间的摩擦消耗,即,由于挤压部26下面与压碎部25a上面间的摩擦,能抑制沿焊接点13表面方向的振动,具有能抑制引线21损伤的效果。
这样,引线21挤压部26被挤压在焊接点13上形成的压碎部25a上,因此,具有可以同时抑制两个方向即沿与焊接点13表面垂直方向以及沿焊接点13表面方向振动的效果。
通过上述工序在焊接点13上形成折返引线21的挤压部26后,说明引线21成形,成环,焊接在引脚17的工序。
如图10(a)所示,参照图9说明的挤压部形成工序后,边从毛细管41前端输送引线21的同时提升毛细管41后,实行反向工序,即,使得在上述挤压部形成工序结束时相对焊接点13的接合中心线28偏向引脚17侧的毛细管41朝与引脚17相反方向移动。通过该反向工序,从焊接点13的引脚17侧立起的引线21成为朝着与引脚17相反方向弯曲倾斜形状。另一方面,毛细管41内的引线21保持与焊接点13面大致垂直的方向,因此,在反向工序结束状态的毛细管41前端附近的引线21上,形成朝与引脚17相反方向凸出的弯曲部分。
如图10(b)至图10(d)所示,反向工序之后与上述实施形态相同,进行第一扭折形成工序,第二扭折形成工序。接着,第二扭折形成工序之后,如图10(e)所示进行第二焊接工序。如图10(e)所示,第二扭折形成工序之后,将毛细管41从焊接点13的接合中心线28朝引脚17进行闭环处理。通过该闭环处理,第一扭折35成为第一弯曲部27,第二扭折37成为第二弯曲部29,直线部38成为从第二弯曲部29沿引脚17表面延伸的直线部31,直线部31的端部成为焊接在引脚17上的直线部侧端部33。
如上所述,在本实施形态中,将引线21焊接在半导体芯片11表面的焊接点13上后,使得引线21折返,形成挤压在球颈25的压碎部25a上的挤压部26,输送引线21的同时,使得毛细管41朝引脚17方向以及与引脚17相反方向移动,使得引线21形成朝与引脚17相反方向凸出的第一扭折35,朝引脚17方向凸出的第二扭折37,以及与第二扭折37连续的直线部38之后,将毛细管41进行闭环处理从而接合引线21和引脚17,因此,接合时,直线部38成形为沿引脚17表面方向的直线部31,同时,能使得与直线部31连续的直线部侧端部33作为推压在引脚17表面上状态接合。如上述方法那样接合的引线21,成为直线部31由引脚17沿着半导体芯片11厚度方向进行支承的状态。
在本实施形态中,上述挤压部26的下面被挤压在焊接点13的压焊球23上形成的压碎部25a上,沿半导体芯片11厚度方向或相对焊接点13垂直方向受到支承,同时,通过挤压力可以消耗沿焊接点13面方向的振动能量,换句话说,由于上述挤压部26的下面被挤压在焊接点13的压焊球23上形成的压碎部25a上,沿半导体芯片11厚度方向或相对焊接点13垂直方向受到支承,两者间接合面积增大,摩擦力增大,因此可以抑制引线21在焊接点13侧的振动。而且,与上述实施形态相同,引线21的直线部31沿半导体芯片11的厚度方向或相对引脚17表面垂直方向受到支承,同时,被推压在引脚17上,振动能量能作为直线部31与引脚17间的摩擦消耗,换句话说,直线部31与引脚17间的摩擦能抑制振动,因此,即使在引线21的引脚17侧也能抑制引线21的振动。因此,与上述实施形态相比,可以抑制引线21整体更大的振动,具有能更有效地减弱已焊接完的引线21与焊接点13及引脚17的接合部因其他引线21超声波励振引起损伤的效果。
在本实施形态中,与前面说明的实施形态相同,通过如图1至图3说明那样的整体封装法制造半导体装置10场合,引脚框12通过带16被吸附在焊接台53上,从上方推压各区段70外周,即使这种引脚框12的固定状态不佳场合,由于挤压部26和直线部31的支承作用以及摩擦力,减弱振动,具有能更有效地减弱已焊接完的引线21与焊接点13的接合部以及引线21与引脚17的接合部因其他引线21超声波励振引起损伤的效果。
上面参照附图说明了本发明的实施例,但本发明并不局限于上述实施形态。在本发明技术思想范围内可以作种种变更,它们都属于本发明的保护范围。

Claims (4)

1.一种半导体装置,半导体芯片表面的焊接点与引脚通过引线连接,在与引脚框的半导体芯片安装面相反侧的面粘贴带,进行制造,其特征在于:
该半导体装置包括:
球焊部,引线插入穿通毛细管,从其下端凸出,在该引线前端形成初始压焊球,将该初始压焊球焊接在焊接点上;
引线,从球焊部向引脚延伸,与引脚接合;
引线在球焊后的引线输送工序中,形成朝与引脚相反方向凸出的第一扭折以及朝引脚方向凸出的第二扭折,此后经闭环处理与引脚接合;
引线由以下各部分形成:从焊接点朝引脚延伸、朝半导体芯片厚度方向弯曲的第一弯曲部,朝与第一弯曲部相反方向弯曲的第二弯曲部,从第二弯曲部朝引脚、沿引脚表面方向延伸的直线部,以及焊接在引脚上的直线部侧端部;
直线部的引脚侧面朝引脚表面被推压。
2.一种半导体装置,半导体芯片表面的焊接点与引脚通过引线连接,在与引脚框的半导体芯片安装面相反侧的面粘贴带,进行制造,其特征在于:
该半导体装置包括:
挤压部,引线插入穿通毛细管,从其下端凸出,在该引线前端形成初始压焊球,将该初始压焊球焊接在焊接点上,成为球焊部,压碎形成在球焊部上的球颈,挤压在压碎的球颈上折返的引线侧面形成该挤压部;
引线,从挤压部向引脚延伸并与引脚接合;
引线在挤压部形成后的引线输送工序中,形成朝与引脚相反方向凸出的第一扭折以及朝引脚方向凸出的第二扭折,此后经闭环处理与引脚接合;
引线由以下各部分形成:从挤压部朝引脚延伸、朝半导体芯片厚度方向弯曲的第一弯曲部,朝与第一弯曲部相反方向弯曲的第二弯曲部,从第二弯曲部朝引脚、沿引脚表面方向延伸的直线部,以及焊接在引脚上的直线部侧端部:
直线部的引脚侧面朝引脚表面被推压。
3.一种引线接合方法,系半导体装置的引线接合方法,半导体芯片表面的焊接点与引脚通过引线连接,引线插入穿通毛细管,从其下端突出,在该引线前端形成初始压焊球,将该初始压焊球焊接在焊接点上,形成球焊部,从该球焊部向引脚延伸,形成朝半导体芯片厚度方向弯曲的第一弯曲部,朝与第一弯曲部相反方向弯曲的第二弯曲部,从第二弯曲部朝引脚、沿引脚表面方向延伸的直线部,以及焊接在引脚上的直线部侧端部,直线部的引脚侧面朝引脚表面被推压,在与引脚框的半导体芯片安装面相反侧的面粘贴带,进行制造,其特征在于,该引线接合方法包括:
第一焊接工序,引线插入穿通毛细管,从其下端突出,在该引线前端形成初始压焊球,将该初始压焊球推压至焊接点上进行接合;
反向工序,边输送引线,边使得毛细管上升后,使得毛细管朝与引脚相反方向移动;
第一扭折形成工序,边输送比上述反向工序长的引线,边使得毛细管上升后,使得毛细管朝引脚方向移动直到超过焊接点的接合中心的位置,在引线上形成朝与引脚相反方向凸出的第一扭折;
第二扭折形成工序,边输送引线,边使得毛细管上升后,使得毛细管朝与引脚相反方向移动直到焊接点的接合中心位置,形成朝引脚方向凸出的第二扭折以及与该第二扭折连续的直线部;
第二焊接工序,使得毛细管朝引脚进行闭环处理,将毛细管推压在引脚上,使引线与引脚接合。
4.一种引线接合方法,系半导体装置的引线接合方法,半导体芯片表面的焊接点与引脚通过引线连接,引线插入穿通毛细管,从其下端突出,在该引线前端形成初始压焊球,将该初始压焊球焊接在焊接点上,形成球焊部,在球焊部上形成球颈,引线包括压碎所述球颈、挤压在压碎的球颈上折返的引线侧面形成的挤压部,从该挤压部向引脚延伸、朝半导体芯片厚度方向弯曲的第一弯曲部,朝与第一弯曲部相反方向弯曲的第二弯曲部,从第二弯曲部朝引脚、沿引脚表面方向延伸的直线部,以及焊接在引脚上的直线部侧端部,直线部的引脚侧面朝引脚表面被推压,在与引脚框的半导体芯片安装面相反侧的面粘贴带,进行制造,其特征在于,该引线接合方法包括:
第一焊接工序,引线插入穿通毛细管,从其下端突出,在该引线前端形成初始压焊球,将该初始压焊球推压至焊接点上进行接合;
挤压部形成工序,输送引线,同时边提升毛细管,边使得毛细管朝与引脚相反方向移动后,降低毛细管,用毛细管面部压碎球颈,再次输送引线,同时边提升毛细管,边朝引脚方向移动后,再次降低毛细管,将引线侧面推压在被压碎的球颈上形成挤压部;
反向工序,边输送引线,边使得毛细管上升后,使得毛细管朝与引脚相反方向移动直到超过焊接点的接合中心的位置;
第一扭折形成工序,边输送比上述反向工序长的引线,边使得毛细管上升后,使得毛细管朝引脚方向移动直到超过焊接点的接合中心的位置,在引线上形成朝与引脚相反方向凸出的第一扭折;
第二扭折形成工序,边输送引线,边使得毛细管上升后,使得毛细管朝与引脚相反方向移动直到焊接点的接合中心位置,形成朝引脚方向凸出的第二扭折以及与该第二扭折连续的直线部;
第二焊接工序,使得毛细管朝引脚进行闭环处理,将毛细管推压在引脚上,使引线与引脚接合。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013049965A1 (en) * 2011-10-08 2013-04-11 Sandisk Semiconductor (Shanghai) Co., Ltd. Dragonfly wire bonding

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4625858B2 (ja) * 2008-09-10 2011-02-02 株式会社カイジョー ワイヤボンディング方法、ワイヤボンディング装置及びワイヤボンディング制御プログラム
US8192048B2 (en) * 2009-04-22 2012-06-05 3M Innovative Properties Company Lighting assemblies and systems
US8384228B1 (en) * 2009-04-29 2013-02-26 Triquint Semiconductor, Inc. Package including wires contacting lead frame edge
JP2012004464A (ja) * 2010-06-18 2012-01-05 Toshiba Corp 半導体装置、半導体装置の製造方法及び半導体装置の製造装置
JP5917817B2 (ja) * 2011-03-25 2016-05-18 シチズン電子株式会社 ワイヤーボンディング構造
JP6002461B2 (ja) * 2011-08-26 2016-10-05 ローム株式会社 半導体装置および電子デバイス
KR101464189B1 (ko) * 2013-04-17 2014-11-21 대우전자부품(주) 헤비 와이어 본딩 방법
JP2018137342A (ja) * 2017-02-22 2018-08-30 株式会社村田製作所 半導体装置及びその製造方法
KR102460014B1 (ko) 2018-08-24 2022-10-26 삼성전자주식회사 반도체 패키지
CN110491793B (zh) * 2019-08-26 2020-03-13 广东工业大学 一种三维快速引线成弧方法及装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2531099B2 (ja) * 1993-07-13 1996-09-04 日本電気株式会社 ワイヤ―ボンディング方法
JP3377747B2 (ja) 1998-06-23 2003-02-17 株式会社新川 ワイヤボンディング方法
JP2005116915A (ja) 2003-10-10 2005-04-28 Sanyo Electric Co Ltd 半導体装置
JP3946730B2 (ja) 2004-04-26 2007-07-18 株式会社カイジョー ボンディングワイヤのループ形状及びそのループ形状を備えた半導体装置並びにワイヤボンディング方法
WO2006018671A1 (en) * 2004-08-19 2006-02-23 Infineon Technologies Ag Mixed wire semiconductor lead frame package
CN101675510B (zh) * 2007-05-16 2011-12-14 库利克和索夫工业公司 金属线接合方法和接合力校准

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013049965A1 (en) * 2011-10-08 2013-04-11 Sandisk Semiconductor (Shanghai) Co., Ltd. Dragonfly wire bonding

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