JP2012004464A - 半導体装置、半導体装置の製造方法及び半導体装置の製造装置 - Google Patents
半導体装置、半導体装置の製造方法及び半導体装置の製造装置 Download PDFInfo
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- JP2012004464A JP2012004464A JP2010139998A JP2010139998A JP2012004464A JP 2012004464 A JP2012004464 A JP 2012004464A JP 2010139998 A JP2010139998 A JP 2010139998A JP 2010139998 A JP2010139998 A JP 2010139998A JP 2012004464 A JP2012004464 A JP 2012004464A
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Abstract
【解決手段】実施形態によれば、第1半導体素子5と、第1電極10と、第2電極20と、ボール部30と、ワイヤ40と、を備えた半導体装置が提供される。第1電極は、第1半導体素子5に電気的に接続される。ボール部は、第1電極の上に設けられる。ワイヤは、ボール部と第2電極とを接続する。ワイヤの第2電極とは反対側の端の折り返し部分41の厚さ41tは、ワイヤの径40dよりも薄い。
【選択図】図1
Description
なお、図面は模式的または概念的なものであり、各部分の厚みと幅との関係、部分間の大きさの比率などは、必ずしも現実のものと同一とは限らない。また、同じ部分を表す場合であっても、図面により互いの寸法や比率が異なって表される場合もある。
なお、本願明細書と各図において、既出の図に関して前述したものと同様の要素には同一の符号を付して詳細な説明は適宜省略する。
図1(a)及び図1(b)は、第1の実施形態に係る半導体装置の構成を例示する模式的断面図である。
すなわち、図1(b)は、半導体装置の概要を例示しており、図1(a)は、図1(b)の1B部分を拡大して例示している。
図2は、第1の実施形態に係る半導体装置の構成を例示する模式的平面図である。
図2は、図1(b)の1B部分を拡大して例示している。
第1電極10は、半導体素子5に電気的に接続される。半導体素子5には、例えばメモリなどの半導体チップが用いられる。ただし、実施形態はこれに限らず、半導体素子5には任意の半導体チップを用いることができる。
ワイヤ40は、ボール部30と第2電極20とを接続する。すなわち、ワイヤ40の一端は、ボール部30と接し、ワイヤ40の他端は、第2電極20と接する。
ボール部30及びワイヤ40には、例えば金などの材料が用いられる。
すなわち、図3(a)は模式的断面図であり、図3(b)は模式的平面図である。
図3(a)及び図3(b)に表したように、参考例の半導体装置119においては、ワイヤ40の第2電極20とは反対側の端の2重折り返し部49の厚さ49tは、ワイヤ40の径40dよりも厚い。半導体装置119における2重折り返し部49は、ワイヤ40のうちでボール部30からX1方向に向けて延在する部分と、ワイヤ40のうちでX1方向の端から折り返してX2方向に向けて延在する部分と、が重なった部分である。このため、半導体装置119における2重折り返し部49の厚さ49tは、ワイヤ40の径40dの約2倍程度の厚さである。
図4(a)〜図4(f)、図5(a)〜図5(f)、図6(a)〜図6(f)、及び、図7(a)〜図7(e)は、第1の実施形態に係る半導体装置の製造方法を例示する模式図である。
図4(a)、図4(c)、図4(e)、図5(a)、図5(c)、図5(e)、図6(a)、図6(c)、及び、図6(e)は、ステップSP01〜SP09の各工程におけるキャピラリ60の状態及び動作を例示している。図4(b)、図4(d)、図4(f)、図5(b)、図5(d)、図5(f)、図6(b)、図6(d)、及び、図6(f)は、ステップSP01〜SP09の各工程におけるキャピラリ60、第1電極10、ボール部30及びワイヤ40の状態を例示している。
図7(a)〜図7(e)は、ステップSP10〜SP14におけるキャピラリ60の状態及び動作を例示している。なお、図4(d)には、断面図の他に、ボール部30の平面図も描かれている。
台座部31の径31dは、例えば50μm〜60μmであり、上部32の径32dは、例えば台座部31の径31dよりも5μm〜10μm程度小さくなる。ただし、実施形態はこれに限らず、台座部31の径31d及び上部32の径32dは任意である。
その後、図7(b)に表したように、キャピラリ60を、第1電極10に対して相対的にX1方向に移動させる(ステップSP11)。
その後、図7(c)に表したように、キャピラリ60を、さらに上昇させる(ステップSP12)。
その後、図7(d)に表したように、キャピラリ60を第2電極20(図示しない)へ向けてX2方向に沿って移動させる(ステップSP13)。
そして、図7(e)に表したように、キャピラリ60を第2電極20に向けて近接させ、ワイヤ40のボール部30とは反対側の端を第2電極20に接続する(ステップSP14)。
これにより、図1(a)、図1(b)及び図2に例示した半導体装置110が製造される。
すなわち、図8(a)は、実施形態に係る半導体装置110におけるキャピラリ60の動きを模式的に例示し、図8(b)は、参考例の半導体装置119におけるキャピラリ60の動きを模式的に例示している。
図8(a)に表したように、半導体装置110の製造においては、キャピラリ60を、第1電極10に対して相対的にX1方向に移動させた(ステップSP04)後に、キャピラリ60を降下させて第2電極側先端62によるワイヤ40の変形(ステップSP05)が実施される。さらに、キャピラリ60を第1電極10に対して相対的にX2方向に移動させた(ステップSP07)後に、キャピラリ60を降下させて第1電極側先端61によるワイヤ40の変形(ステップSP08)が実施される。そして、その後、ワイヤ40が第2電極20に接続される(ステップSP14)。上記のキャピラリ60のX1方向に向けた移動、及び、X2方向に向けた移動の距離は、ボール部30の範囲内である。このように、半導体装置110の製造においては、1回目のワイヤ40の押しつぶし(ステップSP05)と、2回目のワイヤ40の押しつぶし(ステップSP08)と、が実施される。
図9(a)及び図9(b)は、実施例に係る半導体装置の構成を例示する模式図である。
すなわち、図9(a)は模式的断面図であり、図9(b)は模式的斜視図である。図9(b)は、分かり易いように、実施例に係る半導体装置111の走査電子顕微鏡(SEM)写真像を基に、各要素の外形を線で描いたものである。
図9(a)及び図9(b)に表したように、本実施形態に係る実施例の半導体装置111においては、半導体素子5に電気的に接触する第1電極10として、半導体素子5の上に設けられたパッド電極11が用いられている。そして、パッド電極11とボール部30との間に下層接続部14が設けられている。下層接続部14は、パッド電極11に接続された下層ワイヤ13と、下層ワイヤ13の下層終端部12と、を含む。下層ワイヤ13は、パッド電極11と、パッド電極11よりもX1方向に設けられている別の電極(図示しない)と、を接続している。
図10は、図9(b)を拡大したものである。
さらに、境界の線Ldは、ボール部30の凸部30cの側面とワイヤ40との境界に対応する。
図11(a)〜図11(d)は、実施例に係る半導体装置の製造方法を例示する模式図である。
すなわち、図11(a)、図11(b)、図11(c)及び図11(d)は、ステップSP05、SP06、SP07及びSP08におけるワイヤ40の状態を模式的に示している。
第2の実施の形態においては、積層された半導体チップが用いられる。そして、ワイヤ40は、積層された半導体チップどうしを電気的に接続する。
図12(a)に表したように、本実施形態に係る半導体装置120は、既に説明した第1半導体素子(半導体素子5)と、第1電極10と、第2電極20と、ボール部30と、ワイヤ40と、に加え、第2半導体素子6(半導体チップ)をさらに備える。第2半導体素子6には、例えばメモリなどの半導体チップが用いられる。ただし、実施形態はこれに限らず、第2半導体素子6には任意の半導体チップを用いることができる。
ワイヤ40は、第1電極10の上方と、第2電極20の上方と、の間において、第1半導体素子(半導体素子5)の主面及び第2半導体素子6の主面に対して実質的に平行である。
すなわち、半導体装置121は、下層ワイヤ13をさらに備える。下層ワイヤ13の一端(下層終端部12)は、ボール部30と第1電極10との間に接続される。下層ワイヤ13は、第1電極10から、第2電極20から第1電極10に向かう方向(X1方向)に向けて延出する。
図13(a)〜図13(d)は、実施例に係る半導体装置の構成を例示する模式図である。
図13(a)は、実施例に係る半導体装置122の構成の概要を例示する模式的断面図であり、図13(b)は、図13(a)の一部13Aを拡大した模式的斜視図であり、図13(c)は、図13(b)の一部13Bを拡大した模式的斜視図であり、図13(d)は、図13(c)の一部13Cを拡大した模式的斜視図である。なお、図13(b)、図13(c)及び図13(d)は、半導体装置122のSEM写真像を基に、各要素の外形を描いたものである。
また、図13(b)に表したように、下層ワイヤ13の第1電極10に接続された部分から延出する部分は、第1電極10の主面に対して実質的に平行である。
図14(a)は、本実施形態に係る別の実施例の半導体装置123の一部を拡大した模式的斜視図であり、図14(b)は、図14(a)の一部14Aを拡大した模式的斜視図である。図14(a)及び図14(b)は、半導体装置123のSEM写真像を基に、各要素の外形を描いたものである。
図15に表したように、本実施形態に係る別の半導体装置124は、第1半導体素子(半導体素子5)が基板9の上に設けられ、その上に第2半導体素子6が積層され、その上に第3〜第9半導体素子6a〜6gが順次積層されている。そして、半導体素子の相互がワイヤ40によって接続されている。
このように、半導体装置において、設けられる半導体素子の数は、任意である。
第3の実施形態は、半導体装置の製造方法である。
図16は、第3の実施形態に係る半導体装置の製造方法を例示するフローチャート図である。
図16に表したように、半導体素子5に電気的に接続された第1電極10の上方に配置されたキャピラリ60を下降させて、キャピラリ60に保持されたワイヤ40の先端のボール30aを第1電極10に押し付けて、第1電極10上にワイヤ40に接続されたボール部を形成する(ステップS110)。
すなわち、ステップSP01及びステップSP02を実施する。
すなわち、ステップSP03〜ステップSP05を実施する。ステップS120(ステップSP05)において、ボール部30を第1電極10に押し付けて、ボール部30も変形させても良い。
すなわち、ステップSP06〜ステップSP08を実施する。ステップS130(ステップSP08)において、ボール部30を第1電極10に押し付けて、ボール部30も変形させても良い。
すなわち、例えば、ステップSP09〜ステップSP14を実施する。
第4の実施形態は、半導体装置の製造装置である。
図4(a)に表したように、本実施形態に係る製造装置は、ワイヤ40を供給するキャピラリ60と、キャピラリ60の位置を制御する制御部80と、を備える。
また、各具体例のいずれか2つ以上の要素を技術的に可能な範囲で組み合わせたものも、本発明の要旨を包含する限り本発明の範囲に含まれる。
Claims (7)
- 第1半導体素子と、
前記第1半導体素子に電気的に接続された第1電極と、
第2電極と、
前記第1電極の上に設けられたボール部と、
前記ボール部と前記第2電極とを接続するワイヤと、
を備え、
前記ワイヤの前記第2電極とは反対側の端の折り返し部分の厚さは、前記ワイヤの径よりも薄いことを特徴とする半導体装置。 - 前記折り返し部分の前記第2電極とは反対の側の端は、前記ボール部の前記第2電極とは反対の側の端よりも前記第2電極に近いことを特徴とする請求項1記載の半導体装置。
- 前記ワイヤは、前記ワイヤの前記ボール部の上方の部分に設けられた凹部を有し、
前記ワイヤの前記ボール部に近接した部分は、上方に向けて延出していることを特徴とする請求項1または2に記載の半導体装置。 - 前記第1半導体素子の前記第1電極が設けられる側の主面に積層された第2半導体素子をさらに備え、
前記第2電極は、前記第2半導体素子に電気的に接続され、
前記ワイヤは、前記第1電極の上方と、前記第2電極の上方と、の間において、前記第1の主面及び前記第2半導体素子の主面に対して実質的に平行であることを特徴とする請求項1〜3のいずれか1つに記載の半導体装置。 - 一端が前記ボール部と前記第1電極との間に接続され、前記第1電極から、前記第2電極から前記第1電極に向かう方向に向けて延出する下層ワイヤをさらに備えたことを特徴とする請求項4記載の半導体装置。
- 半導体素子に電気的に接続された第1電極の上方に配置されたキャピラリを下降させて、前記キャピラリに保持されたワイヤの先端のボールを前記第1電極に押し付けて、前記第1電極上に前記ワイヤに接続されたボール部を形成し、
前記キャピラリを上昇させて前記キャピラリを第2電極から前記第1電極に向かう第1方向に向けて移動させた後に、前記キャピラリの前記第2電極の側の第2電極側先端で、前記ワイヤを前記第1電極に向けて加圧して前記ワイヤを変形させることにより、前記ワイヤの径よりも細い径を有する部分を形成し、
前記キャピラリを上昇させて前記キャピラリを前記第1電極から前記第2電極に向かう第2方向に向けて移動させた後に、前記キャピラリの前記第2電極側先端に対向する第1電極側先端で前記ワイヤを前記第1電極に向けて加圧して前記ワイヤを変形させて、前記ワイヤの前記第2電極とは反対の端に、前記部分に基づく、前記ワイヤの前記径よりも薄い厚さを有する折り返し部分を形成し、
前記ワイヤの前記ボール部とは反対側の端を前記第2電極に接続することを特徴とする半導体装置の製造方法。 - ワイヤを供給するキャピラリと、
前記キャピラリの位置を制御する制御部と、
を備え、
前記制御部は、
半導体素子に電気的に接続された第1電極の上方に前記キャピラリを配置した後、前記キャピラリを下降させて、前記キャピラリに保持された前記ワイヤの先端のボールを前記第1電極に押し付けて、前記第1電極上に前記ワイヤに接続されたボール部を形成し、
前記キャピラリを上昇させて前記キャピラリを第2電極から前記第1電極に向かう第1方向に向けて移動させた後に、前記キャピラリの前記第2電極の側の第2電極側先端で、前記ワイヤを前記第1電極に向けて加圧して前記ワイヤを変形させることにより、前記ワイヤの径よりも細い径を有する部分を形成させ、
前記キャピラリを上昇させて前記キャピラリを前記第1電極から前記第2電極に向かう第2方向に向けて移動させた後に、前記キャピラリの前記第2電極側先端に対向する第1電極側先端で、前記ワイヤを前記第1電極に向けて加圧して前記ワイヤを変形させて、前記ワイヤの前記第2電極とは反対の端に、前記部分に基づく、前記ワイヤの前記径よりも薄い厚さを有する折り返し部分を形成させ、
前記ワイヤの前記ボール部とは反対側の端を前記第2電極に接続させることを特徴とする半導体装置の製造装置。
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TW100109462A TWI484613B (zh) | 2010-06-18 | 2011-03-18 | 半導體裝置、半導體裝置之製造方法及半導體裝置之製造設備 |
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