CN101611484A - 无引脚半导体封装及其制造方法 - Google Patents

无引脚半导体封装及其制造方法 Download PDF

Info

Publication number
CN101611484A
CN101611484A CNA2006800520635A CN200680052063A CN101611484A CN 101611484 A CN101611484 A CN 101611484A CN A2006800520635 A CNA2006800520635 A CN A2006800520635A CN 200680052063 A CN200680052063 A CN 200680052063A CN 101611484 A CN101611484 A CN 101611484A
Authority
CN
China
Prior art keywords
pin
nead
frame
framework
semiconductor dice
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2006800520635A
Other languages
English (en)
Other versions
CN101611484B (zh
Inventor
R·S·圣安东尼奥
A·苏巴迪奥
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Interconnect Technology Ltd
Original Assignee
Advanced Interconnect Technology Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Interconnect Technology Ltd filed Critical Advanced Interconnect Technology Ltd
Publication of CN101611484A publication Critical patent/CN101611484A/zh
Application granted granted Critical
Publication of CN101611484B publication Critical patent/CN101611484B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

一种封闭半导体单元片(40)的封装(50)，通过以下步骤制造。首先，提供导电框架。这个框架具有多个布置成矩阵形式的引脚框架(14)，每个引脚框架(14)具有多个从中心孔向外延伸的间隔引脚(16)。该导电框架进一步包括多个连棒，其连接相邻的引脚框架(14)的外端部分。其次，在连棒中形成凹槽以便在相邻引脚框架(14)的外端部分之间形成厚度减小的部分。第三，将半导体单元片(40)电耦合(42)到所述引脚(16)的内部部分。第四，将框架和半导体单元片(40)密封到模塑料(46)中。最后，沿着凹槽切割模塑料(46)和框架以便形成被切单的半导体封装(50)，其具有高度大于厚度减小部分的高度的外引脚部分。

Description

无引脚半导体封装及其制造方法
技术领域
[0001]本发明涉及无引脚半导体封装及制造此类封装的方法。更特别地，本发明涉及制造引脚毛边(lead burr)减少且焊料填角(solder fillet)得到改善的无引脚半导体封装的方法。
背景技术
[0002]半导体器件封装提供对一个或多个集成电路器件(其被称为半导体单元片(semi conductor die)，封闭在封装内部)的环境保护。半导体单元片具有通过引线接合(wire bonds)、胶带接合(tapebonds)等电互连到引脚框架或内插板的内引脚部分的输入/输出(I/O)焊盘。引脚框架或内插板的相对的外引脚部分电互连到印刷电路板上的电路、挠性电路或其它外电路。高分子模压树脂封闭半导体单元片和引脚框架或内插板的至少内引脚部分。
[0003]在引脚框架或内插板的外引脚末端在封装体的一个面处终止且未延伸超过封装覆盖区(package footprint)时，该封装称为“无引脚”或“没有引脚”半导体封装。传统无引脚封装包括具有环绕正方形封装的底面周边设置的四组引脚的四方扁平无引脚(QFN)封装和具有设置在封装底部的相对侧的两组引脚的双扁平无引脚(DFN)封装。
[0004]为了促进某些有引脚或无引脚半导体封装的制造，以片状形式提供引脚框架矩阵。这样的矩阵称为框架。在制造期间，将半导体单元片附着于设置在由引脚框架的内引脚限定的孔内的单元片焊盘。随后将该单元片电互连到内引脚末端。在将单元片附着于每个焊盘并电互连到构成框架的每个引脚框架时，用模压树脂密封整个组件。模压树脂固化或变硬之后，通过被称为切单(singulation)的工艺将各个封装与密封的框架分开。
[0005]切单的一种方法被称为锯割切单(saw singulation)。用锯切开模压树脂和金属引脚框架。由于模压树脂相对较硬，金属引脚框架相对较软，所以锯片必须切开不相似的材料，而且无法优化锯片设计以适用于每种材料。锯切引起的金属碎屑粘附于锯片，使切割面变形并降低锯片的使用寿命。引脚框架的不完全切割导致毛边的形成。毛边可能从一个外引脚端延伸到间隔很近的相邻外引脚端，导致短路。
[0006]授予Ikenaga等人的美国专利No.6,744,118中公开一种克服锯割切单中的困难的方法。参照图1，Ikenaga等人公开了具有沿锯切轨迹(saw track)104或104’设置的厚度减小部分102的引脚框架100。从一侧部分地蚀刻该引脚框架以便形成厚度减小部分102。一侧蚀刻在本领域中称为“半蚀刻”。参考文献公开锯片的宽度不能等于厚度减小部分的宽度，因为沿着蚀刻部分的厚度有变化，将无法顺利切割。因此，选用的锯片宽度要大于厚度减小部分的宽度(锯切轨迹104’)或者小于厚度减小部分的宽度(锯切轨迹104)。通过锯切轨迹104’，碎料形成残余物和碎屑形成的问题虽然得到缓解，但仍然是问题。
[0007]选择锯切轨迹104减少必须用锯片切割的金属的量，减少锯片上金属碎屑的积聚，还减少形成的毛边的数量。图2示出这种方法的缺点。引脚108外缘的一部分106从模压塑料封装体的周边110处凹陷，这种状态称为“缩回(pull-back)”。缩回导致与印刷电路板112接触的面积减小，影响安装完整性。此外，焊料填角114不延伸到封装周边110，造成检验困难。更进一步地，引脚底部的表面面积115被减小。在装配过程中，引脚并排布置并由粘接胶带支撑。引线接合工艺在接合金质接合引线时向引脚施加力。如果不控制这个力，引脚将弯曲。由于这个能被施加于“缩回”引脚的力受到限制，因此可以用于引线接合的金线的直径也受到限制。
[0008]授予Jeong等人的美国专利No.6,605,865中公开锯割切单的另一种方法。如图3所示，美国专利6,605,865公开具有引脚框架118的封装116，该引脚框架118具有厚度减小的突出部分120。用冲压机剪切表面122，从而将封装切单。但是，突出部分的减小的厚度降低引脚的稳定性，造成引线124的接合更加困难。剪切将应力引入引脚和封装，其可能由于导致分层或微裂纹而影响可靠性。
[0009]因此，还需要一种没有上述缺点的制造无引脚半导体封装的方法并且还需要改进无引线半导体封装。
发明内容
[0010]依照本发明的第一实施方案，提供了一种用于半导体封装的框架。该框架包括布置成矩阵形式并通过连棒互连的多个引脚框架。每个引脚框架包括引脚并且连棒将相邻引脚框架的引脚彼此互连。连棒具有布置在相邻引脚框架的引脚之间的凹槽，减少切单期间要用锯片切割的金属的量。
[0011]依照本发明的第二实施方案，提供了一种用于半导体封装的框架，其具有布置成矩阵形式并通过连棒互连的多个引脚框架。将半导体单元片安装在由各个引脚框架的内引脚端限制范围的单元片焊盘上，随后用模压树脂密封组件。然后沿着连棒切割模制组件以便切单单独的半导体封装。每个引脚框架包括引脚并且连棒将相邻引脚框架的引脚彼此互连。连棒在每个引脚框架相邻引脚之间具有厚度减小部分，使得在切单之后，暴露在半导体封装侧面上的部分引脚具有比厚度减小的部分大的剖面高度。
[0012]依照本发明的第三实施方案，提供了一种制造半导体封装的方法，其包括的步骤有：提供具有布置成矩阵形式并通过连棒互连的多个引脚框架的框架，其中每个引脚框架具有多个引脚并且连棒将相邻引脚框架的引脚彼此互连；在每个引脚框架的相邻引脚之间形成连棒中的凹槽以便形成厚度减小的部分；将半导体单元片电学连接到各个引脚框架的内引脚；将引脚框架和半导体单元片用模塑料共同密封；以及沿着连棒切割模塑料和框架以便将单独的半导体封装切单，其中暴露在各个半导体封装的侧面上的部分引脚具有比厚度减小部分大的剖面高度。
[0013]本发明的一个多个实施方案的细节在附图和以下说明中阐述。根据说明书、附图和权利要求，本发明的其它目的、特征和优点是显而易见的。
附图说明
[0014]图1是切单之前现有技术中已知的引脚框架矩阵的一部分横截面图。
[0015]图2是来自图1中框架矩阵的切单之后半导体封装的外引脚部分的横截面图。
[0016]图3是现有技术中已知的凸出厚度减小的外引脚部分的半导体封装的横截面图。
[0017]图4是示出用于切单的锯线的本发明的框架的局部透视图。
[0018]图5是图4的框架的局部剖面图。
[0019]图6是图4的框架的引脚框架元件的仰视图。
[0020]图7是图6的框架的引脚框架元件的俯视图。
[0021]图8是图4的框架的示意图。
[0022]图9A-9G绘出连续制造步骤期间本发明的半导体器件封装。
[0023]图10是安装到印刷电路板的本发明的半导体封装的局部横截面图。
[0024]图11示出本发明的可选半导体封装，其中通过倒装芯片接合将半导体单元片连接到引脚框架。
具体实施方式
[0025]图4是本发明的框架10的局部透视图，图5是其局部剖面图。框架10由诸如铜或铜基合金的导电材料形成。对于铜基，意味着合金包含的铜按重量计高于50％。锯切轨迹12示出锯片22通过以便分开相邻引脚框架14、14’的路径。每个引脚框架14包括引脚16，相邻引脚框架的引脚16’通过连棒18彼此互连。如下文所述，连棒18提供有减少锯片在切单过程中必须切割的金属的量的凹槽20。顶侧蚀刻剖面可以选择性地包含底切(undercut)21，引脚16、16’在锯切之前在该处连接。这个底切21减少将在锯切过程中除去的金属的量并进一步将侧面毛边的形成减到最少。
[0026]图6示出引脚框架14的仰视图，其为框架的元件，而图7是引脚框架14的俯视图。引脚框架14包括多个引脚16。单元片焊盘23布置在由引脚16的内端限定的中心孔中。从单元片焊盘23的拐角延伸的是系棒(tie bar)24。系棒24通常作为直立的棒形成，其具有从与单元片焊盘23相对的末端伸出的突出体26。如前所述，布置在引脚框架14边缘周围的是将相邻引脚框架的引脚16’与引脚16互连的连棒18。锯切轨迹12通常在垂直于引脚长轴的方向上沿着连棒18延伸。
[0027]每个引脚16具有布置在引脚底面上的第一引脚表面28和引脚顶面上的接合位置(bond site)30。引脚16被彼此隔开并与单元片焊盘23隔开以便使引脚与单元片焊盘电学隔离。在示出的实施方案中，引脚框架14有八个引脚16，布置在单元片焊盘23四边中的每个边上。引脚框架14的厚度减小的部分由图6中的交叉阴影线示出。例如，可以减小引脚16末端部分和单元片焊盘23周边的厚度以便形成帮助将单元片焊盘23和引脚16固定在模压树脂中的凸缘32、34。此外，连棒18提供有布置在引脚框架14的相邻引脚16之间的厚度减小的部分(凹槽)20。
[0028]将认识到引脚的数目和定位可以根据特殊应用的需要而改变。例如，引脚框架可以包括两组布置在单元片焊盘相对侧的引脚，供双、无引脚半导体封装使用。此外，将认识到对于某些封装芯片结构，例如对于下文中讨论的图11的倒装结构，可以除去单元片焊盘。
[0029]图8是框架10的示意图。该框架包括布置成矩阵的多个引脚框架14。示出的矩阵是引脚框架的8×8矩阵，但框架10可以包括任何所需阵列型式的任何适当数目的引脚框架。
[0030]图9A-9G绘出连续制造步骤期间本发明的半导体器件封装50。在图9A中，引脚框架14通过连棒18互连到相邻引脚框架14’。形成引脚框架14、14’阵列的导电材料片具有剖面高度“h”，其等于用于单元片焊盘23和引脚16的所需剖面高度。虽然图9A示出两个互连引脚框架，但可以预期对于多封装组件，可以互连任何数目的引脚框架。
[0031]通过诸如压印、化学蚀刻、激光烧蚀等任何已知工艺形成引脚框架14的部件，包括单元片焊盘23、引脚16、连棒18和系棒24。这些部件的每一个中厚度减小的区域通过诸如化学蚀刻或激光烧蚀的受控减成法形成。例如，旨在形成引脚16的接触表面的每个表面、连棒18的全厚部分和单元片焊盘23的中心部分可以涂覆化学抗蚀剂，剩余表面暴露于适当的蚀刻剂经历将暴露区域的厚度减小到所需的减小的厚度“t”的有效时间。连棒、单元片焊盘的凸缘和引脚的锯线部分及系棒需要有典型地减小的厚度。减小的厚度“t”可以在剖面高度“h”的厚度的30％与70％之间，更优选在剖面高度的40％与60％之间。
[0032]参照图9B，形成引脚框架14之后，引脚16的接合位置30和单元片焊盘23的接合位置36可以被镀有便于与接合引线的接合的材料。例如，接合位置30、36可以镀镍、钯、金、银及其它引线可接合金属或金属合金中的一种或多种。
[0033]参照图9C，在引线接合的制备中，将每个引脚16的底面28和单元片焊盘23的底面固定到表面38。在示出的实施方案中，表面38在粘合带上形成。其次，用例如焊料、环氧树脂、双面胶带等传统粘接材料将半导体单元片40固定到单元片焊盘。
[0034]参照图9D，在将单元片40固定到单元片焊盘23之后，在单元片40表面上的I/O焊盘44与引脚上的接合位置30之间连接接合引线42。在一些实施方案中，接合引线42还通过接合位置36将I/O焊盘电互连到单元片焊盘。引线接合可以借助于超声波接合(其中应用压力与超声波振动突发(burst)的结合来形成冶金学冷焊)、热压接合(其中应用压力与提高的温度的结合来形成焊接)、或热超声波接合(其中用压力、提高的温度与超声波突发的结合来形成焊接)。接合中使用的引线42优选为金、金基合金、铝或铝基合金。作为引线接合的替换，可以使用胶带自动接合。
[0035]连棒18的厚度减小部分不影响引线接合期间的引脚16稳定性，这是因为触点30与连棒18的一部分相邻，该部分的厚度等于引脚16的全剖面高度“h”。这与现有技术中的布置不同，在现有技术布置中，相邻引脚框架的触点之间材料的去除减小触点与表面38之间的接触面积，造成引线接合期间引脚的稳定性相对较差。
[0036]参照图9E，在完成引线接合之后，用模塑料(moldingcompound)46密封单元片40、引脚框架14和接合引线42。通过诸如传递模塑或注射模塑的任何适当技术将模塑料布置在封装部件周围。模塑料46是诸如高分子模压树脂的电绝缘材料，例如环氧树脂。高分子模压树脂的典型流动温度在约250℃与约300℃之间。作为替换，模塑料可以是低温耐热玻璃合成物。
[0037]系棒24和凸缘34的减小的厚度允许在系棒24和凸缘34下面容纳模塑料46，这允许系棒和凸缘34将单元片焊盘23机械地锁定在模塑料46中并帮助将单元片焊盘保持在封装中。同样，凸缘32将触点16锚定在封装中。
[0038]参照图9F，模塑之后，除去表面38，并且触点16的底面28可以镀有便于与外电路的电学互连的材料。例如，底面28可以镀有镍、钯、金、银或其它适当材料中的一种或多种。
[0039]参照图9G，然后用锯割切单或其它适当工艺切割模塑料46和连棒18以便将相邻引脚框架14、14’分开并形成单独的半导体封装。如图4和5中所示，由凹槽20形成的连棒18的厚度减小部分减少了切单引脚框架时锯片22必须通过的金属的量。此外，凹槽20形成引脚16的暴露表面28之间的空间。即使引脚16在切单后镀敷，这个空间也降低或消除了毛边或污迹导致引脚之间短路的可能性。
[0040]返回参照图9G，每个半导体封装50具有底部(第一)封装面52、相对的顶部(第二)封装面54和在底部封装面52与顶部封装面54之间延伸的封装侧面56。封装面一部分是由模塑料46形成。每个引脚16的底面和单元片焊盘22的底面暴露在封装50的底面52上。
[0041]封装50可以电耦合到外电路，例如印制电路、挠性电路、另一个半导体封装、试验器件或其它元件或器件。如图10中所示，封装50可以焊接到印刷电路板60。有利的是，暴露在封装50的侧面56处的引脚16的一部分是引脚16的全剖面高度，实现板安装期间的全高度焊料填角62。图2和3的现有技术的填角与图10的填角的比较显示，本发明的引脚16在封装50的底面52和侧面56上具有比通过现有技术实现的更大的接触面积(暴露面积)，这改善了板安装的完整性。此外，与填角可见性缺乏或降低的现有技术填角的情况相比，本发明的触点16提供更具可见性的焊料填角62，使检验变得更容易。
[0042]参照图11，在本发明的可选实施方案中，通过倒装芯片接合，将包括集成电路器件40的半导体器件封装66连接到引脚框架14。除了已经除去图9的单元片焊盘23和引线42并且通过焊接等将芯片上的I/O焊盘电互连到引线16上的接合位置30之外，这些封装与图9所示的封装基本类似，并且可以用相同的方法形成。
[0043]一般而言，本发明的框架包含通过连棒互连的多个引脚框架，所述连棒提供有布置在每个引脚框架的相邻引脚之间的凹槽以便减少切单封装时锯片必须通过的金属的量。此外，凹槽形成暴露引脚之间的空间，降低或消除毛边或污迹导致引脚之间短路的可能性。该凹槽不影响引脚与集成电路器件电互连期间的引脚稳定性，保证可靠的接合完整性。而且，所形成的封装具有在侧面暴露的全引脚材料，允许板安装期间有焊料填角。
[0044]虽然是在密封集成电路器件方面进行描述，但是本发明的封装还可以用来密封混合式器件，其中将一个或多个无源或光学器件耦合到单个单元片焊盘上的一个或多个集成电路器件。
[0045]已经描述了本发明的多个实施方案。虽然如此，但是可以理解能够在不脱离本发明的精神和范畴的情况下进行各种修改。因此，其它实施方案在所附权利要求的范围内。

Claims (19)

1.一种制造封闭半导体单元片(40)的封装(50)的方法，其特征在于以下步骤：
(a).提供导电框架(10)，其具有多个布置成矩阵形式的引脚框架(14、14′)，每个引脚框架具有从中心孔向外延伸的多个间隔引脚(16、16′)，所述导电框架(10)进一步具有多个连棒(24)，其连接所述引脚框架(14、14′)中相邻各引脚框架的外端部分；
(b).在所述连棒(24)中形成凹槽(20)以便在所述引脚框架(14、14′)的相邻各引脚框架的外端部分之间形成厚度减小的部分；
(c).将半导体单元片(40)电学耦合(42)到所述引脚(16、16′)的内部部分(30)；
(d).用模塑料(46)密封所述框架(10)和半导体单元片(40)；和
(e).沿着所述凹槽(20)切割(12)所述模塑料(46)和框架(10)以便形成被切单的半导体封装(50)，其具有高度大于所述厚度减小部分的高度的外引脚部分。
2.如权利要求1所述的方法，其特征在于通过化学蚀刻从所述框架(10)的一侧形成所述凹槽(20)。
3.如权利要求2所述的方法，其特征在于所述凹槽(20)将所述厚度减小的部分的厚度减小至所述框架(10)厚度的30％至70％。
4.如权利要求2所述的方法，其特征在于通过锯割切单执行所述切割(12)步骤(e)。
5.如权利要求4所述的方法，其特征在于所述锯割切单步骤导致所述外引脚部分的侧面部分构成所述半导体封装(50)的外周表面(56)的一部分。
6.如权利要求5所述的方法，其特征在于所述外引脚部分的所述侧面部分的高度等于所述框架(10)的高度。
7.如权利要求5所述的方法，其特征在于构成所述外周表面(56)的所述侧面部分涂覆有金属以便提高焊料润湿性。
8.如权利要求2所述的方法，其特征在于所述框架(100)进一步包括布置在所述中心孔中的单元片焊盘(23)并且半导体单元片(40)被接合(36)到所述单元片焊盘(23)。
9.如权利要求8所述的方法，其特征在于所述化学蚀刻步骤进一步在所述引脚(16、16′)和所述单元片焊盘(23)中的至少一个上形成凸缘(32、34)。
10.如权利要求2所述的方法，其特征在于所述半导体单元片(40)直接接合到所述引脚(16、16′)的内端部分(30)。
11.一种用于半导体封装(50)的导电框架(10)，其特征在于：
布置成矩阵形式的多个引脚框架(14、14′)，每个引脚框架(14，14′)具有从中心孔向外延伸的多个间隔引脚(16、16′)；和
多个连棒(24)，其连接所述引脚框架(14、14′)的相邻各引脚框架的外端部分，其中凹槽(20)延伸到每个所述连棒(24)中并布置在每个所述引脚框架(14、14′)的相邻引脚(16、16′)之间。
12.如权利要求11所述的导电框架(10)，其特征在于位于所述凹槽(20)下面的所述连棒(24)的一部分的厚度为所述导电框架(10)的厚度的30％至70％。
13.如权利要求12所述的导电框架(10)，其特征进一步在于单元片焊盘(23)布置在所述中心孔中。
14.如权利要求13所述的导电框架(10)，其特征在于所述单元片焊盘(23)与所述引脚(16、16′)中的至少一个包括环绕其外周的厚度减小的凸缘(32、34)。
15.一种密封至少一个半导体单元片的无引脚封装(66)，其特征在于：
引脚框架(14、14′)，其具有从内引脚端向外延伸到外引脚端的多个引脚(16、16′)，其中所述内引脚端限定中心孔并且所述外引脚端的侧面部分限定所述无引脚封装(66)的外周表面(56)，其中所述外引脚端至少与所述内引脚端一样厚；
所述至少一个半导体单元片(40)，其布置在所述中心孔中并电互连(42)到所述内引脚端；和
模塑料(46)，其密封所述至少一个半导体单元片(40)和所述内引脚端，其中所述模塑料(46)进一步限定所述无引脚封装(66)的所述外周表面(56)。
16.如权利要求15所述的无引脚封装(66)，其特征在于由所述外引脚端限定的所述外周表面(56)具有相当于已经部分通过化学蚀刻形成、部分通过锯切形成的表面。
17.如权利要求16所述的无引脚封装(66)，其特征在于由所述外引脚端限定的所述外周表面(56)涂覆有提高焊料润湿性的金属。
18.如权利要求17所述的无引脚封装(66)，其特征在于单元片焊盘(23)布置在所述中心孔中并且所述至少一个半导体单元片(40)被接合到所述单元片焊盘(23)。
19.如权利要求17所述的无引脚封装(66)，其特征在于所述至少一个半导体单元片(40)被直接接合到所述内引脚端。
CN2006800520635A 2005-12-02 2006-11-17 无引脚半导体封装及其制造方法 Expired - Fee Related CN101611484B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US74196505P 2005-12-02 2005-12-02
US60/741,965 2005-12-02
US11/590,726 US7943431B2 (en) 2005-12-02 2006-10-31 Leadless semiconductor package and method of manufacture
US11/590,726 2006-10-31
PCT/US2006/044768 WO2007067330A2 (en) 2005-12-02 2006-11-17 Leadless semiconductor package and method of manufacture

Publications (2)

Publication Number Publication Date
CN101611484A true CN101611484A (zh) 2009-12-23
CN101611484B CN101611484B (zh) 2012-03-21

Family

ID=38117869

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2006800520635A Expired - Fee Related CN101611484B (zh) 2005-12-02 2006-11-17 无引脚半导体封装及其制造方法

Country Status (5)

Country Link
US (1) US7943431B2 (zh)
EP (1) EP1972011A2 (zh)
CN (1) CN101611484B (zh)
TW (1) TWI358114B (zh)
WO (1) WO2007067330A2 (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106663661A (zh) * 2014-07-14 2017-05-10 美光科技公司 具有高效率散热路径的堆叠式半导体裸片组合件及相关联系统
CN107026130A (zh) * 2015-09-15 2017-08-08 英特矽尔美国有限公司 用于封装器件的装置和方法
CN109599344A (zh) * 2012-06-29 2019-04-09 恩智浦美国有限公司 半导体器件封装及其制作方法
CN112786580A (zh) * 2019-11-04 2021-05-11 联发科技股份有限公司 半导体封装及其制造方法和印刷电路板组件

Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8039947B2 (en) * 2006-05-17 2011-10-18 Stats Chippac Ltd. Integrated circuit package system with different mold locking features
DK2121204T3 (en) 2007-01-12 2016-01-18 Opex Corp A method and apparatus for sorting of items
JP2008258411A (ja) * 2007-04-05 2008-10-23 Rohm Co Ltd 半導体装置および半導体装置の製造方法
US20090162976A1 (en) * 2007-12-21 2009-06-25 Kuan-Hsing Li Method of manufacturing pins of miniaturization chip module
US8008132B2 (en) * 2007-12-28 2011-08-30 Sandisk Technologies Inc. Etched surface mount islands in a leadframe package
US8084299B2 (en) 2008-02-01 2011-12-27 Infineon Technologies Ag Semiconductor device package and method of making a semiconductor device package
US8244733B2 (en) 2008-05-05 2012-08-14 University Of Massachusetts Adaptive hybrid reasoning decision support system
JP5217800B2 (ja) * 2008-09-03 2013-06-19 日亜化学工業株式会社 発光装置、樹脂パッケージ、樹脂成形体並びにこれらの製造方法
US10163766B2 (en) 2016-11-21 2018-12-25 Semiconductor Components Industries, Llc Methods of forming leadless semiconductor packages with plated leadframes and wettable flanks
US9899349B2 (en) * 2009-01-29 2018-02-20 Semiconductor Components Industries, Llc Semiconductor packages and related methods
US10199311B2 (en) 2009-01-29 2019-02-05 Semiconductor Components Industries, Llc Leadless semiconductor packages, leadframes therefor, and methods of making
US8829685B2 (en) * 2009-03-31 2014-09-09 Semiconductor Components Industries, Llc Circuit device having funnel shaped lead and method for manufacturing the same
US8609467B2 (en) * 2009-03-31 2013-12-17 Sanyo Semiconductor Co., Ltd. Lead frame and method for manufacturing circuit device using the same
US8329509B2 (en) * 2010-04-01 2012-12-11 Freescale Semiconductor, Inc. Packaging process to create wettable lead flank during board assembly
TW201220455A (en) * 2010-11-10 2012-05-16 Raydium Semiconductor Corp Semiconductor device
US9324646B2 (en) 2010-12-13 2016-04-26 Infineon Technologies America Corp. Open source power quad flat no-lead (PQFN) package
US9449957B2 (en) 2010-12-13 2016-09-20 Infineon Technologies Americas Corp. Control and driver circuits on a power quad flat no-lead (PQFN) leadframe
US9524928B2 (en) 2010-12-13 2016-12-20 Infineon Technologies Americas Corp. Power quad flat no-lead (PQFN) package having control and driver circuits
US9620954B2 (en) 2010-12-13 2017-04-11 Infineon Technologies Americas Corp. Semiconductor package having an over-temperature protection circuit utilizing multiple temperature threshold values
US9355995B2 (en) * 2010-12-13 2016-05-31 Infineon Technologies Americas Corp. Semiconductor packages utilizing leadframe panels with grooves in connecting bars
US9659845B2 (en) 2010-12-13 2017-05-23 Infineon Technologies Americas Corp. Power quad flat no-lead (PQFN) package in a single shunt inverter circuit
US9443795B2 (en) 2010-12-13 2016-09-13 Infineon Technologies Americas Corp. Power quad flat no-lead (PQFN) package having bootstrap diodes on a common integrated circuit (IC)
US9362215B2 (en) 2010-12-13 2016-06-07 Infineon Technologies Americas Corp. Power quad flat no-lead (PQFN) semiconductor package with leadframe islands for multi-phase power inverter
US8587101B2 (en) 2010-12-13 2013-11-19 International Rectifier Corporation Multi-chip module (MCM) power quad flat no-lead (PQFN) semiconductor package utilizing a leadframe for electrical interconnections
US9711437B2 (en) 2010-12-13 2017-07-18 Infineon Technologies Americas Corp. Semiconductor package having multi-phase power inverter with internal temperature sensor
CN102789994B (zh) 2011-05-18 2016-08-10 飞思卡尔半导体公司 侧面可浸润半导体器件
TWI455269B (zh) * 2011-07-20 2014-10-01 Chipmos Technologies Inc 晶片封裝結構及其製作方法
DE102011112659B4 (de) 2011-09-06 2022-01-27 Vishay Semiconductor Gmbh Oberflächenmontierbares elektronisches Bauelement
CA2872496C (en) 2012-04-09 2020-12-29 Opex Corporation Method and apparatus for sorting or retrieving items
US8937376B2 (en) * 2012-04-16 2015-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor packages with heat dissipation structures and related methods
US9000589B2 (en) 2012-05-30 2015-04-07 Freescale Semiconductor, Inc. Semiconductor device with redistributed contacts
JP6087153B2 (ja) * 2013-01-10 2017-03-01 株式会社三井ハイテック リードフレーム
US9601415B2 (en) * 2014-03-27 2017-03-21 Renesas Electronics Corporation Method of manufacturing semiconductor device and semiconductor device
CN103928353A (zh) * 2014-04-14 2014-07-16 矽力杰半导体技术(杭州)有限公司 无外引脚封装构造及其制造方法与导线框架
US20160172275A1 (en) * 2014-12-10 2016-06-16 Stmicroelectronics S.R.L. Package for a surface-mount semiconductor device and manufacturing method thereof
CN105895611B (zh) 2014-12-17 2019-07-12 恩智浦美国有限公司 具有可湿性侧面的无引线方形扁平半导体封装
US10796986B2 (en) * 2016-03-21 2020-10-06 Infineon Technologies Ag Leadframe leads having fully plated end faces
US20170294367A1 (en) * 2016-04-07 2017-10-12 Microchip Technology Incorporated Flat No-Leads Package With Improved Contact Pins
WO2017181399A1 (en) * 2016-04-22 2017-10-26 Texas Instruments Incorporated Improved lead frame system
US11780676B2 (en) 2019-08-14 2023-10-10 Opex Corporation Systems and methods for managing inventory
CN113035722A (zh) 2019-12-24 2021-06-25 维谢综合半导体有限责任公司 具有选择性模制的用于镀覆的封装工艺
CN113035721A (zh) 2019-12-24 2021-06-25 维谢综合半导体有限责任公司 用于侧壁镀覆导电膜的封装工艺
US11768229B2 (en) * 2021-08-23 2023-09-26 Allegro Microsystems, Llc Packaged current sensor integrated circuit

Family Cites Families (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01125963A (ja) * 1987-11-11 1989-05-18 Nec Corp リードフレーム
JPH03136270A (ja) * 1989-10-20 1991-06-11 Dainippon Printing Co Ltd リードフレーム
JPH06232305A (ja) * 1993-02-05 1994-08-19 Toshiba Corp リ−ドフレ−ムの製造方法
JPH06275764A (ja) * 1993-03-19 1994-09-30 Fujitsu Miyagi Electron:Kk リードフレーム及びそのリードフレームを用いた半導体装置の製造方法
US5608262A (en) * 1995-02-24 1997-03-04 Lucent Technologies Inc. Packaging multi-chip modules without wire-bond interconnection
WO1996042107A1 (en) * 1995-06-13 1996-12-27 Hitachi Chemical Company, Ltd. Semiconductor device, wiring board for mounting semiconductor and method of production of semiconductor device
JPH09260538A (ja) * 1996-03-27 1997-10-03 Miyazaki Oki Electric Co Ltd 樹脂封止型半導体装置及び製造方法とその実装構造
MY118338A (en) * 1998-01-26 2004-10-30 Motorola Semiconductor Sdn Bhd A leadframe, a method of manufacturing a leadframe and a method of packaging an electronic component utilising the leadframe.
US6498099B1 (en) * 1998-06-10 2002-12-24 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
US6229200B1 (en) * 1998-06-10 2001-05-08 Asat Limited Saw-singulated leadless plastic chip carrier
US6281568B1 (en) * 1998-10-21 2001-08-28 Amkor Technology, Inc. Plastic integrated circuit device package and leadframe having partially undercut leads and die pad
JP2001077287A (ja) * 1999-09-06 2001-03-23 Mitsubishi Electric Corp 半導体装置用リードフレーム
US6483180B1 (en) * 1999-12-23 2002-11-19 National Semiconductor Corporation Lead frame design for burr-free singulation of molded array packages
JP2001185651A (ja) * 1999-12-27 2001-07-06 Matsushita Electronics Industry Corp 半導体装置およびその製造方法
US6525405B1 (en) * 2000-03-30 2003-02-25 Alphatec Holding Company Limited Leadless semiconductor product packaging apparatus having a window lid and method for packaging
JP2001320007A (ja) * 2000-05-09 2001-11-16 Dainippon Printing Co Ltd 樹脂封止型半導体装置用フレーム
US6400004B1 (en) * 2000-08-17 2002-06-04 Advanced Semiconductor Engineering, Inc. Leadless semiconductor package
TW473965B (en) * 2000-09-04 2002-01-21 Siliconware Precision Industries Co Ltd Thin type semiconductor device and the manufacturing method thereof
US6337510B1 (en) * 2000-11-17 2002-01-08 Walsin Advanced Electronics Ltd Stackable QFN semiconductor package
US6448107B1 (en) * 2000-11-28 2002-09-10 National Semiconductor Corporation Pin indicator for leadless leadframe packages
US6700186B2 (en) * 2000-12-21 2004-03-02 Mitsui High-Tec, Inc. Lead frame for a semiconductor device, a semiconductor device made from the lead frame, and a method of making a semiconductor device
US6424024B1 (en) * 2001-01-23 2002-07-23 Siliconware Precision Industries Co., Ltd. Leadframe of quad flat non-leaded package
JP3628971B2 (ja) * 2001-02-15 2005-03-16 松下電器産業株式会社 リードフレーム及びそれを用いた樹脂封止型半導体装置の製造方法
US6605865B2 (en) * 2001-03-19 2003-08-12 Amkor Technology, Inc. Semiconductor package with optimized leadframe bonding strength
TW498443B (en) * 2001-06-21 2002-08-11 Advanced Semiconductor Eng Singulation method for manufacturing multiple lead-free semiconductor packages
SG111919A1 (en) * 2001-08-29 2005-06-29 Micron Technology Inc Packaged microelectronic devices and methods of forming same
US6891276B1 (en) * 2002-01-09 2005-05-10 Bridge Semiconductor Corporation Semiconductor package device
JP3939554B2 (ja) * 2002-01-15 2007-07-04 シャープ株式会社 半導体用リードフレーム
TW533566B (en) * 2002-01-31 2003-05-21 Siliconware Precision Industries Co Ltd Short-prevented lead frame and method for fabricating semiconductor package with the same
US6885086B1 (en) * 2002-03-05 2005-04-26 Amkor Technology, Inc. Reduced copper lead frame for saw-singulated chip package
US6841854B2 (en) * 2002-04-01 2005-01-11 Matsushita Electric Industrial Co., Ltd. Semiconductor device
US6608366B1 (en) * 2002-04-15 2003-08-19 Harry J. Fogelson Lead frame with plated end leads
US6812552B2 (en) * 2002-04-29 2004-11-02 Advanced Interconnect Technologies Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
AU2003242873A1 (en) 2002-06-06 2003-12-22 Koninklijke Philips Electronics N.V. Quad flat non-leaded package comprising a semiconductor device
US6841414B1 (en) * 2002-06-19 2005-01-11 Amkor Technology, Inc. Saw and etch singulation method for a chip package
US6872599B1 (en) * 2002-12-10 2005-03-29 National Semiconductor Corporation Enhanced solder joint strength and ease of inspection of leadless leadframe package (LLP)
US6847099B1 (en) * 2003-02-05 2005-01-25 Amkor Technology Inc. Offset etched corner leads for semiconductor package
US7153724B1 (en) * 2003-08-08 2006-12-26 Ns Electronics Bangkok (1993) Ltd. Method of fabricating no-lead package for semiconductor die with half-etched leadframe
CN100514580C (zh) 2003-08-26 2009-07-15 宇芯（毛里求斯）控股有限公司 可颠倒无引线封装及其堆叠
US7060536B2 (en) * 2004-05-13 2006-06-13 St Assembly Test Services Ltd. Dual row leadframe and fabrication method
US7242076B2 (en) * 2004-05-18 2007-07-10 Fairchild Semiconductor Corporation Packaged integrated circuit with MLP leadframe and method of making same
US7087461B2 (en) * 2004-08-11 2006-08-08 Advanced Semiconductor Engineering, Inc. Process and lead frame for making leadless semiconductor packages
US7262491B2 (en) * 2005-09-06 2007-08-28 Advanced Interconnect Technologies Limited Die pad for semiconductor packages and methods of making and using same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109599344A (zh) * 2012-06-29 2019-04-09 恩智浦美国有限公司 半导体器件封装及其制作方法
CN106663661A (zh) * 2014-07-14 2017-05-10 美光科技公司 具有高效率散热路径的堆叠式半导体裸片组合件及相关联系统
CN107026130A (zh) * 2015-09-15 2017-08-08 英特矽尔美国有限公司 用于封装器件的装置和方法
CN107026130B (zh) * 2015-09-15 2022-10-21 英特矽尔美国有限公司 用于封装器件的装置和方法
CN112786580A (zh) * 2019-11-04 2021-05-11 联发科技股份有限公司 半导体封装及其制造方法和印刷电路板组件

Also Published As

Publication number Publication date
WO2007067330A2 (en) 2007-06-14
WO2007067330A3 (en) 2009-05-07
US7943431B2 (en) 2011-05-17
CN101611484B (zh) 2012-03-21
US20070126092A1 (en) 2007-06-07
EP1972011A2 (en) 2008-09-24
TW200737475A (en) 2007-10-01
TWI358114B (en) 2012-02-11

Similar Documents

Publication Publication Date Title
CN101611484B (zh) 无引脚半导体封装及其制造方法
CN101375382B (zh) 半导体器件封装及其制造方法
CN100514580C (zh) 可颠倒无引线封装及其堆叠
US5696033A (en) Method for packaging a semiconductor die
KR100462105B1 (ko) 수지밀봉형 반도체장치의 제조방법
EP1032037B1 (en) Resin-moulded semiconductor device, method for manufacturing the same, and leadframe
CN100416815C (zh) 包括无源器件的引线框架及其形成方法
US8174096B2 (en) Stamped leadframe and method of manufacture thereof
JP2002134676A (ja) リードフレーム及びそれを備えた半導体パッケージ、並びにその半導体パッケージの製造方法
EP3440697B1 (en) Flat no-leads package with improved contact leads
JP2005191240A (ja) 半導体装置及びその製造方法
KR20000028854A (ko) 플라스틱 집적회로 장치 패키지와 마이크로 리드프레임 및패키지의 제조 방법
US20040056363A1 (en) Semiconductor device and a method of manufacturing the same
KR20000017634A (ko) 반도체 장치 및 그 제조 방법
KR20140032889A (ko) 반도체 장치의 제조 방법 및 반도체 장치
EP0657922B1 (en) A packaged semiconductor device and method of its manufacture
KR19980066540A (ko) 캐리어프레이 및 서브스트레이트와 이들을 이용한 볼 그리드 어레이 패키지의 제조방법
US20220208660A1 (en) Electronic package with surface contact wire extensions
CN114981940A (zh) 在坚固的封装衬底中具有分割裸片垫的经封装电子装置
CN100466209C (zh) 半导体器件及其加工和封装方法
JP5857883B2 (ja) モールドパッケージの製造方法
JP3723351B2 (ja) 半導体装置、およびその製造方法
JP3076282B2 (ja) 半導体装置の製造方法
JP2001077275A (ja) リードフレームとそれを用いた樹脂封止型半導体装置の製造方法
KR100206954B1 (ko) 반도체 볼 그리드 어레이 패키지의 제조방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20120321

Termination date: 20141117

EXPY Termination of patent right or utility model