CN101606237B - 包括带检测连接焊盘的电路基片的半导体设备及其制造方法 - Google Patents
包括带检测连接焊盘的电路基片的半导体设备及其制造方法 Download PDFInfo
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- CN101606237B CN101606237B CN2008800042825A CN200880004282A CN101606237B CN 101606237 B CN101606237 B CN 101606237B CN 2008800042825 A CN2008800042825 A CN 2008800042825A CN 200880004282 A CN200880004282 A CN 200880004282A CN 101606237 B CN101606237 B CN 101606237B
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- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/162—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01087—Francium [Fr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Tests Of Electronic Circuits (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007087662A JP2008251608A (ja) | 2007-03-29 | 2007-03-29 | 半導体装置およびその製造方法 |
JP087662/2007 | 2007-03-29 | ||
PCT/JP2008/056265 WO2008123481A1 (en) | 2007-03-29 | 2008-03-25 | Semiconductor device comprising circuit substrate with inspection connection pads and manufacturing method thereof |
Publications (2)
Publication Number | Publication Date |
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CN101606237A CN101606237A (zh) | 2009-12-16 |
CN101606237B true CN101606237B (zh) | 2012-10-17 |
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Family Applications (1)
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CN2008800042825A Expired - Fee Related CN101606237B (zh) | 2007-03-29 | 2008-03-25 | 包括带检测连接焊盘的电路基片的半导体设备及其制造方法 |
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US (1) | US7932517B2 (ja) |
EP (1) | EP2126968A1 (ja) |
JP (1) | JP2008251608A (ja) |
KR (1) | KR20090101293A (ja) |
CN (1) | CN101606237B (ja) |
TW (1) | TWI373114B (ja) |
WO (1) | WO2008123481A1 (ja) |
Families Citing this family (16)
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JP5222509B2 (ja) | 2007-09-12 | 2013-06-26 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US20100308468A1 (en) * | 2008-03-14 | 2010-12-09 | Noriyuki Yoshikawa | Semiconductor device and semiconductor device fabrication method |
JP2010192653A (ja) * | 2009-02-18 | 2010-09-02 | Panasonic Corp | 半導体装置 |
NZ577731A (en) | 2009-06-16 | 2010-08-27 | Innate Therapeutics Ltd | Compositions and methods for treatment of multiple sclerosis |
JP4829358B2 (ja) * | 2010-03-30 | 2011-12-07 | 株式会社東芝 | モジュールおよび電子機器 |
US8343810B2 (en) | 2010-08-16 | 2013-01-01 | Stats Chippac, Ltd. | Semiconductor device and method of forming Fo-WLCSP having conductive layers and conductive vias separated by polymer layers |
JP5666366B2 (ja) * | 2011-03-31 | 2015-02-12 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US9431274B2 (en) * | 2012-12-20 | 2016-08-30 | Intel Corporation | Method for reducing underfill filler settling in integrated circuit packages |
TWI548042B (zh) * | 2013-04-23 | 2016-09-01 | 巨擘科技股份有限公司 | 電子系統及其核心模組 |
JP5684349B1 (ja) | 2013-09-10 | 2015-03-11 | 株式会社東芝 | 半導体装置および半導体装置の検査方法 |
TWI569368B (zh) | 2015-03-06 | 2017-02-01 | 恆勁科技股份有限公司 | 封裝基板、包含該封裝基板的封裝結構及其製作方法 |
CN105990307B (zh) * | 2015-03-06 | 2019-06-07 | 恒劲科技股份有限公司 | 封装基板及包含该封装基板的封装结构及其制作方法 |
CN108573877B (zh) * | 2017-03-14 | 2021-08-27 | 兴讯科技股份有限公司 | 形成贴附式双面载放零件的电子芯片模块的方法 |
KR102586888B1 (ko) * | 2018-11-27 | 2023-10-06 | 삼성전기주식회사 | 반도체 패키지 |
KR102632367B1 (ko) * | 2018-12-04 | 2024-02-02 | 삼성전기주식회사 | 반도체 패키지 |
US12055633B2 (en) * | 2020-08-25 | 2024-08-06 | Lumentum Operations Llc | Package for a time of flight device |
Citations (1)
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US5986460A (en) * | 1995-07-04 | 1999-11-16 | Ricoh Company, Ltd. | BGA package semiconductor device and inspection method therefor |
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Publication number | Priority date | Publication date | Assignee | Title |
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JPH1079405A (ja) * | 1996-09-04 | 1998-03-24 | Hitachi Ltd | 半導体装置およびそれが実装された電子部品 |
TW449844B (en) * | 1997-05-17 | 2001-08-11 | Hyundai Electronics Ind | Ball grid array package having an integrated circuit chip |
JPH1117057A (ja) * | 1997-06-26 | 1999-01-22 | Nec Corp | 検査パッド付きbga型半導体装置 |
JP3459765B2 (ja) * | 1997-07-16 | 2003-10-27 | シャープ株式会社 | 実装検査システム |
US6678167B1 (en) * | 2000-02-04 | 2004-01-13 | Agere Systems Inc | High performance multi-chip IC package |
JP2001291820A (ja) * | 2000-04-05 | 2001-10-19 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
JP3874062B2 (ja) * | 2000-09-05 | 2007-01-31 | セイコーエプソン株式会社 | 半導体装置 |
JP2002314031A (ja) * | 2001-04-13 | 2002-10-25 | Fujitsu Ltd | マルチチップモジュール |
US20020158318A1 (en) * | 2001-04-25 | 2002-10-31 | Chen Hung Nan | Multi-chip module |
JP2004022664A (ja) * | 2002-06-13 | 2004-01-22 | Matsushita Electric Ind Co Ltd | 半導体装置のパッケージおよび検査回路 |
US7087988B2 (en) * | 2002-07-30 | 2006-08-08 | Kabushiki Kaisha Toshiba | Semiconductor packaging apparatus |
JP3888302B2 (ja) | 2002-12-24 | 2007-02-28 | カシオ計算機株式会社 | 半導体装置 |
DE10300958A1 (de) * | 2003-01-13 | 2004-07-22 | Epcos Ag | Modul mit Verkapselung |
JP2004281633A (ja) * | 2003-03-14 | 2004-10-07 | Olympus Corp | 積層モジュール |
JP2005209882A (ja) * | 2004-01-22 | 2005-08-04 | Renesas Technology Corp | 半導体パッケージ及び半導体装置 |
US7151010B2 (en) * | 2004-12-01 | 2006-12-19 | Kyocera Wireless Corp. | Methods for assembling a stack package for high density integrated circuits |
JP4581768B2 (ja) * | 2005-03-16 | 2010-11-17 | ソニー株式会社 | 半導体装置の製造方法 |
JP5259053B2 (ja) * | 2005-12-15 | 2013-08-07 | パナソニック株式会社 | 半導体装置および半導体装置の検査方法 |
JP2008226945A (ja) * | 2007-03-09 | 2008-09-25 | Casio Comput Co Ltd | 半導体装置およびその製造方法 |
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2007
- 2007-03-29 JP JP2007087662A patent/JP2008251608A/ja active Pending
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2008
- 2008-03-25 KR KR1020097016355A patent/KR20090101293A/ko not_active Application Discontinuation
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- 2008-03-25 WO PCT/JP2008/056265 patent/WO2008123481A1/en active Application Filing
- 2008-03-25 CN CN2008800042825A patent/CN101606237B/zh not_active Expired - Fee Related
- 2008-03-26 US US12/079,259 patent/US7932517B2/en not_active Expired - Fee Related
- 2008-03-27 TW TW097110911A patent/TWI373114B/zh not_active IP Right Cessation
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5986460A (en) * | 1995-07-04 | 1999-11-16 | Ricoh Company, Ltd. | BGA package semiconductor device and inspection method therefor |
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WO2008123481A1 (en) | 2008-10-16 |
KR20090101293A (ko) | 2009-09-24 |
TW200847379A (en) | 2008-12-01 |
TWI373114B (en) | 2012-09-21 |
JP2008251608A (ja) | 2008-10-16 |
US7932517B2 (en) | 2011-04-26 |
CN101606237A (zh) | 2009-12-16 |
EP2126968A1 (en) | 2009-12-02 |
US20080237589A1 (en) | 2008-10-02 |
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