CN101578695A - 半导体元件的安装结构体及半导体元件的安装方法 - Google Patents
半导体元件的安装结构体及半导体元件的安装方法 Download PDFInfo
- Publication number
- CN101578695A CN101578695A CNA2007800485532A CN200780048553A CN101578695A CN 101578695 A CN101578695 A CN 101578695A CN A2007800485532 A CNA2007800485532 A CN A2007800485532A CN 200780048553 A CN200780048553 A CN 200780048553A CN 101578695 A CN101578695 A CN 101578695A
- Authority
- CN
- China
- Prior art keywords
- mentioned
- semiconductor element
- recess
- substrate
- assembling structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 256
- 238000000034 method Methods 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 130
- 238000010438 heat treatment Methods 0.000 claims abstract description 6
- 229920005989 resin Polymers 0.000 claims description 77
- 239000011347 resin Substances 0.000 claims description 77
- 230000002093 peripheral effect Effects 0.000 claims description 40
- 238000009434 installation Methods 0.000 claims description 38
- 238000007789 sealing Methods 0.000 claims description 24
- 230000015572 biosynthetic process Effects 0.000 claims description 15
- 238000002788 crimping Methods 0.000 claims description 12
- 230000008676 import Effects 0.000 claims description 7
- 239000013536 elastomeric material Substances 0.000 claims description 5
- 208000034189 Sclerosis Diseases 0.000 claims description 2
- 238000001816 cooling Methods 0.000 abstract description 5
- 230000008569 process Effects 0.000 abstract description 4
- 229920006223 adhesive resin Polymers 0.000 abstract 2
- 239000012945 sealing adhesive Substances 0.000 abstract 2
- 239000000463 material Substances 0.000 description 16
- 230000000052 comparative effect Effects 0.000 description 15
- 239000000945 filler Substances 0.000 description 10
- 238000012545 processing Methods 0.000 description 8
- 230000008602 contraction Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000012141 concentrate Substances 0.000 description 3
- 238000002474 experimental method Methods 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 239000003351 stiffener Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 229920002379 silicone rubber Polymers 0.000 description 2
- 239000004945 silicone rubber Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002148 esters Chemical class 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05655—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
- H01L2224/2733—Manufacturing methods by local deposition of the material of the layer connector in solid form
- H01L2224/27334—Manufacturing methods by local deposition of the material of the layer connector in solid form using preformed layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32057—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/75252—Means for applying energy, e.g. heating means in the upper part of the bonding apparatus, e.g. in the bonding head
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/75301—Bonding head
- H01L2224/75314—Auxiliary members on the pressing surface
- H01L2224/75315—Elastomer inlay
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/75301—Bonding head
- H01L2224/75314—Auxiliary members on the pressing surface
- H01L2224/75315—Elastomer inlay
- H01L2224/75316—Elastomer inlay with retaining mechanisms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83009—Pre-treatment of the layer connector or the bonding area
- H01L2224/83051—Forming additional members, e.g. dam structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83194—Lateral distribution of the layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/0665—Epoxy resin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/1579—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30105—Capacitance
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
本发明提供一种半导体元件的安装结构体,通过在与半导体元件的外周端部对置的位置处的基板表面上形成其内侧的一部分配置有密封粘接用树脂的凹部,从而在抑制密封粘接用树脂中的凸缘部分(扩边部分)的配置区域的扩大的同时增大其倾斜角度。由此,减轻了因安装时的加热处理或冷却处理而产生的各构件的热膨胀差和热收缩差所导致的半导体元件周边部分产生的应力负荷,能够避免半导体元件的安装结构体的内部破损。
Description
技术领域
本发明涉及一种半导体元件的安装结构体及半导体元件的安装方法,其中,通过突起电极对半导体元件的元件电极与基板的基板电极进行连接,并且在上述半导体元件与上述基板之间配置密封粘接用树脂,从而将上述半导体元件安装到上述基板上。
背景技术
作为电子器件在利用与以往的半导体封装相比能大幅度缩小安装面积的裸片(bare chip)安装的情形中,使半导体芯片(半导体元件)的电路形成面与基板的电路形成面对置并通过隔着由金等金属形成的凸块(突起电极)重叠来获得导通的面朝下(face down)安装,相比于使基板的电路形成面与半导体芯片的电路形成面的相反侧的面对置并通过引线结合引出金属细线来连接两端子的面朝上(face up)安装,半导体芯片及其安装结构体整体能够进一步小型化,因此被广泛利用。
在此,图15中表示这样的以往的半导体芯片的安装结构体501的示意俯视图,图16中表示图15的安装结构体501中的A-A线剖视图。如图15和图16所示,在具有大致方形的形状的半导体芯片2的下表面侧即电路形成面上形成有多个作为元件电极的焊盘3,在作为基板4的上表面侧的电路形成面上形成有多个基板电极5。各个焊盘3和基板电极5通过在焊盘3上独立形成的突起电极即凸块6独立地电连接。另外,在半导体芯片2与基板4之间,作为密封粘接用的绝缘性树脂填充配置有底层填料7,由此,以各个焊盘3、基板电极5和凸块6被密封的状态形成了半导体芯片2和基板4被粘接起来的安装结构体。
这样的安装结构体例如可通过使半导体芯片2的各个焊盘3上形成的凸块6与表面贴附有片状的底层填料7的基板4对置,然后实施隔着底层填料7将半导体芯片2按压到基板4的所谓的压片工序来形成。尤其是,在这样的以往的压片工序中,能够同时进行向半导体芯片2与基板4之间填充配置底层填料7、隔着凸块6使半导体芯片2的焊盘3与基板4的基板电极5电连接,从简化工序和缩短时间的方面来看是有效的,因此被广泛利用。
专利文献1:特开2000-188362号公报
专利文献2:特开2002-134558号公报
近年,为了实现半导体封装的小型、低成本化,以芯片内部布线的微细化为目的的芯片内部的绝缘材料的低介电常数化正在发展。关于这样的低介电常数的树脂材料(以下称为“Low-k材料”),在介电常数降低的同时伴随着其机械强度的脆弱化,在半导体芯片的安装工序中,有可能发生由Low-k材料的脆弱性引起的半导体芯片的内部破损。
这里,关于Low-k材料,利用图19所示的半导体芯片的示意剖面图进行说明。如图19所示,半导体芯片2具备:硅(Si)层511、在硅层511上由Low-k材料形成的Low-k层512、在Low-k层512上形成且主要形成布线的布线层513、在布线层513上由SiO2或SiNx形成的绝缘层514。此外,Low-k层512和布线层513例如层叠多个薄膜层而形成。另外,配置成在绝缘层514的表面露出多个焊盘3,对各个焊盘3与硅层511进行电连接的多个通孔电极515按照贯通Low-k层512和布线层513的方式形成。这样的Low-k层512形成为厚度比作为半导体芯片2的主体部分的硅层511薄的薄膜,并且如上所述,具有介电常数低且机械强度比其他层脆弱的特点。由于这样的Low-k层512的机械强度的脆弱性,有可能发生例如Low-k层512中产生裂缝516或在Low-k层512处发生界面剥离等导致的半导体芯片的内部破损。
一般,半导体芯片的热膨胀系数与底层填料或基板的热膨胀系数相比极小,因安装时的加热处理或冷却处理所产生的各构件的热膨胀差或热收缩差,在半导体芯片的各部分尤其是方形的半导体芯片的角部会产生大的拉伸负荷。例如,假设半导体芯片的热膨胀率为1,则底层填料的热膨胀率为40~50ppm、基板的热膨胀率为5~20ppm。另外,在半导体芯片的安装工序中,例如,由于在安装了半导体芯片后的基板的割断工序、即多块成型基板的割断工序或实施向基板的背面添加焊料球的工序等时所产生的机械负荷,基板会发生挠曲,对半导体芯片的负荷增大。
为了减轻这些负荷,例如在专利文献1中如图17的示意说明图所示,在半导体元件的安装结构体601中采用了下述结构,即,在基板4的表面形成槽部610,该基板4位于半导体元件2的周围形成的填充剂(底层填料)607的凸缘部(扩边部)607a的下部,向该槽部610中也填充填充剂607,即用填充剂填满槽部610。在这样的结构中,槽部610中填充的填充剂607起到锚固作用,提高了填充剂607与基板4的粘接强度。即,采用了借助填充剂使基板4牢固地保持半导体元件的外周端部的结构。
另外,例如在专利文献2中如图18所示,在半导体元件的安装结构体701中采用了下述结构,即,通过在半导体元件2的角部的侧面与底层填料707之间设置加强构件(树脂)711,从而由该加强构件711分散所作用的应力。
但是,在专利文献1的半导体元件的安装结构体601中,由于采用了为提高填充剂607与基板4的接合力而向半导体元件2的安装区域的周围形成的槽部610内可靠地填充填充剂607的结构,因此,凸缘部607a处配置的填充剂607的量变多,存在凸缘部607a的扩展区域扩大的趋势。因此,难以充分降低由各部件的热膨胀差或热收缩差引起的拉伸负荷,尤其是对薄型化的半导体元件施加应力负荷(拉伸负荷)会发生剥离引起的元件破损。这里,剥离是指在半导体元件中与底层填料(树脂或填充剂)接触的部分从半导体元件主体分离的现象。
另外,在专利文献2的半导体元件的安装结构体701中,为了缓和应力而使用了两种树脂,因此其制造工序变得复杂。进而,对于薄型化的半导体元件2而言,还存在难以配置加强构件711的问题。
发明内容
本发明的目的在于解决上述问题,提供一种半导体元件的安装结构体及其安装方法,借助突起电极连接半导体元件的元件电极和基板的基板电极,并且在上述半导体元件与上述基板之间配置密封粘接用树脂,将上述半导体元件安装到上述基板上,由此,减轻因安装时的加热处理或冷却处理而产生的各构件的热膨胀差和热收缩差、以及相对于安装后的机械负荷的基板的挠曲所导致的半导体元件周边部分产生的负荷,能够避免半导体元件的安装结构体的内部破损。
为了实现上述目的,本发明按以下方式构成。
根据本发明的第一方式,提供一种半导体元件的安装结构体,其特征在于,具备:具有多个元件电极的半导体元件;具有多个基板电极的基板;对上述各个元件电极和基板电极进行连接的多个突起电极;密封粘接用树脂,其配置在上述半导体元件与上述基板之间,以对上述各个元件电极、基板电极和突起电极进行密封,并对上述半导体元件与上述基板进行粘接;和凹部,其形成在上述基板的电极形成面上与上述半导体元件的外周端部对置的位置,且在内侧的一部分配置有上述密封粘接用树脂。
根据本发明的第二方式,提供一种具有下述特征的第一方式所述的半导体元件的安装结构体,在上述基板上形成的上述凹部,是通过在其内侧配置上述树脂来限制上述树脂向上述基板的与上述半导体元件对置的区域外扩展的扩展区域的树脂扩展区域限制用凹部。
根据本发明的第三方式,提供一种具有下述特征的第一方式所述的半导体元件的安装结构体,上述凹部形成为包括上述基板的比与上述半导体元件对置的区域的外周端部靠内侧的区域。
根据本发明的第四方式,提供一种具有下述特征的第一方式所述的半导体元件的安装结构体,上述凹部具有按照向上述基板的与上述半导体元件对置的区域的周围变深的方式倾斜的内底部。
根据本发明的第五方式,提供一种具有下述特征的第一方式所述的半导体元件的安装结构体,在上述基板的与上述半导体元件对置的区域的中心形成有比上述凹部的开口端部隆起的隆起部,从上述隆起部到上述凹部的内底部设置有下降梯度。
根据本发明的第六方式,提供一种具有下述特征的第一方式~第五方式中任一方式所述的半导体元件的安装结构体,在与具有大致方形的形状的上述半导体元件的角部对置的位置形成的上述凹部,形成为其内侧的容积比其他位置形成的上述凹部小。
根据本发明的第七方式,提供一种具有下述特征的第一方式~第五方式中任一方式所述的半导体元件的安装结构体,在上述基板的与上述半导体元件对置的区域的外周端部形成有多个上述凹部。
根据本发明的第八方式,提供一种具有下述特征的第一方式~第五方式中任一方式所述的半导体元件的安装结构体,在上述基板的与上述半导体元件对置的区域的外周端部的整周连续形成有上述凹部。
根据本发明的第九方式,提供一种具有下述特征的第一方式~第五方式中任一方式所述的半导体元件的安装结构体,在与具有大致方形的形状的上述半导体元件的角部对置的位置形成的上述凹部,形成为具有比其他位置形成的上述凹部深的内底部。
根据本发明的第十方式,提供一种具有下述特征的第四方式所述的半导体元件的安装结构体,在与具有大致方形的形状的上述半导体元件的角部对置的位置形成的上述凹部,形成为具有倾斜角度比其他位置形成的上述凹部的上述内底部的倾斜角度大的上述内底部。
根据本发明的第十一方式,提供一种半导体元件的安装方法,其特征在于,在半导体元件的安装区域的外周端部形成有凹部的基板的上述安装区域上配置密封粘接用树脂,隔着上述密封粘接用树脂将上述半导体元件按压到上述基板上,通过各个突起电极对上述半导体元件的各个元件电极与上述基板的各个基板电极进行连接,并且将向上述安装区域外扩展的上述密封粘接用树脂的一部分导入到上述凹部内,限制上述树脂的扩展区域,同时通过上述树脂对上述各个元件电极、基板电极和突起电极进行密封,然后对上述密封粘接用树脂进行加热使其硬化,将上述半导体元件安装到上述基板上。
根据本发明的第十二方式,提供一种具有下述特征的第十一方式所述的半导体元件的安装方法,利用具有由弹性材料形成的按压部的压接工具通过上述按压部隔着上述密封粘接用树脂将上述半导体元件按压到上述基板上,并通过上述按压部对向上述安装区域外扩展的上述密封粘接用树脂进行按压将其导入上述凹部内以限制上述树脂的扩展区域,与此同时进行基于上述密封粘接用树脂的密封,。
(发明效果)
根据本发明,在半导体的安装结构体中,由于在与半导体元件的外周端部对置的位置的基板表面上形成了其内侧的一部分配置有密封粘接用树脂的凹部,因此,能限制密封粘接用树脂中的凸缘部分(扩边部分)的配置区域的扩大,同时能增大其倾斜角度。即,由于隔着树脂将半导体元件安装到基板上时施加的按压力,树脂向基板与半导体元件的对置区域的周围外侧扩展而形成凸缘部分,但此时通过将树脂的一部分导入到凹部内能减少树脂的扩展区域,并且能增大凸缘部分的倾斜角度。这样,通过减少凸缘部分的扩展区域的面积并增大其倾斜角度,能够减轻因安装时的加热处理或冷却处理而产生的各构件的热膨胀差和热收缩差、以及相对于安装后的机械负荷的基板的挠曲所导致的半导体元件周边部分产生的应力负荷,能够避免半导体元件的安装结构体的内部破损。
附图说明
本发明的以上和其他目的及特点可通过结合附图对优选实施方式的下述描述进一步明了,各附图中,
图1是本发明的第一实施方式的半导体芯片的安装结构体的示意剖视图;
图2是上述第一实施方式的变形例的半导体芯片的安装结构体的示意剖视图;
图3是相对于上述第一实施方式的比较例的半导体芯片的安装结构体的示意剖视图;
图4是表示图1的半导体芯片的安装结构体的制造方法的示意说明图,是表示即将通过压接工具进行按压之前的状态的图;
图5是表示图1的半导体芯片的安装结构体的制造方法的示意说明图,是表示正在通过压接工具进行按压的状态的图;
图6是本发明的第二实施方式的半导体芯片的安装结构体的示意剖视图;
图7是上述第二实施方式的变形例的半导体芯片的安装结构体的示意剖视图;
图8是相对于上述第二实施方式的比较例的半导体芯片的安装结构体的示意剖视图;
图9是相对于上述第二实施方式的另一比较例的半导体芯片的安装结构体的示意剖视图;
图10是本发明的第三实施方式的半导体芯片的安装结构体的示意剖视图;
图11是本发明的第四实施方式的半导体芯片的安装结构体的示意俯视图;
图12是本发明的第四实施方式的另一半导体芯片的安装结构体的示意俯视图;
图13是本发明的第四实施方式的又一半导体芯片的安装结构体的示意俯视图;
图14是本发明的第四实施方式的再一半导体芯片的安装结构体的示意俯视图;
图15是以往的半导体芯片的安装结构体的示意俯视图;
图16是图15的半导体芯片的安装结构体中的A-A线示意剖视图;
图17是以往的另一半导体芯片的安装结构体的示意剖视图;
图18是以往的又一半导体芯片的安装结构体的示意剖视图;
图19是以往的半导体芯片的示意剖视图;
图20是本发明的第五实施方式的半导体芯片的安装结构体的示意俯视图;
图21是图20的半导体芯片的安装结构体中的B-B线示意剖视图;
图22是图20的半导体芯片的安装结构体中的C-C线示意剖视图;
图23是第五实施方式的变形例的半导体芯片的安装结构体的示意俯视图。
具体实施方式
继续进行本发明的描述之前,在附图中对相同部件标注了相同标记。
下面,基于附图对本发明的实施方式进行详细说明。
(第一实施方式)
图1中表示作为本发明的第一实施方式的半导体元件的安装结构体的一例的半导体芯片的安装结构体1的示意剖视图。
如图1所示,该第一实施方式的半导体芯片的安装结构体1中,在基板4上配置作为密封粘接用树脂的一例的片状的底层填料7,隔着该底层填料7安装有半导体芯片2。在半导体芯片2的图中下表面侧即电路形成面上形成有作为元件电极的一例的多个焊盘3,按照与这些焊盘3的形成位置对应的方式在基板4的图中上表面侧即电路形成面(电极形成面)上形成有多个基板电极5,各个焊盘3和各个基板电极5通过作为突起电极的一例的凸块6独立地电连接。另外,凸块6主要由Au形成,以稍微被挤压变形的状态介于基板电极5与焊盘3之间。另外,底层填料7由绝缘性树脂材料形成,将处于相互电连接状态的各个焊盘3、基板电极5和凸块6完全覆盖并密封,而且按照维持这些部件的连接状态的方式介于半导体芯片2与基板4之间将两者粘接起来。在这样的状态下,半导体芯片2被安装到基板4上,构成了半导体芯片的安装结构体1即半导体封装部件。
另外,半导体芯片2的平面形状为大致方形,在与半导体芯片2的方形的外周端部对置的基板4上的位置P1、即基板4上用于安装半导体芯片2的安装区域(半导体芯片2投影到基板表面上的区域或基板4与半导体芯片2对置的区域)的外周端部位置P1,形成有比其周围表面下凹一部分而构成的凹部(或槽部)8。该凹部8形成为使与半导体芯片2的外周端部对置的位置P1位于其内侧。即,如图1所示,按照使与半导体芯片2的外周端部对置的位置P1位于以半导体芯片2的中心为基准的凹部8的外侧方向的端部位置P3与内侧方向的端部位置P2之间的方式,决定凹部8的形成位置。
另外,如图1所示,凹部8内处于在底层填料7的外周侧形成的凸缘部(扩边部)7a中的树脂的一部分配置在该凹部8内的状态。不过,并不是凹部8内完全被树脂填充的状态,而是只有内侧的一部分配置了树脂的状态。这样,通过使凸缘部7a中的树脂的一部分配置在该凹部8内,与未形成凹部8的情形相比,凸缘部7a的扩展区域被限制在缩小的方向,并且,成为凸缘部7a的倾斜角度更陡峭的状态、即相对于基板4的表面的角度更大的状态。
基板4例如由玻璃环氧树脂材料形成,焊盘3和基板电极5由铜形成。此外,焊盘3和基板电极5可由Ni或镀Au、或Al形成。另外,底层填料7作为绝缘性树脂材料例如由具有热硬化性的环氧树脂材料形成。此外,作为基板4,还可使用陶瓷基板、树脂基板、树脂片基板等。另外,底层填料7通过在基板4上配置片状的材料而形成,但也可替代这种情况而通过将半液状的树脂材料涂敷到基板4上等来配置。
凹部8例如通过激光加工等方法形成。在使用这样的激光加工方法时,如图1所示,通过预先在基板4的内部设置用于使激光加工停止的停止层9,能够容易地形成所希望的深度的凹部8。这样的停止层9例如可使用铜层。此外,在作为基板4使用树脂成形基板的情况下,利用模具形成凹部8而非利用激光加工。这样的凹部8的形成方法,优选考虑基板4所使用的材料的种类和基板的形状等来决定。
在这样的半导体芯片的安装结构体1中,例如,半导体芯片2的厚度尺寸为0.15mm,底层填料7的厚度尺寸(基板与半导体芯片之间的距离)为0.05mm,基板4的厚度尺寸为0.30mm,凹部8的深度尺寸为0.10mm。此外,凹部8的宽度尺寸(图1中的P2P3之间的距离)为0.45mm,凹部8的内侧方向的端部位置P2与半导体芯片2的外周端部位置P1之间的距离为0.15mm,凹部8的外侧方向的端部位置P3与半导体芯片2的外周端部位置P1之间的距离为0.3mm。此外,并不希望凹部8的外侧方向的端部位置P3与半导体芯片2的外周端部位置P1相距过远,例如,优选按照P1P3之间的距离在0.5mm以下的方式形成凹部8。另外,优选按照凹部8的内侧方向的端部位置P2不到达基板电极5的形成位置的方式形成凹部8。
这里,图2中表示该第一实施方式的变形例的半导体芯片的安装结构体11的示意剖视图,图3中表示该第一实施方式的比较例的半导体芯片的安装结构体21的示意剖视图。此外,在图2和图3所示的半导体芯片的安装结构体11、21中,对于具有与图1的安装结构体1相同结构的构件标注相同标记并省略说明。
首先,在图2所示的变形例的半导体芯片的安装结构体11中,按照凹部8的内侧方向的端部位置P2与半导体芯片2的外周端部位置P1大致一致的方式形成了凹部8。此外,在凹部8内并非由底层填料7完全填充而仅配置一部分这一点上与图1的安装结构体1具有同样的结构。在这样的结构中,虽然凸缘部7a的扩展区域与图1的安装结构体1相比存在稍微扩大的趋势,但与未形成凹部的结构相比具有能限制在使扩展区域缩小的方向上的效果,而且,能形成使凸缘部7a的倾斜角度处于陡峭的状态。
相对于此,在图3的比较例的半导体芯片的安装结构体21中,具有按照比半导体芯片2的外周端部位置P1更靠外侧的方式形成了凹部8的结构。而且,凹部8内被底层填料7大致完全填充。在这样的结构的安装结构体21中,无法限制凸缘部7a的扩展区域的扩大。即,想要扩展的凸缘部7a到达凹部8之后才能开始限制其扩展区域的扩大,但在充分远离半导体芯片2的外周端部位置地形成凹部8的结构中,无法限制其扩大。结果,凸缘部7a的倾斜角度更小,以放倒状态形成。
分别制作图1和图2的该第一实施方式的半导体芯片的安装结构体1、11以及图3的比较例的半导体芯片的安装结构体21,在规定的条件下进行了热循环实验。具体而言,每种安装结构体制作100个,对这100个安装结构体在相对湿度为80%以下的气氛中反复进行500次从0℃~80℃的温度变化的循环。然后,确认各个安装结构体中的电连接状态和能否实现导通,测定施加热循环所导致的在半导体芯片的安装结构体中发生剥离或内部破损的不合格个数。另外,实施多组这样的热循环实验。
结果,在图1的该第一实施方式的半导体芯片的安装结构体1中,100个中不合格个数为0~1个左右。另外,在图2的该第一实施方式的半导体芯片的安装结构体11中,100个中不合格个数为1~2个左右。相对于此,在图3的比较例的半导体芯片的安装结构体21中,100个中不合格个数多达10~20个左右。根据这些实验结果可知,在该第一实施方式的半导体芯片的安装结构体中,与比较例相比能充分降低不合格个数。
在图1和图2的该第一实施方式的半导体芯片的安装结构体1、11中,由于形成为使凹部8位于半导体芯片2的外周端部位置P1,因此,能减少凸缘部7a中的树脂的量、即在基板4上配置的凸缘部7a的树脂量。所以,能够降低由热膨胀率差产生的应力负荷,即使在反复实施热循环的情况下也能减少不合格个数。
相对于此,在图3的比较例的半导体芯片的安装结构体21中,由于凹部8的形成位置远离半导体芯片2的外周端部,结果凸缘部7a中的树脂量增多。因此,不能降低应力负荷,在反复实施热循环的情况下容易产生不合格产品。
这样,在该第一实施方式的半导体芯片的安装结构体中,通过在相当于半导体芯片2的外周端部的位置形成凹部,将凸缘部7中本要扩展的树脂导入到凹部内,能够减小扩展区域。从这样的观点出发,凹部内未完全填充树脂能减少凸缘部的树脂量因而优选。另外,凸缘部的倾斜角度增大能减少树脂量因而优选。从这样的观点出发,优选凹部8的内侧方向的端部位置P2位于半导体芯片2的外周端部位置P1的内侧。由此,能降低因热膨胀差等对各部件产生的应力负荷。尤其是,这样的效果在使用Low-k材料的半导体芯片的安装结构体中有效。此外,从这样的凹部8的功能来看,凹部8可以说是树脂扩展区域限制用凹部。
下面,利用图4和图5所示的半导体芯片2和基板4的示意剖视图,对这样的半导体芯片的安装结构体1的制造方法、即向基板4安装半导体芯片2的方法进行说明。
首先,如图4所示,向基板4上由凹部8包围的安装区域配置例如片状的底层填料7。此时,按照底层填料7不进入凹部8内的方式进行底层填料7的配置。此外,也可取代使用这样的片状的底层填料7,而使用半液状的树脂材料。然后,在按照基板4的安装区域内形成的各个基板电极5与焊盘3对置的方式进行了半导体芯片2相对于基板4的定位的状态下,将半导体芯片2隔着底层填料7配置到基板4上。
然后,将装备了由作为弹性材料的一例的硅酮橡胶材料形成的按压部16的压接工具15,定位并配置到基板4上隔着底层填料7配置的半导体芯片2的上方。而后,使压接工具15下降从而使按压部16抵接到半导体芯片2的上表面,并且通过进一步下降来相对基板4按压半导体芯片2。
通过由该按压而施加的按压力,如图5所示,底层填料7沿基板4的表面被按压扩展,向安装区域外扩展。由于在安装区域的周围形成有凹部8,因此这样被按压扩展的底层填料7的一部分进入凹部8,由凹部8限制了向安装区域外扩展的区域。进而,由于在压接工具15上设置的按压部16由硅酮橡胶材料形成,因此在按压的同时其形状发生弹性变形,绕半导体芯片2的周围凹陷,在限制想要向安装区域外扩展的底层填料7的同时,能起到将底层填料7的一部分积极导向凹部8内的作用。结果,在底层填料7的周围形成具有大的倾斜角度的凸缘部7a。
另一方面,通过这样的按压,半导体芯片2上形成的凸块6挤压底层填料7,从而成为与基板4的基板电极5电连接的状态。然后,通过压接工具15加热底层填料7使其热硬化,从而形成如图1所示的半导体芯片的安装结构体1。
此外,在上述的制造方法的说明中,为了更可靠地形成凸缘部7a的形状,对使用具有由弹性材料形成的按压部16的压接工具15的情况进行了说明,但也可不使用这样的压接工具。不过,通过使用具有按压部16的压接工具15,例如,即使在半导体芯片2的外周端部的平面位置上树脂的扩展量存在偏差,也能通过弹性变形的按压部16积极限制树脂的扩展量,从而能够减少扩展的偏差。
(第二实施方式)
此外,本发明并不限定于上述实施方式,也能以其他各种方式实施。例如,图6中表示作为本发明的第二实施方式的半导体元件的安装结构体的一例的半导体芯片的安装结构体31的示意剖视图。此外,在图6的半导体芯片的安装结构体31中,对于与上述第一实施方式的安装结构体1相同结构的构件标注相同标记并省略说明。
如图6所示,该第二实施方式的半导体芯片的安装结构体31在其凹部38的内底部38a形成为倾斜面这一点上,具有与上述第一实施方式的半导体芯片的安装结构体1不同的结构。下面,以该不同结构为主进行说明。
如图6所示,在基板4上的与半导体芯片2的外周端部对置的位置P1形成有凹部38。凹部38具有从其内侧方向的端部位置P2向外侧方向变深地倾斜的内底部38a。该内底部38a形成为在外侧方向的端部位置P3达到最深部。另外,凹部38的内侧方向的端部位置P2配置为比半导体芯片2的外周端部位置P1更靠半导体芯片2的中心侧,外侧方向的端部位置P3配置为比半导体芯片2的外周端部位置P1更靠外侧,在这一点上具有与上述第一实施方式的半导体芯片的安装结构体1同样的配置结构。
在这样的结构的半导体芯片的安装结构体31中,除了上述第一实施方式的半导体芯片的安装结构体所具有的效果之外,还能够在向基板4安装半导体芯片2时,通过倾斜的内底部38a使想要向安装区域的周围扩展的底层填料7顺畅地导入到凹部38内,从而能使树脂具有良好的流动性。通过这样使树脂具有良好的流动性,例如能够使对底层填料7加热而产生的气泡(void)更好地向树脂外部排出,从而能够提高接合的可靠性。另外,通过沿着倾斜的内底部38a顺畅地将树脂导入凹部38内,与例如上述第一实施方式的结构那样未形成倾斜的内底部的情况相比,树脂的流向不会较大地变化,因此能进一步减少变形等的发生。
这里,在图7中表示本第二实施方式的变形例的半导体芯片的安装结构体41的示意剖视图,在图8、图9中表示比较例的半导体芯片的安装结构体51、61的示意剖视图。
首先,图7的变形例的半导体芯片的安装结构体41形成了具有以与图6的凹部38相同的深度D1倾斜的内底部48a的凹部48,但在按照凹部48的内侧方向的端部位置P2与半导体芯片2的外周端部位置P1大致一致的方式配置凹部48这一点,具有与图6的安装结构体31不同的结构。
在这样的结构中,与图6的安装结构体31同样,在凸缘部7a处能降低因热膨胀差而产生的负荷。但是,由于凹部48的容积比凹部38小,因此底层填料7的扩展量不会过大所以优选。
另外,图8的比较例的半导体芯片的安装结构体51以及图9的比较例的半导体芯片的安装结构体61中凹部的配置位置和图6的安装结构体31相同,但其深度或深或浅。
具体而言,在图8的安装结构体51中,凹部58的深度D2设定为比凹部38的深度D1深(例如设定为D2=D1×2)。在这样的结构中,需考虑深度D2的大小和树脂的量,但凹部58的容积过大,凹部58内配置的底层填料7的热膨胀或热收缩可能会对半导体芯片2产生应力负荷从而造成影响。
另外,在图9的安装结构体61中,凹部68的深度D3设定为比凹部38的深度D1浅(例如设定为D3=D1×0.5)。在这样的结构中,需考虑深度D3的大小和树脂的量,但凹部68的容积对于导入扩展的树脂而言并不充分,有时难以有效地使凸缘部7a的倾斜角度变陡。在这种情况下,可能无法充分降低各构件的热膨胀差所产生的应力负荷。
分别制作图6~图9的半导体芯片的安装结构体31、41、51和61,在与上述第一实施方式同样的条件下进行了热循环实验。结果,在图6的该第二实施方式的半导体芯片的安装结构体31中,100个中不合格个数为0个。另外,在图7的该第二实施方式的半导体芯片的安装结构体41中,100个中不合格个数为2~4个左右。相对于此,在图8的比较例的半导体芯片的安装结构体51中,100个中不合格个数多达10~20个左右。另外,在图9的比较例的半导体芯片的安装结构体61中,100个中不合格个数多达5~10个左右。根据这些实验结果可知,在该第二实施方式的半导体芯片的安装结构体中,与比较例相比能充分降低不合格个数。
(第三实施方式)
下面,图10中表示本发明的第三实施方式的半导体芯片的安装结构体71的示意剖视图。如图10所示,该第三实施方式的半导体芯片的安装结构体71具有与图6所示的上述第二实施方式的安装结构体31同样的凹部38的配置结构,但在基板4的安装区域的大致中央附近形成有比其他表面隆起的隆起部79这一点与图6的结构不同。
如图10所示,通过在安装区域的大致中央附近形成了隆起部79,从隆起部79的顶部经凹部38中的倾斜的内底部38a到凹部38的最深部形成了梯度。这样的梯度例如也可从安装区域的中央附近以放射状形成,还可朝向四方形成。另外,这样的梯度并不限于必须连续的情况,也可以是其一部分包括平坦部形成所谓的金字塔状(或阶梯状)。这是由于还存在例如在形成了基板电极5的附近等处无法形成倾斜面的情况。
这样,通过在基板4上从安装区域的大致中央附近到凹部38内设置了下降梯度,能使安装半导体芯片2时被挤压扩展到安装区域外的底层填料7具有良好的流动性,能有效排出气泡等,从而能实现可靠性高的接合。另外,这种良好的流动性,能使树脂积极且有效地导入到凹部38内,并能有效限制凸缘部7a的扩展区域。此外,这样的隆起部79相对于未形成隆起部79的状态的底层填料7的厚度尺寸0.05mm形成为0.015mm~0.025mm左右的高度尺寸。
(第四实施方式)
下面,作为本发明的第四实施方式的半导体芯片的安装结构体,对凹部的平面配置结构的各种方式进行说明。图11~图14中表示该第四实施方式的半导体芯片的安装结构体101、111、121和131的示意俯视图。此外,在以下的说明中,对凹部的平面配置结构进行说明,关于凹部的剖面形状,应用上述第一实施方式~第三实施方式的结构。
首先,在图11的半导体芯片的安装结构体101中,沿半导体芯片2的外周端部在其整个周围形成有凹部108。这样,通过在整个周围形成凹部108,将从外周端部的任意位置扩展的底层填料7导入到凹部108内,从而能可靠地限制扩展区域。
然后,在图12的半导体芯片的安装结构体111中,采用了在半导体芯片2的四个角部分及其附近配置了凹部118的结构。一般,半导体芯片2的角部分由于距半导体芯片2的中心的距离大,因此热膨胀或热收缩引起的应力负荷容易集中。从这样的观点来看,在以降低角部分的应力负荷为主要目的的情况下,这样的结构是有效的。
另外,在图13的半导体芯片的安装结构体121中,采用了在与半导体芯片2的外周端部对置的位置局部形成凹部128的结构。即,在外周端部,凹部128并未连续形成,存在未形成凹部128的部分。根据这样的结构,可利用未形成凹部128的部分作为布线形成位置,能使作为半导体芯片的安装结构体整体的设计变得容易。此外,在这样局部配置的凹部128中,通过将角部分设置在中心能降低应力容易集中的角部分的应力负荷,通过将边部分设置在中心能对与角部分相比树脂的扩展量多的边部分的树脂的扩展区域进行积极限制。
另外,在图14的半导体芯片的安装结构体131中,采用了包括与半导体芯片2的外周端部对置的位置且具有大致椭圆形状的凹部138的配置结构。这样的凹部138的配置结构考虑了底层填料7的实际的流动性,将流动性比较高的边部分的凹部138的宽度尺寸设定得较大,将流动性比较低的角部分的凹部138的宽度尺寸设定得较小。根据这样的结构,在边部分想要大幅扩展的底层填料7能够被具有大容量的凹部138可靠地限制,在容易发生应力集中的角部分也能限制底层填料7的扩展。另外,通过将这样的结构的凹部138与具有由弹性材料形成的按压部16的压接工具15组合使用,能形成大致椭圆形状的凸缘部7a,能整体降低因热膨胀率差等产生的应力负荷。
(第五实施方式)
下面,图20中表示本发明的第五实施方式的半导体芯片的安装结构体201的示意俯视图。另外,图21中表示图20的半导体芯片的安装结构体201中的B-B线剖视图,图22中表示C-C线剖视图。
首先,如图20的示意俯视图所示,在半导体芯片的安装结构体201中,采用了在半导体芯片2的四个角部分配置四个凹部208并且在角部分之间的边部分也配置两个凹部218的结构。
这里,如半导体芯片的安装结构体201的边部分的剖视图(B-B线剖视图)即图21和角部分的剖视图(C-C线剖视图)即图22所示,在角部分形成的凹部208的内底面208a的深度D11比在边部分形成的凹部218的内底面218a的深度D12深。这样,通过使凹部208和218的深度相互不同,能使角部分的凹部208的内底面208a的倾斜角度θ1比边部分的凹部218的内底面218a的倾斜角度θ2大。
在具有这种结构的该第五实施方式的半导体芯片的安装结构体201中,考虑底层填料7的实际的流动性,平缓地形成流动性比较高的边部分的凹部218的内底面218a的倾斜角度θ2,限制底层填料7向凹部218的流动量,并且增大流动性比较低的角部分的凹部208的内底面208a的倾斜角度θ1,能容易地将底层填料7导入到凹部208中,从而在整个半导体芯片的安装结构体201中实现基于底层填料7的可靠密封。
进而,通过采用使角部分的凹部208的深度D11比边部分的凹部218的深度D12大的结构,能使角部分形成的凸缘部7a的倾斜角度θ3比边部分形成的凸缘部7a的倾斜角度θ4大。这样,通过在容易产生应力集中的角部分使凸缘部7a的倾斜角度θ3比较大,能够降低因热膨胀率差等产生的应力负荷。
此外,在图20所示的半导体芯片的安装结构体201中,对角部分的凹部208的内侧端部沿半导体芯片2的角部分的形状形成的情况进行了说明,但本发明并不限定于这种情况。可以取代这种情况,例如如图23的变形例的半导体芯片的安装结构体251的示意俯视图所示,采用凹部258的内底面延伸到角部分的内侧区域的结构。尤其是,由于在角部分的内侧区域大多不形成焊盘3等,因此,通过采用这种结构,能有效利用内侧区域。
此外,通过适当组合上述各实施方式中的任意实施方式,能起到各自所具有的效果。
本发明的半导体芯片的安装结构,通过在相当于半导体芯片的外周端部的基板表面的位置设置凹部,将想要从安装区域扩展的树脂导入,从而能够抑制树脂的扩展区域的扩大,能够减轻因安装时的加热或冷却处理而产生的各构件的热膨胀差和热收缩差、以及相对于安装后的机械负荷的基板的挠曲所导致的半导体芯片中产生的应力负荷,能够避免芯片内部的破损。
关于本发明参照附图对优选实施方式进行了充分说明,但对于本领域技术人员而言自然明了各种变形和修改。这种变形和修改只要不脱离由所附的权利要求书限定的本发明的范围,就应理解为包括在本发明的范围内。
2006年12月26日申请的日本专利申请No.2006-349511号的说明书、附图以及权利要求书所公开的内容引入到本说明书中作为整体进行参照。
Claims (12)
1、一种半导体元件的安装结构体,其特征在于,具备:
具有多个元件电极的半导体元件;
具有多个基板电极的基板;
对上述各个元件电极和基板电极进行连接的多个突起电极;
密封粘接用树脂,其配置在上述半导体元件与上述基板之间,以对上述各个元件电极、基板电极和突起电极进行密封,并对上述半导体元件与上述基板进行粘接;和
凹部,其形成在上述基板的电极形成面上与上述半导体元件的外周端部对置的位置,且在内侧的一部分配置有上述密封粘接用树脂。
2、根据权利要求1所述的半导体元件的安装结构体,其特征在于,
在上述基板上形成的上述凹部,是通过在其内侧配置上述树脂来限制上述树脂向上述基板的与上述半导体元件对置的区域外扩展的扩展区域的树脂扩展区域限制用凹部。
3、根据权利要求1所述的半导体元件的安装结构体,其特征在于,
上述凹部形成为包括上述基板的比与上述半导体元件对置的区域的外周端部靠内侧的区域。
4、根据权利要求1所述的半导体元件的安装结构体,其特征在于,
上述凹部具有按照向上述基板的与上述半导体元件对置的区域的周围变深的方式倾斜的内底部。
5、根据权利要求1所述的半导体元件的安装结构体,其特征在于,
在上述基板的与上述半导体元件对置的区域的中心形成有比上述凹部的开口端部隆起的隆起部,从上述隆起部到上述凹部的内底部设置有下降梯度。
6、根据权利要求1~5中任一项所述的半导体元件的安装结构体,其特征在于,
在与具有大致方形的形状的上述半导体元件的角部对置的位置形成的上述凹部,形成为其内侧的容积比其他位置形成的上述凹部小。
7、根据权利要求1~5中任一项所述的半导体元件的安装结构体,其特征在于,
在上述基板的与上述半导体元件对置的区域的外周端部形成有多个上述凹部。
8、根据权利要求1~5中任一项所述的半导体元件的安装结构体,其特征在于,
在上述基板的与上述半导体元件对置的区域的外周端部的整周连续形成有上述凹部。
9、根据权利要求1~5中任一项所述的半导体元件的安装结构体,其特征在于,
在与具有大致方形的形状的上述半导体元件的角部对置的位置形成的上述凹部,形成为具有比其他位置形成的上述凹部深的内底部。
10、根据权利要求4所述的半导体元件的安装结构体,其特征在于,
在与具有大致方形的形状的上述半导体元件的角部对置的位置形成的上述凹部,形成为具有倾斜角度比其他位置形成的上述凹部的上述内底部的倾斜角度大的上述内底部。
11、一种半导体元件的安装方法,其特征在于,
在半导体元件的安装区域的外周端部形成有凹部的基板的上述安装区域上配置密封粘接用树脂,
隔着上述密封粘接用树脂将上述半导体元件按压到上述基板上,通过各个突起电极对上述半导体元件的各个元件电极与上述基板的各个基板电极进行连接,并且将向上述安装区域外扩展的上述密封粘接用树脂的一部分导入到上述凹部内,限制上述树脂的扩展区域,同时通过上述树脂对上述各个元件电极、基板电极和突起电极进行密封,
然后对上述密封粘接用树脂进行加热使其硬化,将上述半导体元件安装到上述基板上。
12、根据权利要求11所述的半导体元件的安装方法,其特征在于,
利用具有由弹性材料形成的按压部的压接工具通过上述按压部隔着上述密封粘接用树脂将上述半导体元件按压到上述基板上,并且通过上述按压部对向上述安装区域外扩展的上述密封粘接用树脂进行按压将其导入上述凹部内以限制上述树脂的扩展区域,与此同时进行基于上述密封粘接用树脂的密封。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP349511/2006 | 2006-12-26 | ||
JP2006349511 | 2006-12-26 | ||
PCT/JP2007/074844 WO2008078746A1 (ja) | 2006-12-26 | 2007-12-25 | 半導体素子の実装構造体及び半導体素子の実装方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101578695A true CN101578695A (zh) | 2009-11-11 |
CN101578695B CN101578695B (zh) | 2012-06-13 |
Family
ID=39562535
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2007800485532A Expired - Fee Related CN101578695B (zh) | 2006-12-26 | 2007-12-25 | 半导体元件的安装结构体及半导体元件的安装方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US8110933B2 (zh) |
JP (1) | JP5039058B2 (zh) |
CN (1) | CN101578695B (zh) |
WO (1) | WO2008078746A1 (zh) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103081094A (zh) * | 2011-01-27 | 2013-05-01 | 松下电器产业株式会社 | 附带贯通电极的基板及其制造方法 |
CN104112806A (zh) * | 2013-04-17 | 2014-10-22 | 展晶科技(深圳)有限公司 | 发光二极管及其封装结构 |
CN104112739A (zh) * | 2013-04-16 | 2014-10-22 | 展晶科技(深圳)有限公司 | 发光二极管 |
CN106992157A (zh) * | 2015-11-27 | 2017-07-28 | 富士电机株式会社 | 半导体装置 |
CN108321139A (zh) * | 2017-01-10 | 2018-07-24 | 丰田自动车株式会社 | 半导体器件和半导体器件的制造方法 |
CN110349847A (zh) * | 2018-04-08 | 2019-10-18 | 上海新微技术研发中心有限公司 | 一种通过键合材料进行键合的方法和键合结构 |
US10910289B2 (en) | 2016-10-21 | 2021-02-02 | Sony Semiconductor Solutions Corporation | Electronic substrate and electronic apparatus |
CN113038698A (zh) * | 2021-03-08 | 2021-06-25 | 京东方科技集团股份有限公司 | 柔性电路板、显示面板、制备方法和显示装置 |
US11676929B2 (en) | 2016-10-21 | 2023-06-13 | Sony Semiconductor Solutions Corporation | Electronic substrate and electronic apparatus |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5210839B2 (ja) * | 2008-12-10 | 2013-06-12 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
JP5017399B2 (ja) * | 2010-03-09 | 2012-09-05 | 株式会社東芝 | 半導体発光装置および半導体発光装置の製造方法 |
US9484279B2 (en) * | 2010-06-02 | 2016-11-01 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming EMI shielding layer with conductive material around semiconductor die |
US8536718B2 (en) | 2010-06-24 | 2013-09-17 | Stats Chippac Ltd. | Integrated circuit packaging system with trenches and method of manufacture thereof |
JP5246215B2 (ja) * | 2010-07-21 | 2013-07-24 | 株式会社村田製作所 | セラミック電子部品及び配線基板 |
US8617926B2 (en) * | 2010-09-09 | 2013-12-31 | Advanced Micro Devices, Inc. | Semiconductor chip device with polymeric filler trench |
US8546957B2 (en) | 2010-12-09 | 2013-10-01 | Stats Chippac Ltd. | Integrated circuit packaging system with dielectric support and method of manufacture thereof |
CN102563557B (zh) * | 2010-12-30 | 2016-08-17 | 欧司朗股份有限公司 | 用于灯条的封装方法 |
US9355924B2 (en) * | 2012-10-30 | 2016-05-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit underfill scheme |
US9368422B2 (en) * | 2012-12-20 | 2016-06-14 | Nvidia Corporation | Absorbing excess under-fill flow with a solder trench |
CN105190855B (zh) * | 2013-03-13 | 2017-09-19 | 丰田自动车株式会社 | 半导体装置 |
CN103325702A (zh) * | 2013-07-04 | 2013-09-25 | 北京京东方光电科技有限公司 | 芯片的绑定方法及芯片绑定结构 |
JP2017120800A (ja) * | 2015-12-28 | 2017-07-06 | 富士通株式会社 | 半導体素子、半導体素子の製造方法及び電子機器 |
JP2017152484A (ja) * | 2016-02-23 | 2017-08-31 | 京セラ株式会社 | 配線基板 |
JP6678506B2 (ja) * | 2016-04-28 | 2020-04-08 | 株式会社アムコー・テクノロジー・ジャパン | 半導体パッケージ及び半導体パッケージの製造方法 |
CN111316408B (zh) * | 2017-10-30 | 2023-07-18 | 三菱电机株式会社 | 电力用半导体装置以及电力用半导体装置的制造方法 |
JP6905958B2 (ja) * | 2018-06-27 | 2021-07-21 | 京セラ株式会社 | 接着構造、撮像装置、および移動体 |
JP7321009B2 (ja) * | 2019-07-01 | 2023-08-04 | 新光電気工業株式会社 | 配線基板、接合型配線基板及び配線基板の製造方法 |
US11778293B2 (en) * | 2019-09-02 | 2023-10-03 | Canon Kabushiki Kaisha | Mounting substrate to which image sensor is mounted, sensor package and manufacturing method thereof |
KR20210058165A (ko) * | 2019-11-13 | 2021-05-24 | 삼성전자주식회사 | 반도체 패키지 |
JP2022125682A (ja) * | 2021-02-17 | 2022-08-29 | レノボ・シンガポール・プライベート・リミテッド | 電子基板および電子機器 |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0451144A (ja) | 1990-06-19 | 1992-02-19 | Toray Ind Inc | インドメチレン色素系記録材料 |
JPH0451144U (zh) * | 1990-09-03 | 1992-04-30 | ||
JP3233535B2 (ja) * | 1994-08-15 | 2001-11-26 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP2858569B2 (ja) * | 1996-11-25 | 1999-02-17 | 日本電気株式会社 | チップ型デバイスの実装方法及びその実装方法により製造するデバイス |
JPH10270496A (ja) * | 1997-03-27 | 1998-10-09 | Hitachi Ltd | 電子装置、情報処理装置、半導体装置並びに半導体チップの実装方法 |
US6288451B1 (en) * | 1998-06-24 | 2001-09-11 | Vanguard International Semiconductor Corporation | Flip-chip package utilizing a printed circuit board having a roughened surface for increasing bond strength |
JP2000165047A (ja) * | 1998-11-26 | 2000-06-16 | Nippon Carbide Ind Co Inc | プリント配線板の製造方法 |
JP2000188362A (ja) | 1998-12-21 | 2000-07-04 | Kyocera Corp | 半導体素子の実装構造 |
JP2001035886A (ja) | 1999-07-23 | 2001-02-09 | Nec Corp | 半導体装置及びその製造方法 |
US6391683B1 (en) * | 2000-06-21 | 2002-05-21 | Siliconware Precision Industries Co., Ltd. | Flip-chip semiconductor package structure and process for fabricating the same |
JP2002134558A (ja) | 2000-10-25 | 2002-05-10 | Toshiba Corp | 半導体装置及びその製造方法 |
JP3764074B2 (ja) * | 2001-08-03 | 2006-04-05 | 株式会社日立製作所 | 電子機器の製造方法および加工システム |
JP4963148B2 (ja) * | 2001-09-18 | 2012-06-27 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP2003347460A (ja) | 2002-05-28 | 2003-12-05 | Kyocera Corp | 電子装置 |
JP2004214344A (ja) * | 2002-12-27 | 2004-07-29 | Nec Kansai Ltd | 固体撮像装置 |
JP2004266016A (ja) | 2003-02-28 | 2004-09-24 | Seiko Epson Corp | 半導体装置、半導体装置の製造方法、及び半導体基板 |
JP4100213B2 (ja) | 2003-03-25 | 2008-06-11 | 松下電器産業株式会社 | 電子部品実装用の基板および電子部品実装方法 |
TWI315094B (en) * | 2003-04-25 | 2009-09-21 | Advanced Semiconductor Eng | Flip chip package |
JP2004349399A (ja) | 2003-05-21 | 2004-12-09 | Nec Corp | 部品実装基板 |
JP2005109037A (ja) * | 2003-09-29 | 2005-04-21 | Sanyo Electric Co Ltd | 半導体装置 |
US6939751B2 (en) * | 2003-10-22 | 2005-09-06 | International Business Machines Corporation | Method and manufacture of thin silicon on insulator (SOI) with recessed channel |
US7235431B2 (en) * | 2004-09-02 | 2007-06-26 | Micron Technology, Inc. | Methods for packaging a plurality of semiconductor dice using a flowable dielectric material |
US7148560B2 (en) * | 2005-01-25 | 2006-12-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | IC chip package structure and underfill process |
JP4551255B2 (ja) * | 2005-03-31 | 2010-09-22 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP4760361B2 (ja) | 2005-12-20 | 2011-08-31 | ソニー株式会社 | 半導体装置 |
JP2007189005A (ja) | 2006-01-12 | 2007-07-26 | Sharp Corp | 半導体装置の実装構造 |
-
2007
- 2007-12-25 US US12/521,020 patent/US8110933B2/en not_active Expired - Fee Related
- 2007-12-25 JP JP2008551119A patent/JP5039058B2/ja not_active Expired - Fee Related
- 2007-12-25 WO PCT/JP2007/074844 patent/WO2008078746A1/ja active Application Filing
- 2007-12-25 CN CN2007800485532A patent/CN101578695B/zh not_active Expired - Fee Related
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103081094A (zh) * | 2011-01-27 | 2013-05-01 | 松下电器产业株式会社 | 附带贯通电极的基板及其制造方法 |
CN104112739A (zh) * | 2013-04-16 | 2014-10-22 | 展晶科技(深圳)有限公司 | 发光二极管 |
CN104112806A (zh) * | 2013-04-17 | 2014-10-22 | 展晶科技(深圳)有限公司 | 发光二极管及其封装结构 |
CN106992157A (zh) * | 2015-11-27 | 2017-07-28 | 富士电机株式会社 | 半导体装置 |
CN106992157B (zh) * | 2015-11-27 | 2021-10-26 | 富士电机株式会社 | 半导体装置 |
US10910289B2 (en) | 2016-10-21 | 2021-02-02 | Sony Semiconductor Solutions Corporation | Electronic substrate and electronic apparatus |
US11676929B2 (en) | 2016-10-21 | 2023-06-13 | Sony Semiconductor Solutions Corporation | Electronic substrate and electronic apparatus |
CN108321139A (zh) * | 2017-01-10 | 2018-07-24 | 丰田自动车株式会社 | 半导体器件和半导体器件的制造方法 |
CN110349847A (zh) * | 2018-04-08 | 2019-10-18 | 上海新微技术研发中心有限公司 | 一种通过键合材料进行键合的方法和键合结构 |
CN113038698A (zh) * | 2021-03-08 | 2021-06-25 | 京东方科技集团股份有限公司 | 柔性电路板、显示面板、制备方法和显示装置 |
CN113038698B (zh) * | 2021-03-08 | 2022-09-09 | 京东方科技集团股份有限公司 | 柔性电路板、显示面板、制备方法和显示装置 |
Also Published As
Publication number | Publication date |
---|---|
US20100025847A1 (en) | 2010-02-04 |
US8110933B2 (en) | 2012-02-07 |
JPWO2008078746A1 (ja) | 2010-04-30 |
WO2008078746A1 (ja) | 2008-07-03 |
JP5039058B2 (ja) | 2012-10-03 |
CN101578695B (zh) | 2012-06-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101578695B (zh) | 半导体元件的安装结构体及半导体元件的安装方法 | |
US6124546A (en) | Integrated circuit chip package and method of making the same | |
CN103715150B (zh) | 芯片帽及戴有芯片帽的倒装芯片封装 | |
US9087924B2 (en) | Semiconductor device with resin mold | |
US7723839B2 (en) | Semiconductor device, stacked semiconductor device, and manufacturing method for semiconductor device | |
US6545366B2 (en) | Multiple chip package semiconductor device | |
KR100462105B1 (ko) | 수지밀봉형 반도체장치의 제조방법 | |
CN101425486A (zh) | 一种封装结构 | |
KR20050119414A (ko) | 에지 패드형 반도체 칩의 스택 패키지 및 그 제조방법 | |
CN109545754B (zh) | 一种芯片的封装结构、封装方法、显示装置 | |
US10032652B2 (en) | Semiconductor package having improved package-on-package interconnection | |
US6111309A (en) | Semiconductor device | |
CN115995440A (zh) | 半导体封装结构及其制造方法 | |
US8018075B2 (en) | Semiconductor package, method for enhancing the bond of a bonding wire, and method for manufacturing a semiconductor package | |
JP2006294826A (ja) | 半導体装置および半導体装置の製造方法 | |
US6166431A (en) | Semiconductor device with a thickness of 1 MM or less | |
JP2002237566A (ja) | 半導体装置の3次元実装構造体とその製造方法 | |
US12021017B2 (en) | Semiconductor package and manufacturing method thereof | |
CN218632026U (zh) | 一种封装结构及芯片 | |
JP2004228117A (ja) | 半導体装置および半導体パッケージ | |
KR100507131B1 (ko) | 엠씨엠 볼 그리드 어레이 패키지 형성 방법 | |
KR100668848B1 (ko) | 칩 스택 패키지 | |
US20020135056A1 (en) | Semiconductor device and method of manufacturing the same | |
KR19980078349A (ko) | 반도체 패키지 및 그 제조방법 | |
CN115249669A (zh) | 双芯片半导体封装及其制备方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120613 Termination date: 20141225 |
|
EXPY | Termination of patent right or utility model |