CN101527269A - 制造至少两个微电子芯片的组件的方法及设备 - Google Patents
制造至少两个微电子芯片的组件的方法及设备 Download PDFInfo
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Abstract
本发明公开了制造至少两个微电子芯片的组件的方法及设备。所述方法能够形成最初形成在晶片(6)上的芯片(7)的组件。每个芯片包括通过侧面(2)连接的两个平行的主面。至少一个所述侧面包括至少一个用于容纳线状元件(17)的凹槽(3)。首先,将所述晶片粘附到柔性膜(8)上,然后裁切出所述芯片。然后形变所述膜,以使所述芯片(7)相互分离,并使所述凹槽(3)易于接近。然后,通过至少一个线状元件(17)连接所述芯片(7)来形成菊链,通过在所述芯片的所述凹槽(3)中插入线来使每个芯片插入到所述菊链中,然后,从所述形变膜(8)移除所述芯片(7)。
Description
技术领域
本发明涉及一种制造至少两个微电子芯片的组件的方法及设备。
背景技术
目前存在将微电子芯片相互机械并且电气连接的许多技术。传统技术包括一旦芯片已经形成在衬底上并通过锯切分离,则在芯片之间进行刚性机械连接。然后,在形成保护涂层之前,电连接固定在刚性支撑体上的芯片。当芯片的连接极其复杂时,通常使用包括在刚性支撑体上进行连接的该第一方法。然而,该方法具有使用了尤其不适合在柔性结构中集成的刚性机械支撑体的主要缺点。
在文献WO-A-02/084617中描述的第二方法包括在一组纤维或线状元件上集成芯片以形成器件。可通过涂覆实现在纤维中集成芯片。不同的芯片可以通过还能够涂覆或集成在纤维自身中的导电细线相互连接。然而,该文献没有指出在不同的芯片之间导电材料的细线的固定和纤维上的涂敷如何进行。
发明内容
本发明的目的是提供一种以高生产率制造微电子芯片组件的方法。
根据本发明,通过所附的权利要求实现,尤其是通过如下事实实现该目的:在晶片上制作所述芯片,并且每个芯片包括通过侧面连接的两个平行主面,至少一个侧面包括至少一个凹槽,所述方法包括以下连续步骤:
-将晶片粘附到柔性膜上,
-裁切芯片,
-在至少一个芯片的至少一个凹槽附近形变柔性膜以使凹槽易进入,
-在所述芯片的所述凹槽中嵌入线状元件,排列在插入区域中,以及
-在移除区域中,从柔性膜移除芯片。
根据本发明的改进,通过在入口或出口,弯折所述凹槽附近的柔性膜,进行位于输入区域的下行路线的膜的形变。
通过使得至少在输入区域中的膜拉伸的牵引力的应力,实现的膜的形变。
本发明还涉及一种用于制造至少两个微电子芯片的组件的设备,所述芯片制作在晶片上,并且每个芯片包含两个通过侧面连接的平行主面,至少一个侧面包括至少一个凹槽,所述设备包括:
-将晶片粘附到柔性膜上的装置,
-裁切所述芯片的装置,
-在至少一个芯片的至少一个凹槽附近形变柔性膜使凹槽易于接近的装置,
-在排列于插入区域中的所述芯片的所述凹槽中嵌入线状元件的装置,以及
-从移除区域中的柔性膜移除芯片的装置。
附图说明
从如下仅作为非限定的例子给出的并在附图中表示出的本发明具体实施例的说明,其他优点和特点将变得更加清晰明显,其中:
图1到6代表根据本发明能够用于形成菊链(daisy chain)芯片的两个可选实施例。
图7到8示出根据本发生产芯片的菊链的不同步骤。
图9到11示出组装方法的第一实施方式不同变体。
图12到13示出组装方法的第二实施方式的两个变体。
具体实施方式
本发明使用国际专利申请PCT/FR2007/001034中描述的微电子芯片类型,该国际专利申请要求2006年8月29日申请的法国专利申请第0607588的优先权。使用这些芯片构成菊链形式的组件。如图1所示,微电子芯片包括至少一个微电子元件4。微电子芯片具有由形成在芯片边缘的侧面2连接的两个平行的主面1a和1b。侧面2的数量可以改变并且依赖于主面1a和1b轮廓的形状。至少一个侧面包括至少一个凹槽3,其优选地平行于主面1a和1b。以能够插入线状形式元件的方式确定该凹槽的尺寸。
如图2所示,芯片7可以有两个分别制作在两个相对侧面上的凹槽3。每个凹槽分别能够插入线状形式元件。
根据图1和2的芯片还可以是两个微电子元件4或通过间隙物5相连的一个微电子元件4和一个对立板的组件的形式。间隙物的宽度小于所述芯片的宽度,使得在间隙物5的每一侧上能够获得一个凹槽3(图1)或是两个凹槽3(图2)。
一旦线状元件嵌入凹槽中,各个芯片的每个凹槽可以为倾斜的,而线状元件的轴线则保持基本上平行于主面。
可以通过加力执行线状元件的嵌入,然后机械地保持所述元件在适当的位置,或者通过简单的插入执行线状元件的嵌入,其后通过在所述凹槽中粘附线状元件来执行固定。
根据图3和4中所示的芯片的可选实施例,当插入线状元件17时,芯片7的凹槽可弹性形变。然后,通过柔性回复,凹槽压紧线状元件17,则线状元件17被嵌在凹槽3中。有利地,凹槽3可以在其两个纵向末端包括突出元件18,以易于插入线状元件并防止线状元件松动。
优选地,通过承载线的探针9将线状元件引导入到芯片7的凹槽中,探针9将线状元件17引导入到凹槽中和/或在线状元件17上施加压力以迫使线状元件17插入到凹槽3中。线状元件的嵌入可能需要一定的空间,并且因此需要使对于凹槽的接近足够大以使承载线的探针或插入线状元件的任何其他装置通过。
可以通过焊接(soldering)、粘附或者沉积聚合物而将线状元件嵌入到芯片7的凹槽。图5对应于芯片7的俯视图,如图5所示的例子,通过承载线的探针9将线状元件插入凹槽3,并且然后注射器19向凹槽中沉积胶或聚合物以将线状元件17凹密封在凹槽中。
芯片的凹槽可以是导电的,使得当本身导电的线状元件与凹槽电接触时,能够向芯片供电或作为数据总线。出于举例的目的,图6所示的芯片,其凹槽包括至少一个在凹槽3的至少一部分或全部上延伸的电连接焊盘20(例如凸块)。然后,线状元件17可与焊盘20电接触。
为了优化焊盘与线状元件之间的接触,线状元件可以经历电解或密封在导电胶或聚合物中。
根据可选实施例(未示出),线状元件可以部分地插入到凹槽中,并且仅连接两个相邻芯片,通过另一个线状元件执行与另一个芯片连接。
如图7所示,如上所述的微电子芯片7并排制作在硅晶片6上。为了制作芯片的菊链,如图7至13中所示,制造如上所述的至少两个微电子芯片组件的方法包括以下连续步骤:
-将其上制作有芯片7的硅晶片6粘附到柔性膜8上,可以在晶片上制作芯片之前或之后,粘附膜,
-优选地,裁切最初以管芯矩阵形式制作在晶片6上的芯片,但仍旧通过它们所粘附的柔性膜8保持彼此的机械连接。可以用任何合适的方法,例如锯切或者等离子体蚀刻来执行该裁切,
-在至少一个芯片的至少一个凹槽3附近形变柔性膜8以使凹槽3可进入,
-将至少一个线状元件17嵌入到排列在插入区域12中的所述芯片的所述凹槽3中,以及
-在移除区域13中,从柔性膜8移除芯片(例如,卸下芯片)。
可重复最后三步骤直至菊链具有所需长度。
根据改进,插入和移除区域都是相同的。
柔性膜可以是聚合物膜。
根据图9至11中所示的实施例,形变包括在插入区域12的水平,弯折柔性膜,从而允许进入凹槽。因此,通过在邻近沟槽区域弯折柔性膜8来执行位于输入区域10的下行线的柔性膜的形变。
在图9所示的可选实施例中,每个芯片包括排列在由箭头F1指示的柔性膜8行进方向下行线上的凹槽3。为了使线状元件能够插入到两个相邻芯片的凹槽中,形变包括在凹槽3的水平,弯折柔性膜8,从而通过柔性膜的弯折使第一芯片在嵌入区域12的出口摆动,由此为随后放置在插入区域12中的第二芯片7的凹槽3留下自由路径。然后,在插入区域12的位于通过膜8在插入区域12的出口的弯折所形成的断裂的位置,将线状元件17插入到凹槽3中。一旦线状元件17已经插入,柔性膜8前进以将位于插入区域12中的芯片移动到移除区域并将下一个芯片移动到插入区域12上,等等。在图9所示的特定实施例中,在插入区域12的出口,膜8在相对于芯片的行进方向制作了略微超过90度的角。
根据图10所示的可选实施例,每个芯片包括在所述芯片的沿着所述柔性膜行进方向(由箭头F1指示)的上行路线侧上的凹槽。在该可选实施例中,插入区域12相对于输入区域10倾斜。柔性膜在插入区域12的入口处弯折。因此,使其内插入线状元件的芯片7向插入区域摆动,释放凹槽3并使线状元件17能够插入。然后,柔性膜8前进以将下一芯片移动到插入区域12,并且可将在其内插入线状元件的芯片移动到移除区域内(未示出)或是在新的芯片取代它的位置之前从嵌入区域12的水平(1evel)卸下。
根据图11所示的可选实施例,每个芯片包括在两相对侧面上的两个凹槽,在柔性膜8的所述行进方向上,一凹槽位于上行路线和第二凹槽位于下行路线。在该可选实施例中,插入区域12相对于输入区域10倾斜。因此,其内插入两个线状元件的芯片7向插入区域摆动,释放两个凹槽3并使线状元件17能够插入到两个凹槽中。因此,在嵌入区域12的入口处弯折柔性膜8。在芯片传输到插入区域12之前,优选地,卸下先前的芯片,使得位于芯片的行进方向上的下行路线的凹槽空闲。芯片可以在插入区域12中卸下(因此,插入区域12和移除区域相同)。还可以当下一芯片到达插入区域12时,将位于插入区域12中的芯片移动到位于下行路线的移除区域,以使位于所述芯片的行进方向上的下行路线的凹槽空闲。
为了增加芯片的组装速度,该实施例可应用于不止一个芯片,而且可应用于一排芯片,每排芯片连续地从一个区域移动到另一区域。还可以将使用一排芯片应用到所有实施例中。
在图12和13所示的第二实施例中,通过牵引来给柔性膜8施加应力,实现柔性膜8的形变,导致柔性膜至少在输入区域10中被拉伸。一旦柔性膜8当在输入区域10中经过时被拉伸(图7中的箭头方向),在插入区域12的水平,两个相邻芯片间的间距足够允许线状元件和/或承载线的探针9通过。因此,形变区域对应于芯片的输入区域10至插入区域12。
柔性膜8可以是在承受预设的温度时能够拉伸百分之几十的聚合物膜。因此,可以通过牵引和/或加热到使其能够拉伸的温度来给聚合物膜施加应力。在裁切芯片之后,这样的膜能够在芯片之间产生几毫米的间距。例如,可以将施加应力的膜移动到一个加热板11上,优选地温度在80℃和150℃之间,在给定温度下施加的应力能够在凹槽的水平使得芯片相互分开。该间隔有助于承载线的探针9进入凹槽,承载线的探针9协助将线状元件17插入凹槽。
如图12所示,其上粘附有已裁切芯片7的晶片的柔性膜8连续地经过至少两个不同的区域,形成能够增速菊链生产率的生产链。因此,首先将柔性膜移动到可包括加热板11的输入区域10。如果需要,该板11将膜8加热到其拉伸温度以在芯片之间产生间距。当膜移入输入区域10中时,所述间隔变得更大(例如从A变为A’)。然后,将膜8移入凹槽中线状元件17的插入区域12,以及最终到移除区域(未示出)以移除形成菊链的芯片7。移除区域可以与插入区域相同。
根据图13所示的可选实施例,插入区域12包括支撑表面14。有利地,该表面14与加热板11不在同一平面内,以在如果拉伸不足以允许承载线的探针9通过时,有助于承载线的探针9通过。在由加热板11和表面14分别形成的平面的交叉点形成凹角,该角优选地为严格大于180度并严格小于360度。该配置有助于承载线的探针9的移动以及在每个芯片的凹槽中插入线状元件17。
根据该第二实施例及其变体,通过在每个基本步骤中,不再一次仅增加单个芯片,而是一排芯片,可以增速菊链生产率。为此,所述晶片包括多个基本上彼此平行的芯片,并且每排芯片连续地从输入区域10到嵌入区域12经过然后到移除区域13通过。在移除区域13中,在菊链上的简单牵引可足以卸下芯片。
根据适用于不同实施例的改进,通过在移除区域13中使用工具15(图13)降低芯片7或者芯片排与膜8之间粘附表面,提高了每一芯片7或者每排芯片的移除。该工具15可以是刀片或者尖端形式,在每一芯片的中央区域施加压力,而膜8通过移动膜来移动。在图13中为了便于举例的目的,将其上压着膜8的辊16布置在移除区域13的出口处,并且能够使工具15减少芯片粘附到膜的表面,以使芯片容易被移除。
虽然移动膜的装置使膜能够通过牵引而被施加应力,根据图13中所示的所述第二实施例实现,但在输入区域10、插入区域12和移除区域13中,牵引力基本上保持不变。当膜通过加热板11或者单纯的被牵引拉伸时,牵引力能够在输入区域10中使得获得的间距从A到A’。
在移除步骤之后,菊链的空闲部分可以跟随使得能够进行各种处理操作的路径,例如加强线状元件与芯片之间的连接的电解、或者涂敷胶,聚合物等。
每个连接所述芯片以形成菊链的线状元件17可具有几微米的直径,优选地在10μm和300μm之间,适合芯片凹槽的尺寸。线状元件17可以是金属,优选地由银、金等类型至少一种的金属导体形成。有利地,线状元件还可以为由其中至少一个是导电的几个基线构成的股的形式。然后,芯片的凹槽可以作为电连接端子、数据总线等。
另外,芯片还可以在它们的顶部和/或底部的表面集成连接区域,从而增加可能连接的数量,或当以菊链的形式组件时提高它们的机械强度。
线状元件可以是贡献于机械强度的聚合物绝缘线,或涂敷有导电材料的纺织纤维。
线状元件可是中空的,从而使流体,优选的为液体或气体能够在由线的内径形成的通道中流动。通道内流体的流动例如可以对形成菊链的多个芯片进行冷却。散热系统的使用则使得在菊链中能够集成在更高的频率下工作的、更复杂的芯片。
根据上述方法获得的菊链微电子芯片特别地使得多个芯片能够执行精确的共同功能或与织物相关的特别功能。芯片可以是RFID(射频识别)型,连接它们的金属线则能够作为天线,特别是提供电源。
本发明不局限于上述实施例。特别地,可以连接来自不同衬底的不同类型芯片。
一种制造一个晶片上生产的至少两个微电子芯片的组件的装置,每个芯片7包括通过侧面2连接的两个平行主面1a和1b。至少一个侧面2包括至少一个凹槽3,所述装置包括:
-将晶片6粘附到柔性膜8上的装置,
-裁切所述芯片7的装置,
-在至少一个芯片的至少一个凹槽附近形变所述柔性膜使所述凹槽容易接近的装置,
-在所述芯片的所述凹槽3内插入线状元件17的装置,以及
-在移除区域中,从所述柔性膜移除所述芯片的装置,所述线状元件被嵌入到所述芯片中。
Claims (12)
1.一种制造至少两个微电子芯片的组件的方法,其特征在于:在晶片(6)上制造所述芯片,并且每个芯片(7)包括通过侧面(2)连接的两个平行的主面(1a,1b),至少一个所述侧面(2)包括至少一个凹槽(3),所述方法包括以下连续步骤:
-将晶片(6)粘附到柔性膜(8)上,
-裁切所述芯片(7),
-在至少一个芯片的至少一个凹槽附近形变所述柔性膜使所述凹槽(3)易于接近,
-在排列在插入区域(12)中的所述芯片的所述凹槽(3)内嵌入线状元件(17),以及
-在移除区域(13)中从所述柔性膜移除所述芯片。
2.根据权利要求1所述的方法,其特征在于,通过弯折接近所述凹槽的所述柔性膜来实现位于输入区域(10)下行路线的所述膜(8)的形变。
3.根据权利要求2所述的方法,其特征在于,在所述插入区域(12)的入口弯折所述膜(8)。
4.根据权利要求2所述的方法,其特征在于,在所述插入区域(12)的出口弯折所述柔性膜(8)。
5.根据权利要求1所述的方法,其特征在于,通过使得至少在输入区域(10)中的所述膜(8)被拉伸的牵引力的应力,实现所述膜(8)的形变。
6.根据权利要求5所述的方法,其特征在于,所述输入区域(10)配置有加热板(11)。
7.根据权利要求1至6中任一权利要求所述的方法,其特征在于,所述插入区域(12)和移除区域(13)相同。
8.根据权利要求1至6中任一权利要求所述的方法,其特征在于,所述柔性膜(8)是聚合物膜。
9.根据权利要求1至6中任一权利要求所述的方法,其特征在于,每个芯片(7)包括分别设置在两个相对侧面(2)上的两个凹槽(3),通过两条线连接两个相邻芯片,通过承载线的探针(9)将所述线插入到所述凹槽(3)中。
10.根据权利要求1至6中任一权利要求所述的方法,其特征在于,晶片由多排芯片形成,每排从一个区域连续地通过至另一区域。
11.根据权利要求1至6中任一权利要求所述的方法,其特征在于,所述移除区域(13)包括由刀片或者至少一尖端形成的移除工具(15)。
12.一种制造至少两个微电子芯片的组件的设备,其特征在于:在晶片(6)上制作所述芯片,并且每个芯片(7)包括通过侧面(2)连接的两个平行的主面(1a,1b),至少一个所述侧面(2)包括至少一个凹槽(3),所述装置包括:
-将晶片(6)粘附到柔性膜(8)上的装置,
-裁切所述芯片(7)的装置,
-在至少一个芯片的至少一个凹槽附近弯折所述柔性膜使所述凹槽易于接近的装置,
-在排列于插入区域(12)中的所述芯片的所述凹槽(3)中嵌入线状元件(17)的装置,以及
-在移除区域中从所述柔性膜移除所述芯片的装置。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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FR08/01234 | 2008-03-06 | ||
FR0801234A FR2928491A1 (fr) | 2008-03-06 | 2008-03-06 | Procede et dispositif de fabrication d'un assemblage d'au moins deux puces microelectroniques |
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CN101527269A true CN101527269A (zh) | 2009-09-09 |
CN101527269B CN101527269B (zh) | 2012-07-25 |
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CN200880127846.4A Expired - Fee Related CN101960585B (zh) | 2008-03-06 | 2008-10-21 | 包括导线元件和带槽的微电子芯片并包括保持该导线元件的至少一个凸块的组件 |
CN2009101346129A Expired - Fee Related CN101527269B (zh) | 2008-03-06 | 2009-03-06 | 制造至少两个微电子芯片的组件的方法及设备 |
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CN200880127846.4A Expired - Fee Related CN101960585B (zh) | 2008-03-06 | 2008-10-21 | 包括导线元件和带槽的微电子芯片并包括保持该导线元件的至少一个凸块的组件 |
Country Status (9)
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US (2) | US8723312B2 (zh) |
EP (2) | EP2250667B1 (zh) |
JP (2) | JP5341114B2 (zh) |
CN (2) | CN101960585B (zh) |
AT (1) | ATE467900T1 (zh) |
DE (1) | DE602009000024D1 (zh) |
ES (1) | ES2346274T3 (zh) |
FR (1) | FR2928491A1 (zh) |
WO (1) | WO2009112644A1 (zh) |
Cited By (5)
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CN102110677A (zh) * | 2009-12-23 | 2011-06-29 | 原子能和代替能源委员会 | 配线元件与电子芯片的装配方法 |
CN102263010A (zh) * | 2010-05-25 | 2011-11-30 | 原子能和代替能源委员会 | 将芯片器件装配在线上的设备 |
CN103080392A (zh) * | 2010-06-24 | 2013-05-01 | 原子能和代替能源委员会 | 铠装线内芯片元件的容纳 |
JP2019033266A (ja) * | 2012-09-17 | 2019-02-28 | コミッサリア ア レネルジー アトミーク エ オ エナジーズ アルタナティブス | 溝付き及びチップ付きデバイス用のキャップ、キャップを装備するデバイス、デバイスと配線要素のアセンブリ、及びその製造方法 |
WO2020237708A1 (zh) * | 2019-05-30 | 2020-12-03 | 上海新微技术研发中心有限公司 | 硅光芯片的测试方法及设备 |
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-
2008
- 2008-03-06 FR FR0801234A patent/FR2928491A1/fr not_active Withdrawn
- 2008-10-21 EP EP08873297.9A patent/EP2250667B1/fr not_active Not-in-force
- 2008-10-21 WO PCT/FR2008/001476 patent/WO2009112644A1/fr active Application Filing
- 2008-10-21 CN CN200880127846.4A patent/CN101960585B/zh not_active Expired - Fee Related
- 2008-10-21 JP JP2010549171A patent/JP5341114B2/ja not_active Expired - Fee Related
- 2008-10-21 US US12/919,512 patent/US8723312B2/en active Active
-
2009
- 2009-02-19 US US12/379,357 patent/US8012795B2/en not_active Expired - Fee Related
- 2009-02-20 AT AT09354009T patent/ATE467900T1/de active
- 2009-02-20 EP EP09354009A patent/EP2099060B1/fr active Active
- 2009-02-20 DE DE602009000024T patent/DE602009000024D1/de active Active
- 2009-02-20 ES ES09354009T patent/ES2346274T3/es active Active
- 2009-03-05 JP JP2009052290A patent/JP5378011B2/ja not_active Expired - Fee Related
- 2009-03-06 CN CN2009101346129A patent/CN101527269B/zh not_active Expired - Fee Related
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102110677A (zh) * | 2009-12-23 | 2011-06-29 | 原子能和代替能源委员会 | 配线元件与电子芯片的装配方法 |
CN102110677B (zh) * | 2009-12-23 | 2016-03-30 | 原子能和代替能源委员会 | 配线元件与电子芯片的装配方法 |
CN102263010A (zh) * | 2010-05-25 | 2011-11-30 | 原子能和代替能源委员会 | 将芯片器件装配在线上的设备 |
CN102263010B (zh) * | 2010-05-25 | 2016-03-02 | 原子能和代替能源委员会 | 将芯片器件装配在线上的设备 |
CN103080392A (zh) * | 2010-06-24 | 2013-05-01 | 原子能和代替能源委员会 | 铠装线内芯片元件的容纳 |
CN103080392B (zh) * | 2010-06-24 | 2015-11-25 | 原子能和代替能源委员会 | 铠装线内芯片元件的容纳 |
JP2019033266A (ja) * | 2012-09-17 | 2019-02-28 | コミッサリア ア レネルジー アトミーク エ オ エナジーズ アルタナティブス | 溝付き及びチップ付きデバイス用のキャップ、キャップを装備するデバイス、デバイスと配線要素のアセンブリ、及びその製造方法 |
WO2020237708A1 (zh) * | 2019-05-30 | 2020-12-03 | 上海新微技术研发中心有限公司 | 硅光芯片的测试方法及设备 |
Also Published As
Publication number | Publication date |
---|---|
JP2011513980A (ja) | 2011-04-28 |
CN101527269B (zh) | 2012-07-25 |
US8012795B2 (en) | 2011-09-06 |
JP5378011B2 (ja) | 2013-12-25 |
EP2099060A1 (fr) | 2009-09-09 |
ES2346274T3 (es) | 2010-10-13 |
US8723312B2 (en) | 2014-05-13 |
JP5341114B2 (ja) | 2013-11-13 |
CN101960585A (zh) | 2011-01-26 |
DE602009000024D1 (de) | 2010-06-24 |
EP2250667B1 (fr) | 2013-04-24 |
US20090227069A1 (en) | 2009-09-10 |
EP2099060B1 (fr) | 2010-05-12 |
JP2009218590A (ja) | 2009-09-24 |
CN101960585B (zh) | 2014-07-16 |
EP2250667A1 (fr) | 2010-11-17 |
US20110001237A1 (en) | 2011-01-06 |
WO2009112644A1 (fr) | 2009-09-17 |
FR2928491A1 (fr) | 2009-09-11 |
ATE467900T1 (de) | 2010-05-15 |
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