CN102891127A - 电子部件 - Google Patents

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Publication number
CN102891127A
CN102891127A CN2012102503580A CN201210250358A CN102891127A CN 102891127 A CN102891127 A CN 102891127A CN 2012102503580 A CN2012102503580 A CN 2012102503580A CN 201210250358 A CN201210250358 A CN 201210250358A CN 102891127 A CN102891127 A CN 102891127A
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China
Prior art keywords
carrier
chip
electronic unit
carrier surface
semiconductor chip
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CN2012102503580A
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CN102891127B (zh
Inventor
K.霍赛尼
F-P.卡尔茨
J.马勒
M.门格尔
K.施密特
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

一种电子部件包括导电载体。所述导电载体包括载体表面并且半导体芯片包括芯片表面。所述载体表面和所述芯片表面中的一个或二者包括非平面结构。所述芯片被附着到所述载体，芯片表面面向所述载体表面，使得由于所述载体表面与所述第一芯片表面中的一个或二者的所述非平面结构的原因在所述芯片表面与所述载体表面之间提供间隙。所述电子部件进一步包括位于所述间隙中的第一电沉积金属层。

Description

电子部件
技术领域
本发明涉及一种电子部件和一种用于制造电子部件的方法。
背景技术
当半导体芯片被安装到例如引线框架的导电载体上时，由于半导体材料和载体材料的不同的热膨胀系数的原因问题可能出现。特别地，如果在半导体芯片到载体上的安装处理期间，例如在焊接处理(T = 380℃)中或者在粘合处理(T = 200℃)中特定的升高温度被施加到组件，由于不同的热膨胀系数的原因非常高的热机械应力可能出现。在减薄的半导体芯片的情况下由于撕裂和裂缝的形成这些应力反应甚至可以导致半导体芯片的宏观损伤。在其它情况下应力可以导致半导体衬底的强形变，使得后面的处理步骤不再是可能的，例如，激光震颤（laser thrilling）、层压成形、引线结合等。一般而言，在半导体芯片中生成的应力严重地影响后面的处理步骤的可靠性。
附图说明
附图被包括来提供实施例的进一步理解且被并入并且构成本说明书的一部分。附图图示了实施例并且与描述一起用来解释实施例的原理。将容易地了解其它实施例和实施例的许多预定优点，因为通过参考以下的具体描述它们变得更好理解。附图的元素不必相对于彼此按比例绘制。相同的附图标记表示对应的相似部分；
图1示出了根据一个实施例的电子部件的示意截面侧视图表示；
图2A、2B示出了根据一个实施例的电子部件的示意顶视图表示(图2A)和沿着线B-B的示意截面侧视图表示(图2B)；
图3示出了根据一个实施例的电子部件的示意截面侧视图表示；
图4示出了根据一个实施例的电子部件的示意截面侧视图表示；
图5示出了根据一个实施例的用于制造电子部件的方法的流程图；
图6示出了根据一个实施例的用于制造电子部件的方法的流程图；以及
图7A-7F示出根据一个实施例的中间产品的示意顶视图表示以说明用于制造电子部件的方法。
具体实施方式
现参考附图对各方面和实施例进行描述，其中相同的附图标记通常被利用来在所有图中指代相同的元素。在以下描述中，为了解释的目的，陈述了许多细节以便提供实施例的一个或多个方面的完全理解。然而，对本领域的技术人员显而易见的是，实施例的一个或多个方面可以使用更少程度的细节来实现。在其它实例中，已知的结构和元素被以示意的形式示出以便帮助描述实施例的一个或多个方面。应当理解的是，在不背离本发明的范围的情况下可以利用其它的实施例并且可以进行结构上的或逻辑上的变化。应该进一步注意到附图未按比例绘制或者不必按比例绘制。
此外，虽然可以相对于若干实施方式中的仅一个公开实施例的特定特征或方面，但是这样的特征或方面可以按照所期望的并且对任何给定的或特定的应用有利的那样与其它的实施方式的一个或多个特征或方面组合。另外，如果术语“包括”、“具有”、“含有”或其其它变体被用在具体描述或权利要求中，则这样的术语旨在以类似于术语“包含”的方式进行包括。可以使用术语“耦合”或“连接”以及派生词。应该理解的是，这些术语可以被用来指示两个元素合作或者彼此交互而不管它们是否处于直接的物理或电接触，或者它们彼此未直接接触。同样地，术语“示例性的”仅仅意指示例，而不是最佳的或最优的。因此，以下的具体描述未在限制意义上采用，并且本发明的范围由所附权利要求限定。
电子部件和用于制造电子部件的方法的实施例可以使用各种类型的半导体芯片或在半导体芯片中合并的电路，其中有逻辑集成电路、模拟集成电路、混合信号集成电路、传感器电路、MEMS(微电子机械系统)、功率集成电路、具有集成无源器件的芯片等。实施例也可以使用包括MOS晶体管结构或垂直晶体管结构的半导体芯片，所述结构例如IGBT(绝缘栅双极型晶体管)结构，或者一般而言，其中至少一个电接触垫被布置在半导体芯片的第一主面上并且至少一个其它电接触垫被布置在与半导体芯片的第一主面相对的半导体芯片的第二主面上的晶体管结构。
在若干实施例中层或层堆叠被施加到彼此，或者材料被施加或者沉积到层上。应该了解的是，如“施加”或“沉积”这样的术语旨在字面上覆盖将层施加到彼此之上的所有种类和技术。特别地，它们旨在覆盖其中层被作为整体施加一次的技术（例如层压技术）以及其中层被以顺序方式沉积的技术（例如溅射、电镀、模塑法、CVD等）。
半导体芯片可以包括在它们的一个或多个外表面上的接触元件或接触垫，其中接触元件用于电接触半导体芯片。接触元件可以具有任何希望的形式或形状。例如，它们能够具有平台（land）（即半导体封装的外表面上的平接触层）的形式。例如，接触元件或接触垫可以由任何导电材料制成，例如由诸如铝、金、或铜之类的金属或金属合金或导电有机材料或导电半导体材料制成。
在权利要求中和在以下描述中，用于制造电子部件的方法的不同的实施例被描述为特别是在流程图中的处理或措施的特定序列。应当注意的是，实施例不应该限于所描述的特定序列。也能够同时地或以任何其它有用的和适当的序列来实施所有不同的处理或措施或其中特定的一些。
下文中所示出和描述的各种实施例以以下原理优点为特征：
- 最小管芯附着层厚度为“0”，意指不必使用粘合层使得管芯附着层厚度几乎为零；
- 芯片与引线框架或载体之间最小的热机械应力；
- 在管芯附着之后载体或引线框架的最小弯曲；
- 通过粘合或焊接避免任何额外的管芯附着处理；
- 在载体或引线框架的表面上并行芯片附着和层的制造；以及
- 芯片与载体之间改进的热和电连接。
参考图1，根据一个实施例示出了电子部件的示意截面侧视图表示。图1的电子部件10包括包含载体表面2A的导电载体2和包含芯片表面1A的半导体芯片1。半导体芯片1附着到导电载体2，其中芯片表面1A面向载体表面2A，使得由于载体表面2A和芯片表面1A中的一个或它们二者的非平面结构的原因在芯片表面1A与载体表面2A之间提供间隙。电子部件10进一步包括位于间隙中的第一电沉积金属层3。
第一电沉积金属层3直接在芯片表面1A与载体表面2A之间延伸并且是导电的。进一步，第一电沉积金属层3能够通过特征微结构并且通过其纹理和结晶完整性在结构上识别，生长机制和方向可以根据该特征微结构来识别。第一电沉积金属层3因此能够与由诸如溅射或热蒸发或化学汽相沉积之类的其它沉积技术形成的金属层区分开来，并且与由通常通过滚压所形成的金属片提供的金属层区分开来。第一电沉积金属层3也能够在结构上与由软焊（soft solder）或扩散焊（diffusion solder）形成的金属层区分开来。第一电沉积金属层3可以是无锡的并且没有软焊和扩散焊。电沉积金属层的连接结构也可以是无锡的并且没有软焊和扩散焊。
第一电沉积金属层3位于芯片表面1A与载体表面2A之间的间隙中，并且直接从芯片表面1A延伸到载体表面2A。第一电沉积金属层3与芯片表面1A和载体表面2A中的每一个之间的界面没有进一步的粘合剂、包括软焊的基于焊料的材料以及在扩散焊处理期间形成的中间金属相。此界面结构还使第一电沉积金属层3能够与诸如例如扩散焊结合之类的其它的导电连接结构区分开来，该扩散焊结合也可以通过电沉积来沉积但是然后要经历进一步的热处理以产生该结合。电子部件10的芯片表面1A和载体表面2A与第一电沉积金属层3之间的界面没有由第一电沉积金属层3与毗邻表面的材料之间的反应所产生的中间金属相。
根据图1的电子部件10的一个实施例，第一电沉积金属层3可以包括金属或合金，并且可以基本上由银、铜、镍、银基合金、铜基合金以及镍基合金（例如银镍基合金）构成。
根据图1的电子部件10的一个实施例，非平面结构归因于芯片表面1A或载体表面2A中的一个或多个的表面粗糙度。如图1中图示的那样，表面粗糙度可以是例如在导电载体2的制造之后获得的导电载体2的载体表面2A的自然表面粗糙度。根据其实施例，非平面结构归因于载体表面2A的表面粗糙度，其中表面粗糙度特征在于大于3μm的凹陷平均深度。
根据图1的电子部件10的一个实施例，非平面结构归因于芯片表面1A和载体表面2A中的一个或多个的人工表面处理。根据其实施例，人工表面处理使得人工生成的凹陷的平均深度在从1μm - 100μm的范围内。例如，人工表面处理可以包括例如刮擦载体表面2A等的人工表面粗糙化。可以在某种程度上执行这种人工粗糙化使得多个规则地间隔的或不规则地间隔的凹槽被生成在载体表面2A中。还能够执行人工粗糙化使得生成具有相等或者不同地间隔的任意形式和形状的凹陷的规则的或不规则的表面结构。例如，能够通过将规则和相等地间隔的凹陷蚀刻到芯片表面1A和载体表面2A中的一个或多个中来执行人工表面处理。特别地，例如凹陷和隆凸（elevation）的网格图案（checkered pattern）这样的预定图案能够被形成到芯片表面1A中。人工表面处理的另一可能性在于将例如立方体、球或金字塔等规则或不规则布置的隆凸沉积到载体表面2A上。这样的隆凸能够具有从1 μm - 100 μm范围内的平均直径。
根据图1的电子部件10的一个实施例，导电载体2包括引线框架或由引线框架组成。
根据图1的电子部件10的一个实施例，半导体芯片1包括面向导电载体2的金属化层(未示出)。金属化层将被示出在进一步的实施例中的一个中。根据其实施例，能够人工地处理半导体芯片1的芯片表面1A以便在其中获得非平面结构（如之前所描述的那样），并且然后金属化层被施加到结构化的芯片表面1A。例如，金属化层能够是和半导体芯片1合并在一起的器件的电极中的一个或者能够与所述电极中的一个连接，并且一个或多个其它的电极能够被布置在与芯片表面1A相对的半导体芯片1的另一主表面上。
根据图1的电子部件10的一个实施例，第二电沉积金属层5位于横向地在半导体芯片1旁边的载体表面2A上（尤其是在半导体芯片1的所有四周）。根据其实施例，芯片表面1A与第二电沉积金属层5的表面共面。根据其进一步的实施例，第一电沉积金属层3和第二电沉积金属层5由同一种金属材料制成。特别地，在同一个制造步骤中制造第一电沉积金属层3和第二电沉积金属层5。
根据图1的电子部件10的一个实施例，导电载体2 包括从载体表面2A延伸到另一载体表面的一个或多个通孔(未示出)。特别地，通孔从载体表面2A延伸到与载体表面2A相对的载体表面。
参考图2A、2B，示出了根据一个实施例的电子部件的示意顶视图表示(图2A)和沿着线B-B的示意截面侧视图表示(图2B)。图2A、2B的电子部件20包括包含载体表面22A的导电载体22和包含芯片表面21A的半导体芯片21。半导体芯片21附着到载体22，其中芯片表面21A面向载体表面22A，使得间隙被提供在芯片表面21A与载体表面22A之间。根据图2A、2B的实施例，间隙归因于芯片表面21A的非平面结构。电子部件20进一步包括位于间隙中的第一电沉积金属层23。
根据图2A、2B的电子部件20的一个实施例，芯片表面21A的非平面结构由能够在图2A中清楚看出的规则的网格图案构成。网格图案包括白色区域和阴影线区域，其中在阴影线区域中凹陷被蚀刻到芯片表面21A（例如硅表面）中，其中在白色区域中芯片表面21A被原样留下。白色区域和阴影线区域能够具有相等的大小，即相等长度的侧边。然而，也能够制造不同面积和大小的白色区域和阴影线区域。在阴影线区域中形成的凹陷能够在图2B的截面中看见，并且具有在从1 μm - 100 μm的范围内的深度，尤其是具有在从5 μm - 50 μm的范围内的深度。凹陷能够被通过各向同性蚀刻形成到半导体表面中。在图2B的截面视图中载体表面22A被示出为几乎是平的，即没有显著的表面结构。然而，实际上也可以存在一定微观尺度的粗糙度，使得在电沉积的步骤期间第一金属层也沉积到位于半导体芯片21周围的凹陷中。特别地应当注意的是，凹陷不必相对于与它们的垂直尺寸相关的它们的横向尺寸示出成按比例绘制。凹陷的横向尺寸能够在从100 μm - 2 mm的范围内，并且凹陷之间的距离能够在相同的范围内。
参考图3，示出了根据一个实施例的电子部件的示意截面侧视图表示。图3的电子部件30包括包含载体表面32A的导电载体32和包含芯片表面31A的半导体芯片31，其中半导体芯片31被附着到载体32使得芯片表面31A面向载体表面32A。电子部件30进一步包括位于芯片表面31A与载体表面32A之间的至少两个间隔件34，从而在芯片表面31A与载体表面32A之间提供间隙。电子部件30进一步包括在间隙中提供的第一电沉积金属层33。
根据图3的电子部件30的一个实施例，间隔件34位于半导体芯片31的拐角附近。特别地，根据其实施例，电子部件30包括位于半导体芯片31的四个拐角附近的四个间隔件。
根据图3的电子部件30的一个实施例，间隔件34由焊料材料、粘合材料以及电介质材料中的一个或多个制成。
根据图3的电子部件30的一个实施例，半导体芯片31包括面向载体32的金属化层36。金属化层36被施加到半导体芯片31的外部并且直接地接触第一电沉积金属层33。
根据图3的电子部件30的一个实施例，第二电沉积金属层35位于横向地在半导体芯片31旁边的载体表面32A上。特别地，第二电沉积金属层35位于在半导体芯片31的所有四周的载体表面32A上。根据其实施例，芯片表面31A与第二电沉积金属层35的表面共面。
根据图3的电子部件30的一个实施例，间隔件34的直径在从0.5 μm - 50 μm，更特别地从2 μm - 20 μm的范围内。间隔件34能够具有球或圆球的形式。可替换地，间隔件34也能够具有例如靠近半导体芯片31的芯片表面31A的相对的侧边或靠近半导体芯片31的芯片表面31A的所有侧边延伸的条状拉长的隆凸的形式。
根据图3的电子部件30的一个实施例，载体32包括从载体表面32A延伸到另一载体表面，尤其是到与载体表面32A相对的表面的一个或多个通孔(未示出)。
参考图4，示出了根据一个实施例的电子部件的示意截面侧面。电子部件40包括包含载体表面42A的导电载体42和包含芯片表面41A的半导体芯片41，其中芯片41被附着到载体42使得芯片表面41A面向载体表面42A。间隙被提供在芯片表面41A与载体表面42A之间，其中间隙能够由如在先前的实施例中所描述的机制中的任何一个生成。载体42包括从载体表面42A向下延伸到与载体表面42A相对的表面的多个通孔42B。电子部件40进一步包括在间隙中提供的第一电沉积金属层43。电子部件40进一步包括位于横向地在芯片41旁边的载体表面42A上的第二电沉积金属层45。通孔42B用来协助电沉积间隙中的第一金属层43和第二电沉积金属层45的处理。通孔42B能够具有拉长的狭缝的形式或者，可替换地具有基本上环形截面的孔的形式。通孔42B也能够使用在电沉积步骤期间沉积的金属材料来填充。
迄今为止已经示出并且描述了不同的实施例，这些实施例均示出了将半导体芯片附着到导电载体的特定方式。这些实施例特征在于以下优点。不必使用粘合层使得管芯附着层厚度几乎为零。另外，在半导体芯片与载体之间存在最小的热机械应力。在半导体芯片已经被附着到引线框架之后还存在引线框架的最小的弯曲。不存在如焊接或粘合的管芯附着处理（其可能导致在本申请的开头部分所描述的困难）。另外，第一金属层能够与被沉积在导电载体（例如引线框架）上的其它任意地方的第二金属层并行地电沉积。在这点上应当注意的是，这样的金属层通常被施加到引线框架上以便增强其电属性和关于与引线结合的连接的其它属性等等。另外，上述的实施例允许在半导体芯片与载体之间提供改进的热和电连接。
参考图5，示出了根据一个实施例的用于制造电子部件的方法的流程图。提供包括载体表面的导电载体(s1)。提供包括芯片表面的半导体芯片(s2)，其中，载体表面和芯片表面中的一个或它们二者包括非平面结构。芯片被附着到载体，其中芯片表面面向载体表面，使得由于载体表面和芯片表面中的一个或它们二者的非平面结构的原因在芯片表面与载体表面之间提供间隙(s3)。第一金属层被电沉积在间隙中(s4)。
根据图5的方法的一个实施例，载体表面和芯片表面中的一个或多个被处理以获得非平面结构。根据其进一步的实施例，处理可以包括两个表面中的一个或多个的人工粗糙化，取决于处理的方式其可以导致规则的表面结构或不规则的表面结构。根据另一实施例处理包括在载体表面和第一芯片表面中的一个或多个中形成凹陷和隆凸的规则图案（尤其是网格图案）。特别地，半导体芯片由硅芯片构成，并且凹陷的网格图案被蚀刻到第一硅芯片表面中。网格图案能够是诸如先前结合图4中所示出的实施例所描述的。
根据图5的方法的一个实施例，方法进一步包括在和沉积第一金属层的同时在横向地在芯片旁边的载体表面上电沉积第二金属层。特别地，第二金属层被电沉积在第一载体表面上芯片的所有四周。第二金属层能够是和第一金属层相同的金属材料，并且其能够被形成为与第一金属层相连接。
根据图5的方法的一个实施例，将芯片附着到载体能够通过在芯片表面上施加粘合带并且向载体按压芯片使得芯片表面粘合到第一载体表面来执行。粘合带能够呈薄的条带的形式，其附着到芯片表面上或在靠近芯片的一个侧边或芯片的两个相对的侧边或芯片的所有四个侧边的位置附着到载体表面上。随后执行电沉积第一金属层的步骤，同时芯片借助于粘合带粘合到载体。粘合带随后能够被留在芯片与载体之间，或者其也能够通过适当的方式移除。
根据图5的方法的一个实施例，将芯片附着到载体通过应用专门的夹紧机构将芯片夹到载体来执行，其中夹紧机构在将第一金属层电沉积到间隙中之后被移除。
图6示出了根据一个实施例的用于制造电子部件的方法的流程图。在此实施例中，提供了包括载体表面的导电载体(s10)和包括芯片表面的半导体芯片(s20)。在芯片表面与载体表面之间提供至少两个间隔件(s30)。芯片被附着到载体使得芯片表面面向第一载体表面，从而在芯片表面与载体表面之间提供间隙(s40)。第一金属层是在间隙中电沉积的第一金属层(s50)。
根据图6的方法的一个实施例，该方法进一步包括通过将间隔件层施加到芯片表面上并且选择性地移除间隔件层使得至少两个间隔件被留下来形成至少两个间隔件。
根据图6的方法的一个实施例，以球、圆球、立方体或金字塔的形式提供至少两个间隔件。根据另一实施例，间隔件呈具有矩形的形状的截面的拉长的条带、半球、立方体或金字塔的形式。
根据图6的方法的一个实施例，至少两个间隔件由焊料材料、粘合材料或电介质材料制成。
根据图6的方法的一个实施例，该方法进一步包括在晶片级（即，在半导体芯片仍然是包括多个半导体芯片的半导体晶片的一部分并且与其相连接的时候）形成至少两个间隔件。根据其进一步的实施例，间隔件层被施加到半导体晶片上，并且随后，间隔件层被选择性地移除使得在包含在半导体晶片内的每个半导体芯片上留下至少两个间隔件，或者更特别地，留下靠近每个半导体芯片的四个拐角的四个间隔件。在形成间隔件之前能够将金属化层施加到半导体晶片的表面上，即，在半导体芯片的相应的第一表面上。在形成间隔件之后，半导体晶片能够被单体化成多个半导体芯片。
参考图7A-7F，示出了中间产品的示意表示以图示根据一个实施例的用于制造电子部件的方法。实施例包括如先前根据图3的实施例所描述的多个电子部件的晶片级制造。
参考图7A，示出了包括多个已处理的半导体管芯50的已处理的半导体晶片100。半导体晶片100和半导体管芯50被以示意顶视图表示来示出，使得半导体管芯50的上部有源表面被示出在图7A中。
参考图7B，半导体晶片100被翻转使得半导体管芯50的后表面被示出，在稍后的步骤中其每一个都将被安装到导电载体上。另外，图7B示出了在执行进一步处理之后的半导体晶片100，其中半导体管芯50中的每一个的后表面经历结构化处理。所放大的圆稍微更详细地示出了一个半导体管芯50的后面的结构化的结果。已经结合图2A描述了已经被形成到半导体管芯50的后表面中的图案。其基本上由分别包含方形截面的相等间隔的凹陷的网格图案构成。只要半导体管芯50是一个半导体晶片100的一部分，就能够通过例如半导体晶片100 的表面的掩模光刻和各向同性蚀刻以非常有效的方式在晶片级执行结构化。
参考图7C，示出了在将金属化层150沉积到半导体晶片100 的后表面上之后的半导体晶片100。例如，金属化层150 的厚度能够在从100 nm - 5 μm的范围内。
参考图7D，示出了由在粘合层200沉积到金属化层150上之后的半导体晶片100构成的进一步的中间产品。粘合层被沉积到半导体晶片100 的后表面上，其目的是产生如在图2A、2B的实施例中所描述的间隔件。
参考图7E，示出了在粘合层的结构化之后的情形下半导体晶片100的进一步的中间产品。粘合层的结构化的结果是，半导体管芯50中的每一个现在分别包括位于半导体管芯50的四个拐角的四个间隔件204。
参考图7F，示出了在单体化半导体晶片100并且将半导体管芯50彼此分开之后所获得的多个半导体芯片60。半导体芯片60现在每一个都能够被安装到先前结合图3的实施例所解释的导电载体（例如引线框架）上。

Claims (27)

1.一种电子部件，包括：
包括第一载体表面的导电载体；
包括第一芯片表面的半导体芯片，其中，所述第一载体表面和所述第一芯片表面中的一个或二者包括非平面结构，并且其中所述半导体芯片被附着到所述载体，并且所述第一芯片表面面向所述第一载体表面，使得由于所述第一载体表面和所述第一芯片表面中的一个或二者的所述非平面结构的原因在所述第一芯片表面与所述第一载体表面之间提供间隙；以及
位于所述间隙中的第一电沉积金属层。
2.根据权利要求1所述的电子部件，其中，所述非平面结构归因于表面粗糙度。
3.根据权利要求2所述的电子部件，其中，所述表面粗糙度的特征在于大于3 μm的平均凹陷深度。
4.根据权利要求1所述的电子部件，其中，所述非平面结构归因于人工表面处理。
5.根据权利要求1所述的电子部件，其中，所述半导体芯片包括面向所述载体的金属化层。
6.根据权利要求1所述的电子部件，进一步包括：
位于横向地在所述半导体芯片旁边的所述第一载体表面上的第二电沉积金属层。
7.根据权利要求6所述的电子部件，其中，所述第一芯片表面与所述第二电沉积金属层的表面共面。
8.根据权利要求1所述的电子部件，其中，所述载体包括从所述第一载体表面延伸到另一载体表面的一个或多个通孔。
9.一种电子部件，包括：
包括第一载体表面的导电载体；
包括第一芯片表面的半导体芯片，所述半导体芯片被附着到所述载体使得所述第一芯片表面面向所述第一载体表面；
位于所述第一芯片表面与所述第一载体表面之间的至少两个间隔件，从而在所述第一芯片表面与所述第一载体表面之间提供间隙；以及
在所述间隙中提供的第一电沉积金属层。
10.根据权利要求9所述的电子部件，其中，所述至少两个间隔件靠近所述半导体芯片的拐角。
11.根据权利要求9所述的电子部件，其中，所述至少两个间隔件由导电材料、焊料材料、粘合材料以及电介质材料中的一个或多个制造。
12.根据权利要求9所述的电子部件，其中，所述半导体芯片包括面向所述载体的金属化层。
13.根据权利要求9所述的电子部件，进一步包括：
位于横向地在所述半导体芯片旁边的所述第一载体表面上的第二电沉积金属层。
14.根据权利要求13所述的电子部件，其中，所述第一芯片表面与所述第二电沉积金属层的表面共面。
15.根据权利要求9所述的电子部件，其中，所述至少两个间隔件的直径在从0.5至50 μm的范围内。
16.根据权利要求15所述的电子部件，其中，所述直径在从2至20 μm的范围内。
17.根据权利要求9所述的电子部件，其中，所述载体包括从所述第一载体表面延伸到另一载体表面的一个或多个通孔。
18.一种用于制造电子部件的方法，所述方法包括：
提供包括第一载体表面的导电载体；
提供包括第一芯片表面的半导体芯片，其中，所述第一载体表面与所述第一芯片表面中的一个或二者包括非平面结构；
将所述半导体芯片附着到所述载体，其中所述第一芯片表面面向所述第一载体表面，使得由于所述第一载体表面和所述第一芯片表面中的一个或二者的所述非平面结构的原因在所述第一芯片表面与所述第一载体表面之间提供间隙；以及
在所述间隙中电沉积第一金属层。
19.根据权利要求18所述的方法，进一步包括：
处理所述第一载体表面和所述第一芯片表面中的一个或二者以获得所述非平面结构。
20.根据权利要求19所述的方法，其中，所述处理包括将凹陷和隆凸的规则图案形成到所述第一载体表面和所述第一芯片表面中的一个或多个中。
21.根据权利要求19所述的方法，其中，所述规则图案包括网格图案。
22.根据权利要求18所述的方法，进一步包括：
借助于粘合带将所述半导体芯片附着到所述载体。
23.根据权利要求18所述的方法，进一步包括：
在所述第一金属层的所述沉积的同时在横向地在所述半导体芯片旁边的所述第一载体表面上电沉积第二金属层。
24.一种用于制造电子部件的方法，所述方法包括：
提供包括第一载体表面的导电载体；
在芯片表面与所述第一载体表面之间提供至少两个间隔件；
将芯片附着到所述载体使得所述芯片表面面向所述第一载体表面，从而在所述芯片表面与所述第一载体表面之间提供间隙；以及
在所述间隙中电沉积第一金属层。
25.根据权利要求24所述的方法，进一步包括：
通过将间隔件层施加到所述芯片表面上并且选择性地移除所述间隔件层使得留下所述至少两个间隔件来形成所述至少两个间隔件。
26.根据权利要求25所述的方法，其中，在所述芯片仍然是包括多个半导体芯片的半导体晶片的部分时执行形成所述至少两个间隔件。
27.根据权利要求24所述的方法，进一步包括：
在所述第一金属层的所述沉积的同时将第二金属层电沉积到横向地在所述芯片旁边的所述第一载体表面上。
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