CN102282658B - 使用不导电丝网印刷与施涂粘合剂的半导体裸片附接方法 - Google Patents
使用不导电丝网印刷与施涂粘合剂的半导体裸片附接方法 Download PDFInfo
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- CN102282658B CN102282658B CN201080004725.8A CN201080004725A CN102282658B CN 102282658 B CN102282658 B CN 102282658B CN 201080004725 A CN201080004725 A CN 201080004725A CN 102282658 B CN102282658 B CN 102282658B
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Abstract
将例如环氧树脂的均匀不导电材料层(108)丝网印刷到集成电路晶片(102)的背侧上达所需厚度,且接着对其进行加热直到其被硬固化为止(C阶段)(110)。接着将具有经硬固化涂层的所述集成电路晶片锯开以分离个别集成电路裸片(124)。将不导电粘合剂施涂到引线框架(116)的裸片附接桨形件(116a)的配合面上。将所述裸片放置到所述不导电粘合剂中且接着加热裸片与裸片附接桨形件组合件以使所述粘合剂(118)硬固化在所述裸片与裸片附接桨形件的所述配合面之间。此提供所述集成电路裸片与所述裸片附接桨形件的长期电隔离且有效地消除从所述裸片附接桨形件的银迁移,所述银迁移导致形成增加所述裸片中的不希望的泄漏电流且最终在其操作期间导致故障的导电路径。
Description
技术领域
本发明涉及将半导体集成电路裸片附接到引线框架,且更特定来说涉及通过使用不导电丝网印刷与施涂粘合剂将半导体裸片附接到引线框架的相应裸片附接桨形件,所述不导电丝网印刷与施配粘合剂还将半导体裸片与引线框架裸片附接桨形件电隔离。
背景技术
在半导体集成电路的制作期间,将半导体集成电路裸片(其背侧)附接到引线框架的裸片附接桨形件。接着借助接合线将所述半导体集成电路裸片的接合垫附接到引线框架的导体。通常,借助例如环氧树脂的粘合剂将半导体集成电路裸片的背侧附接到所述引线框架的裸片附接桨形件。随时间推移,导电路径可在所述半导体集成电路裸片与裸片引线框架的裸片桨形件之间形成。这些导电路径可通过银从引线框架的裸片附接桨形件到集成电路裸片的背侧的迁移来形成。最终,此银迁移形成半导体集成电路裸片的背侧与裸片桨形件之间的连接,因此导致其之间的电短路。
当半导体集成电路裸片与裸片附接桨形件之间存在电位差时,来自裸片附接桨形件的银分子可随时间迁移。当向半导体集成电路裸片施加操作及/或备用电力时,存在此电位差。银迁移在半导体集成电路裸片正汲取低的静态电流时(例如,在备用操作模式(休眠模式)期间)特别具活性。使半导体集成电路裸片在低的静态电流下运行为必需的,以便可将半导体集成电路裸片从备用(休眠)模式成为操作模式。银迁移形成半导体集成电路裸片与裸片附接桨形件之间的电路径且借此导致半导体集成电路裸片中的高静态电流到达最终半导体集成电路裸片的电路出故障的点。
已使用各种物理附接配置将半导体集成电路裸片与裸片附接桨形件电隔离。一个此种附接配置使用不导电环氧树脂来实现物理附接及电隔离。然而,此已随时间证明为在防止由于半导体集成电路裸片与裸片附接桨形件之间的导电路径所致的高静态电流方面是效率低且不可靠的。
另一类似但更有效的方法是将一个或两个不导电环氧树脂层丝网印刷到集成电路晶片的背侧上。所述集成电路晶片包括多个半导体集成电路裸片。所述经丝网印刷环氧树脂经部分地固化(B阶段)且此后准备好以单个化成个别裸片。接着通过以下操作将个别集成电路裸片附接到多个引线框架的相应裸片附接桨形件:加热所述裸片附接桨形件,接着将涂覆有不导电B阶段环氧树脂的裸片刷磨到经加热裸片附接桨形件上。在已将所述裸片附接到相应裸片附接桨形件之后,对其进行加热直到不导电B阶段环氧树脂被硬固化为止(C阶段)。此形式的附接确实解决了长期的银迁移问题,但B阶段环氧树脂集成电路晶片的有用贮存寿命仅为约2到4个周。
发明内容
因此,存在对以下较佳方式的需要:用不导电材料涂覆半导体集成电路晶片的背侧,使得涂层具有长贮存(贮藏)寿命、辅助经单个化半导体集成电路裸片到引线框架的裸片附接桨形件的附接且防止或大致减少在半导体集成电路裸片的操作期间从裸片附接桨形件的银迁移。
根据本发明的教示内容,将例如环氧树脂的均匀不导电材料层丝网印刷到集成电路晶片的背侧上达所需厚度,且接着对其进行加热直到其被硬固化为止(C阶段)。所述丝网印刷可将所述不导电材料以一图案施加到所述集成电路晶片的所述背侧上。接着将其上具有经硬固化涂层的所述集成电路晶片锯开以在所述晶片中将每一个别集成电路裸片彼此分离(单个化)以准备附接到引线框架的相应裸片附接桨形件。所述所需厚度可从约1毫英寸到3毫英寸、优选地从约1.5毫英寸到2.5毫英寸且最优选地为约2毫英寸。
在将裸片附接到裸片附接桨形件的工艺期间,将不导电粘合剂(例如,环氧树脂)施涂到所述裸片附接桨形件的配合面上。接着将所述裸片的具有经硬固化涂层的面放置到裸片附接桨形件的配合面上的最近施涂的不导电粘合剂中。接下来,加热裸片与裸片附接桨形件组合件以使所述粘合剂硬固化在所述裸片与裸片附接桨形件的配合面之间。在所述粘合剂已被硬固化之后,可将集成电路接合垫线接合到引线框架引线(用于已完成的集成电路外部电路连接的导电引线)。借此提供集成电路裸片与引线框架的裸片附接桨形件的长期电隔离且有效地消除从裸片附接桨形件的银迁移,所述银迁移导致形成增加裸片中的不希望的泄漏电流且最终在其操作期间导致故障的导电路径。
根据本发明的特定实例性实施例,一种用于将半导体裸片附接到引线框架裸片附接桨形件的方法包括以下步骤:将不导电材料施加到半导体集成电路晶片的背面,所述半导体集成电路晶片包括多个集成电路裸片;加热所述半导体集成电路晶片及位于其上的所述不导电材料直到所述不导电材料被硬固化为止;将所述半导体集成电路晶片安装在晶片载体上;其中所述经硬固化的不导电材料位于所述半导体集成电路晶片与所述晶片载体之间;将所述多个集成电路裸片中的每一者彼此分离;在多个引线框架的裸片附接桨形件的面上施涂不导电粘合剂;将所述多个集成电路裸片放置到所述裸片附接桨形件中的相应桨形件的所述面上的所述不导电粘合剂中;加热所述多个集成电路裸片及裸片附接桨形件直到所述不导电粘合剂被硬固化为止;借助接合线将所述多个集成电路裸片的接合垫附接到所述多个引线框架的相应导电引线;及将所述多个引线框架中的每一者分离成若干集成电路。
附图说明
通过参考结合附图进行的以下说明可获取对本发明的更全面理解,在附图中:
图1是根据本发明的特定实例性实施例使用不导电丝网印刷与施涂粘合剂的半导体裸片附接的示意性工艺图;且
图2是根据本发明的特定实例性实施例图1中所展示的半导体裸片附接工艺的示意性流程图。
尽管本发明易于做出各种修改及替代形式,但在图式中是展示并在本文中详细地描述其特定实例性实施例。然而,应理解,本文对特定实例性实施例的说明并非打算将本发明限定于本文中所揭示的特定形式,而是相反,本发明打算涵盖所附权利要求书所界定的所有修改及等效形式。
具体实施方式
现在参考图式,示意性地图解说明特定实例性实施例的细节。图式中相似的元件将由相似的编号表示,且类似的元件将由带有不同小写字母后缀的相似编号表示。
参考图1,其描绘根据本发明的特定实例性实施例使用不导电丝网印刷与施涂粘合剂的半导体裸片附接的示意性工艺图。将半导体集成电路晶片102放置到丝网印刷夹具106中,且借助丝网印刷散布器104在晶片102的背侧(非电路垫侧)上散布不导电材料108。丝网印刷夹具106的使用在涂覆表面领域中是众所周知的。借助丝网印刷夹具106,可将所要的不导电材料108图案施加到晶片102的背侧面。不导电材料108可为(举例来说但不限于)环氧树脂等。
在用不导电材料108对晶片102的背侧面进行丝网印刷之后,将经涂覆晶片102放置到固化炉110中以使不导电材料108硬固化。不导电材料108的硬固化可包括(举例来说但不限于)在约150摄氏度下加热达约2个小时。在不导电材料108已被硬固化到晶片102的背侧面上之后,可在进一步处理之前贮存晶片102达延长的时间周期,或者可将经硬固化的经涂覆晶片102附接到工艺衬底112(例如,安装带),以便可将晶片102单个化(通过切割分离)成多个半导体集成电路裸片124。
引线框架载体114包括多个引线框架116。多个引线框架116中的每一者包括裸片附接桨形件116a及引线框架导体116b。引线框架116是集成电路制作领域的技术人员众所周知的。将粘合剂118施涂到裸片附接桨形件116a中的每一者的面上。接着将经单个化(经分离)的裸片124放置到相应裸片附接桨形件116a中的每一者上的粘合剂118上。将引线框架载体114、多个引线框架116、粘合剂118及经涂覆裸片124的组合件放置到固化炉120中,以便借此使粘合剂118硬固化。不导电粘合剂118的硬固化可包括(举例来说但不限于)在约175摄氏度下加热达约1个小时。粘合剂材料118为大致不导电的且可为(举例来说但不限于)环氧树脂等。
在粘合剂材料118已被硬固化及冷却之后,从固化炉120中取出引线框架116且借助接合线122将裸片124中的每一者上的接合垫126连接到引线框架导体116b中的相应导体。将集成电路接合垫126线接合到引线框架导体116b是集成电路制作领域的技术人员众所周知的。
在将裸片接合垫126中的每一者线接合到引线框架导体116b中的相应导体之后,分离已完成的集成电路组合件且可将其囊封成封装式集成电路(未展示)。
参考图2,其描绘根据本发明的特定实例性实施例图1中所展示的半导体裸片附接工艺的示意性流程图。在步骤202中,用不导电材料(108)涂覆半导体集成电路晶片(102)的背侧。在步骤204中,使涂覆在半导体集成电路晶片(102)的背侧上的不导电材料(108)硬固化。在步骤206中,将经涂覆晶片(102)安装到载体(112)上,且接着在步骤208中,将构成晶片(102)的多个集成电路裸片(124)彼此分离开(单个化)。
在步骤210中,将粘合剂(118)施涂到引线框架载体(114)上的引线框架(116)的裸片附接桨形件(116a)的面上。接着在步骤212中,将经单个化的集成电路裸片(124)放置到相应裸片附接桨形件(116a)的面上的粘合剂(118)中。在步骤214中,加热粘合剂(118)以使其硬固化(C阶段)。在步骤216中,将裸片(124)的接合垫(126)线接合到引线框架(116)的导体(例如,引线指形件)(116b)中的相应导体。在步骤218中,将引线框架(116)与引线框架载体(114)分离以变为已完成的集成电路。可在步骤220中囊封这些已完成的集成电路以变为封装式集成电路,如电子器件领域中众所周知。
尽管已参考本发明的实例性实施例来描绘、描述及界定本发明的各实施例,但此参考并不意味着限定本发明,且不应推断出存在此限定。所揭示的标的物能够在形式及功能上具有大量修改、更改及等效形式,相关领域的且受益于本发明的技术人员将会联想到这些修改、更改及等效形式。所描绘及所描述的本发明实施例仅为实例,而并非是对本发明范围的穷尽性说明。
Claims (11)
1.一种用于将半导体裸片附接到引线框架裸片附接桨形件的方法,所述方法包括以下步骤:
将不导电材料施加到半导体集成电路晶片的背面,所述半导体集成电路晶片包括多个集成电路裸片;
加热所述半导体集成电路晶片及位于其上的所述不导电材料直到所述不导电材料被硬固化为止;
将所述半导体集成电路晶片安装在晶片载体上;其中经硬固化的所述不导电材料接触所述半导体集成电路晶片与所述晶片载体;
将所述多个集成电路裸片中的每一者彼此分离;
在多个引线框架的裸片附接桨形件的面上施涂不导电粘合剂;
将所述多个集成电路裸片放置到所述裸片附接桨形件中的相应桨形件的所述面上的所述不导电粘合剂中;
加热所述多个集成电路裸片及裸片附接桨形件直到所述不导电粘合剂被硬固化为止;
借助接合线将所述多个集成电路裸片的接合垫附接到所述多个引线框架的相应导电引线;及
将所述多个引线框架中的每一者分离成若干集成电路。
2.根据权利要求1所述的方法,其进一步包括囊封所述集成电路以产生封装式集成电路的步骤。
3.根据权利要求1所述的方法,其中以从1毫英寸到3毫英寸的厚度来施加所述不导电材料。
4.根据权利要求1所述的方法,其中以从1.5毫英寸到2.5毫英寸的厚度来施加所述不导电材料。
5.根据权利要求1所述的方法,其中以约2毫英寸的厚度来施加所述不导电材料。
6.根据权利要求1所述的方法,其中所述不导电材料为环氧树脂。
7.根据权利要求1所述的方法,其中所述不导电粘合剂为环氧树脂。
8.根据权利要求1所述的方法,其中通过丝网印刷来完成所述施加所述不导电材料的步骤。
9.根据权利要求8所述的方法,其中以一图案来施加经丝网印刷的所述不导电材料。
10.根据权利要求1所述的方法,其中所述加热所述半导体集成电路晶片及所述不导电材料的步骤包括在约150摄氏度下加热达约2个小时的步骤。
11.根据权利要求1所述的方法,其中所述加热所述多个集成电路裸片及裸片附接桨形件直到所述不导电粘合剂被硬固化为止的步骤包括在约175摄氏度下加热达约1个小时的步骤。
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US7579215B2 (en) * | 2007-03-30 | 2009-08-25 | Motorola, Inc. | Method for fabricating a low cost integrated circuit (IC) package |
US7892894B2 (en) * | 2007-09-20 | 2011-02-22 | Stats Chippac Ltd. | Method of manufacturing integrated circuit package system with warp-free chip |
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2009
- 2009-05-27 US US12/472,675 patent/US7927921B2/en active Active
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2010
- 2010-05-20 TW TW099116180A patent/TWI462196B/zh active
- 2010-05-21 CN CN201080004725.8A patent/CN102282658B/zh active Active
- 2010-05-21 WO PCT/US2010/035763 patent/WO2010138415A2/en active Application Filing
- 2010-05-21 SG SG2011066701A patent/SG174422A1/en unknown
- 2010-05-21 MY MYPI2011004373A patent/MY154082A/en unknown
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US5012322A (en) * | 1987-05-18 | 1991-04-30 | Allegro Microsystems, Inc. | Semiconductor die and mounting assembly |
US6943061B1 (en) * | 2004-04-12 | 2005-09-13 | Ns Electronics Bangkok (1993) Ltd. | Method of fabricating semiconductor chip package using screen printing of epoxy on wafer |
Also Published As
Publication number | Publication date |
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CN102282658A (zh) | 2011-12-14 |
US20100304532A1 (en) | 2010-12-02 |
TW201108337A (en) | 2011-03-01 |
US7927921B2 (en) | 2011-04-19 |
TWI462196B (zh) | 2014-11-21 |
SG174422A1 (en) | 2011-10-28 |
WO2010138415A3 (en) | 2011-05-26 |
WO2010138415A2 (en) | 2010-12-02 |
MY154082A (en) | 2015-04-30 |
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