CN106024745A - 一种半导体管脚贴装结构及其焊接方法 - Google Patents

一种半导体管脚贴装结构及其焊接方法 Download PDF

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CN106024745A
CN106024745A CN201610507751.1A CN201610507751A CN106024745A CN 106024745 A CN106024745 A CN 106024745A CN 201610507751 A CN201610507751 A CN 201610507751A CN 106024745 A CN106024745 A CN 106024745A
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lead frame
chip
metal
solder
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徐赛
刘红军
周正伟
王赵云
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Changjiang Electronics Technology (suqian) Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/84009—Pre-treatment of the connector and/or the bonding area
    • H01L2224/84051—Forming additional members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H01L2224/85051—Forming additional members, e.g. for "wedge-on-ball", "ball-on-wedge", "ball-on-ball" connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/858—Bonding techniques

Abstract

本发明涉及一种半导体管脚贴装结构及其焊接方法，所述结构包括导线架，所述导线架包括载片台（4）和管脚（1），所述载片台（4）上通过焊料（5）设置有芯片（6），所述管脚（1）上通过焊料（5）设置有金属片（2），所述芯片（6）正面与金属片（2）正面之间通过金属线或金属带（3）相连接。本发明一种半导体管脚贴装结构及其焊接方法，它能够解决产品试验过程中不同管脚结构及电性切换的功能需求和避开焊接材料中助焊剂易挥发到管脚造成虚焊的困扰。

Description

一种半导体管脚贴装结构及其焊接方法
技术领域
本发明涉及一种半导体管脚贴装结构及其焊接方法，属于半导体封装技术领域。
背景技术
装片接合(Die bonding)和打线接合（Wire bonding）是集成电路封装产业中最重要的制程之二，装片接合(Die bonding)是把芯片（Chip）通过焊料精确的贴装到导线架（Lead frame）上指定区域，以形成热通路或电通路的技术。打线接合（Wire bonding）是利用金属焊线材将芯片（Chip）及导线架（Lead frame）连接起来的技术，使微小的芯片得以与外面的电路做沟通，而不需要增加太多的面积。
1，在装片接合制程中，将导电或非导电焊料点涂到导线架的载片台上，然后在焊料装点位置装上芯片。如果使用助焊剂挥发性较强的焊料，那么助焊剂很容易挥发到管脚靠近载片台的一端上，在打线接合阶段会因为挥发物粘着在管脚而使得焊线与管脚结合变差俗称虚焊，甚至是失效。
2、在打线接合制程中，不同的金属焊线会配合着不同镀层的导线架来使用，比如使用金线焊接需要搭配镀银管脚，铝带、铝线焊接搭配裸铜管脚。但是，导线架管脚的电镀层往往是在导线架的制作阶段就已经完成的，特别是在产品试验阶段，客户需要对不同的焊线种类进行试验验证，则要频繁切换管脚电镀方式，这就需重新开发导线架，不但会花费大量的时间，同时提高了导线架制造成本。
3、另外，客户的需求总是不断变化的，当需要将相邻管脚或者隔管脚并连，现有结构很难实现，往往需要对导线架进行重新设计，这就进一步提高了框架制造成本。
发明内容
本发明所要解决的技术问题是针对上述现有技术的不足提供一种半导体管脚贴装结构及其焊接方法，它能够满足对产品不同管脚结构及电性切换的功能需求和解决焊接材料中助焊剂易挥发到管脚造成打线虚焊的困扰。
本发明解决上述问题所采用的技术方案为：一种半导体管脚贴装结构，它包括导线架，所述导线架包括载片台和管脚，所述载片台上通过焊料设置有芯片，所述管脚上通过焊料设置有金属片，所述芯片正面与金属片正面之间通过金属线或金属带相连接。
所述载片台与芯片之间为焊料层，也可以为共晶层或粘接胶层。
一种半导体管脚贴装结构的焊接方法，所述方法包括如下步骤：
步骤一、取一金属基板；
步骤二、在金属基板双面或单面镀铜、银、金或镍钯金；
步骤三、将电镀好的金属基板下表面贴膜，使用片环以预定规格将金属基板切割成若干个金属片；
步骤四、提供一导线架，在导线架载片台上装上芯片；
步骤五、在步骤四中装好芯片的导线架需连接或需贴装的管脚上涂覆焊料，再在焊料上植入步骤三中切割好的金属片；
步骤六、把步骤五中已装好芯片和金属片的导线架进行回流焊；
步骤七、对步骤六中完成回流的导线架进行打线作业，将金属丝或金属带由芯片端连接至管脚端金属片上，完成电性连接；
步骤八、将步骤七完成打线作业的导线架采用塑封料进行塑封；
步骤九、将步骤八完成塑封的半成品进行切割或是冲切作业，使原本阵列式塑封体，切割或是冲切独立开来，制得半导体管脚贴装结构。
所述金属基板的材质为铜、铁、铝或不锈钢材。
所述装片方式可根据芯片类型采用共晶装片、导电胶/非导电胶装片或焊料装片。
所述步骤五中金属片的贴装方式可以是分立管脚贴装、相邻管脚贴装或跨管脚贴装。
与现有技术相比，本发明的优点在于：
1、本发明的导线架管脚端贴装金属片的厚度是可控的，可以使载片台与管脚端有足够的高度差，所以能避开大面积的助焊剂挥发，避免管脚污染影响第二焊点质量。
2、本发明通过直连、桥接等方法将传统导线架管脚的固定输出变为弹性输出，灵活了管脚输出设计；
3、本发明通过贴装不同电镀方式的金属片实现导线架管脚不同电镀方式的切换，大小可根据管脚大小及覆盖区域确定，切割及贴片工艺为现有工艺，操作简单。
附图说明
图1为本发明一种半导体管脚贴装结构的示意图。
图2为本发明一种半导体管脚贴装结构的剖视图。
图3~图8为本发明一种半导体管脚贴装结构的制作流程图。
图9~图13为本发明一种半导体管脚贴装结构的焊接方法中金属片与管脚贴片方式的各实施例图。
其中：
管脚1
金属片2
金属丝或金属带3
载片台4
焊料5
芯片6
膜7
片环8。
具体实施方式
以下结合附图实施例对本发明作进一步详细描述。
如图1、图2所示，本实施例中的一种半导体管脚贴装结构，它包括导线架，所述导线架包括载片台4和管脚1，所述载片台4上通过焊料5设置有芯片6，所述管脚1上通过焊料5设置有金属片2，所述芯片6正面与金属片2正面之间通过金属线或金属带3相连接。
所述载片台与芯片之间为焊料层，也可以为共晶层或粘接胶层。
其焊接方法如下：
步骤一、参见图3，取一金属基板，基板材质可以是铜、铁、铝、不锈钢材或有导电性能的其他金属物质，本实施例金属基板优选铜基板，金属基板厚度依据芯片下焊料厚度进行选择，长宽依据管脚大小及贴装覆盖的区域进行选择，金属基板可依据后续管脚金属片的贴装方式冲压出所需形状；
步骤二、参见图4，在金属基板上表面预镀一层铜，下表面预镀一层银，铜层厚度为2~10微米，依据功能需要也可以减薄或是增厚，电镀方式可以是电解电镀也可以采用化学沉积的方式；
步骤三、参见图5，将电镀好的金属基板下表面贴膜，使用片环以预定规格将金属基板切割成若干个金属片；
步骤四、参见图6，提供一导线架，在导线架载片台上装上芯片，装片方式可根据芯片类型采用共晶装片、导电胶/非导电胶装片或焊料装片；
步骤五、参见图7，在步骤四中装好芯片的导线架需连接或需贴装的管脚上涂覆焊料，再在焊料上植入步骤三中切割好的金属片；
步骤六、把步骤五中已装好芯片和金属片的导线架进行回流焊,完成芯片与金属片的贴装；
步骤七、参见图8，对步骤六中完成回流的导线架进行打线作业，将金属丝或金属带由芯片端连接至管脚端金属片上，完成电性连接；
步骤八、将步骤七完成打线作业的导线架采用塑封料进行塑封；
步骤九、将步骤八完成塑封的半成品进行切割或是冲切作业，使原本阵列式塑封体，切割或是冲切独立开来，制得半导体管脚贴装结构。
图9~图13为导线架管脚贴装金属片后的示意图，其中图9为相邻管脚两两相连的贴片形式，图10为所有管脚相连的贴片形式，图11为单个管脚变换电镀方式和管脚高度的贴片形式，图12、图13为跨管脚贴片形式；
除上述实施例外，本发明还包括有其他实施方式，凡采用等同变换或者等效替换方式形成的技术方案，均应落入本发明权利要求的保护范围之内。

Claims (6)

1.一种半导体管脚贴装结构，其特征在于：它包括导线架，所述导线架包括载片台（4）和管脚（1），所述载片台（4）上通过焊料（5）设置有芯片（6），所述管脚（1）上通过焊料（5）设置有金属片（2），所述芯片（6）正面与金属片（2）正面之间通过金属线或金属带（3）相连接。
2.根据权利要求1所述的一种半导体管脚贴装结构，其特征在于：所述载片台与芯片之间为焊料，也可以为共晶层或粘接胶层。
3.一种半导体管脚贴装结构的焊接方法，其特征在于所述方法包括如下步骤：
步骤一、取一金属基板；
步骤二、在金属基板双面或单面镀铜、银、金或镍钯金；
步骤三、将电镀好的金属基板下表面贴膜，使用片环以预定规格将金属基板切割成若干个金属片；
步骤四、提供一导线架，在导线架载片台上装上芯片；
步骤五、在步骤四中装好芯片的导线架需连接或需贴装的管脚上涂覆焊料，再在焊料上植入步骤三中切割好的金属片；
步骤六、把步骤五中已装好芯片和金属片的导线架进行回流焊；
步骤七、对步骤六中完成回流的导线架进行打线作业，将金属丝或金属带由芯片端连接至管脚端金属片上，完成电性连接；
步骤八、将步骤七完成打线作业的导线架采用塑封料进行塑封；
步骤九、将步骤八完成塑封的半成品进行切割或是冲切作业，使原本阵列式塑封体，切割或是冲切独立开来，制得半导体管脚贴装结构。
4.根据权利要求3所述的一种半导体管脚贴装结构的焊接方法，其特征在于：所述金属基板的材质为铜、铁、铝或不锈钢材。
5.根据权利要求3所述的一种半导体管脚贴装结构的焊接方法，其特征在于：所述装片方式可根据芯片类型采用共晶装片、导电胶/非导电胶装片或焊料装片。
6.根据权利要求3所述的一种半导体管脚贴装结构的焊接方法，其特征在于：所述步骤四中金属片的贴装方式为分立管脚贴装、相邻管脚贴装或跨管脚贴装。
CN201610507751.1A 2016-07-01 2016-07-01 一种半导体管脚贴装结构及其焊接方法 Pending CN106024745A (zh)

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