CN205789943U - 一种半导体管脚贴装结构 - Google Patents

一种半导体管脚贴装结构 Download PDF

Info

Publication number
CN205789943U
CN205789943U CN201620681432.8U CN201620681432U CN205789943U CN 205789943 U CN205789943 U CN 205789943U CN 201620681432 U CN201620681432 U CN 201620681432U CN 205789943 U CN205789943 U CN 205789943U
Authority
CN
China
Prior art keywords
pin
transistor
lead frame
chip
assembling structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201620681432.8U
Other languages
English (en)
Inventor
徐赛
刘红军
周正伟
王赵云
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changjiang Electronics Technology (suqian) Co Ltd
Original Assignee
Changjiang Electronics Technology (suqian) Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changjiang Electronics Technology (suqian) Co Ltd filed Critical Changjiang Electronics Technology (suqian) Co Ltd
Priority to CN201620681432.8U priority Critical patent/CN205789943U/zh
Application granted granted Critical
Publication of CN205789943U publication Critical patent/CN205789943U/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/37124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/3716—Iron [Fe] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

本实用新型涉及一种半导体管脚贴装结构，它包括引线框架，所述引线框架包括载片台（4）和管脚（1），所述载片台（4）上通过焊料（5）设置有芯片（6），所述管脚（1）上通过焊料（5）设置有金属片（2），所述芯片（6）正面与金属片（2）正面之间通过金属线或金属带（3）相连接。本实用新型一种半导体管脚贴装结构，它能够解决产品试验过程中不同管脚结构及电性切换的功能需求和避开焊接材料中助焊剂易挥发到管脚造成虚焊的困扰。

Description

一种半导体管脚贴装结构
技术领域
本实用新型涉及一种半导体管脚贴装结构，属于半导体封装技术领域。
背景技术
装片接合(Die bonding)和打线接合（Wire bonding）是集成电路封装产业中最重要的制程之二，装片接合(Die bonding)是把芯片（Chip）通过焊料精确的贴装到导线架（Lead frame）上指定区域，以形成热通路或电通路的技术。打线接合（Wire bonding）是利用金属焊线材将芯片（Chip）及导线架（Lead frame）连接起来的技术，使微小的芯片得以与外面的电路做沟通，而不需要增加太多的面积。
1，在装片接合制程中，将导电或非导电焊料点涂到导线架的载片台上，然后在焊料装点位置装上芯片。如果使用助焊剂挥发性较强的焊料，那么助焊剂很容易挥发到管脚靠近载片台的一端上，在打线接合阶段会因为挥发物粘着在管脚而使得焊线与管脚结合变差俗称虚焊，甚至是失效。
2、在打线接合制程中，不同的金属焊线会配合着不同镀层的导线架来使用，比如使用金线焊接需要搭配镀银管脚，铝带、铝线焊接搭配裸铜管脚。但是，导线架管脚的电镀层往往是在导线架的制作阶段就已经完成的，特别是在产品试验阶段，客户需要对不同的焊线种类进行试验验证，则要频繁切换管脚电镀方式，这就需重新开发导线架，不但会花费大量的时间，同时提高了导线架制造成本。
3、另外，客户的需求总是不断变化的，当需要将相邻管脚或者隔管脚并连，现有结构很难实现，往往需要对导线架进行重新设计，这就进一步提高了框架制造成本。
实用新型内容
本实用新型所要解决的技术问题是针对上述现有技术提供一种半导体管脚贴装结构，它能够解决产品试验过程中不同管脚结构及电性切换的功能需求和避开焊接材料中助焊剂易挥发到管脚造成虚焊的困扰。
本实用新型解决上述问题所采用的技术方案为：一种半导体管脚贴装结构，它包括引线框架，所述引线框架包括载片台和管脚，所述载片台上通过焊料设置有芯片，所述管脚上通过焊料设置有金属片，所述芯片正面与金属片正面之间通过金属线或金属带相连接。
所述载片台与芯片之间为焊料层，也可以为共晶层或粘接胶层。
所述金属片的材质为铜、铁、铝或不锈钢材。
与现有技术相比，本实用新型的优点在于：
1、本发明的导线架管脚端贴装金属片的厚度是可控的，可以使载片台与管脚端有足够的高度差，所以能避开大面积的助焊剂挥发，避免管脚污染影响第二焊点质量。
2、本发明通过直连、桥接等方法将传统导线架管脚的固定输出变为弹性输出，灵活了管脚输出设计；
3、本发明通过贴装不同电镀方式的金属片实现导线架管脚不同电镀方式的切换，大小可根据管脚大小及覆盖区域确定，切割及贴片工艺为现有工艺，操作简单。
附图说明
图1为本实用新型一种半导体管脚贴装结构的示意图。
图2为本实用新型一种半导体管脚贴装结构的剖视图。
图3~图8为本实用新型一种半导体管脚贴装结构的制作流程图。
图9~图13为本实用新型一种半导体管脚贴装结构的焊接方法中金属片与管脚贴片方式的各实施例图。
其中：
管脚1
金属片2
金属丝或金属带3
载片台4
焊料5
芯片6
膜7
片环8。
具体实施方式
以下结合附图实施例对本实用新型作进一步详细描述。
如图1、图2所示，本实施例中的一种半导体管脚贴装结构，它包括引线框架，所述引线框架包括载片台4和管脚1，所述载片台4上通过焊料5设置有芯片6，所述管脚1上通过焊料5设置有金属片2，所述芯片6正面与金属片2正面之间通过金属线或金属带3相连接。
所述载片台与芯片之间为焊料层，也可以为共晶层或粘接胶层。
其焊接方法如下：
步骤一、参见图3，取一金属基板，基板材质可以是铜、铁、铝、不锈钢材或有导电性能的其他金属物质，本实施例金属基板优选铜基板，金属基板厚度依据芯片下焊料厚度进行选择，长宽依据管脚大小及贴装覆盖的区域进行选择，金属基板可依据后续管脚金属片的贴装方式冲压出所需形状；
步骤二、参见图4，在金属基板上表面预镀一层铜，下表面预镀一层银，铜层厚度为2~10微米，依据功能需要也可以减薄或是增厚，电镀方式可以是电解电镀也可以采用化学沉积的方式；
步骤三、参见图5，将电镀好的金属基板下表面贴膜，使用片环以预定规格将金属基板切割成若干个金属片；
步骤四、参见图6，提供一导线架，在导线架载片台上装上芯片，装片方式可根据芯片类型采用共晶装片、导电胶/非导电胶装片和焊料装片；
步骤五、参见图7，在步骤四中装好芯片的导线架需连接或需贴装的管脚上涂覆焊料，再在焊料上植入步骤三中切割好的金属片；
步骤六、把步骤五中已装好芯片和金属片的导线架进行回流焊,完成芯片与金属片的贴装；
步骤七、参见图8，对步骤六中完成回流的导线架进行打线作业，将金属丝或金属带由芯片端连接至管脚端金属片上，完成电性连接；
步骤八、将步骤七完成打线作业的导线架采用塑封料进行塑封；
步骤九、将步骤八完成塑封的半成品进行切割或是冲切作业，使原本阵列式塑封体，切割或是冲切独立开来，制得半导体管脚贴装结构。
图9~图13为导线架管脚贴装金属片后的示意图，其中图9为相邻管脚两两相连的贴片形式，图10为所有管脚相连的贴片形式，图11为单个管脚变换电镀方式和管脚高度的贴片形式，图12、图13为跨管脚贴片形式；
除上述实施例外，本实用新型还包括有其他实施方式，凡采用等同变换或者等效替换方式形成的技术方案，均应落入本实用新型权利要求的保护范围之内。

Claims (3)

1.一种半导体管脚贴装结构，其特征在于：它包括引线框架，所述引线框架包括载片台（4）和管脚（1），所述载片台（4）上通过焊料（5）设置有芯片（6），所述管脚（1）上通过焊料（5）设置有金属片（2），所述芯片（6）正面与金属片（2）正面之间通过金属线或金属带（3）相连接。
2.根据权利要求1所述的一种半导体管脚贴装结构，其特征在于：所述金属片（2）的材质为铜、铁、铝或不锈钢材。
3.根据权利要求1所述的一种半导体管脚贴装结构，其特征在于：所述载片台与芯片之间为焊料，也可以为共晶层或粘接胶层。
CN201620681432.8U 2016-07-01 2016-07-01 一种半导体管脚贴装结构 Active CN205789943U (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201620681432.8U CN205789943U (zh) 2016-07-01 2016-07-01 一种半导体管脚贴装结构

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201620681432.8U CN205789943U (zh) 2016-07-01 2016-07-01 一种半导体管脚贴装结构

Publications (1)

Publication Number Publication Date
CN205789943U true CN205789943U (zh) 2016-12-07

Family

ID=58125633

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201620681432.8U Active CN205789943U (zh) 2016-07-01 2016-07-01 一种半导体管脚贴装结构

Country Status (1)

Country Link
CN (1) CN205789943U (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106024745A (zh) * 2016-07-01 2016-10-12 长电科技（宿迁）有限公司 一种半导体管脚贴装结构及其焊接方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106024745A (zh) * 2016-07-01 2016-10-12 长电科技（宿迁）有限公司 一种半导体管脚贴装结构及其焊接方法

Similar Documents

Publication Publication Date Title
CN102789994B (zh) 侧面可浸润半导体器件
US8642394B2 (en) Method of manufacturing electronic device on leadframe
CN101859755B (zh) 一种功率mosfet封装体及其封装方法
CN103811449B (zh) 焊球凸块结构及其形成方法
CN104685615A (zh) 半导体器件的制造方法及半导体器件
CN101960586A (zh) 使用焊料和膜粘合剂将倒装片封装的散热片/加强片接地的方法
CN207743077U (zh) 一种金锡焊盘单层陶瓷电容器
US20190304879A1 (en) Semiconductor device and method formanufacturing the same
CN108493121B (zh) 一种解决双面电路晶元焊料短路的载板制作及封装方法
US9337131B2 (en) Power semiconductor device and the preparation method
CN205789943U (zh) 一种半导体管脚贴装结构
CN106024745A (zh) 一种半导体管脚贴装结构及其焊接方法
CN104617076A (zh) 一种预置胶膜的智能卡载带及其实现方法
CN102646610A (zh) 半导体器件、用于制造半导体器件的方法以及电源装置
CN108807352B (zh) 一种新型led灯丝制作方法
CN105719977A (zh) 倒扣太赫兹肖特基二极管与石英薄膜电路的互联方法
CN105206594B (zh) 单面蚀刻水滴凸点式封装结构及其工艺方法
US8916970B2 (en) Method for welding gold-silicon eutectic chip, and transistor
CN209056520U (zh) 预设有导电凸块的发光二极管载板
CN102163562B (zh) 一种功率半导体管芯的安装方法和同步降压转换器
CN105355567B (zh) 双面蚀刻水滴凸点式封装结构及其工艺方法
CN102034781B (zh) 在引线框架和晶圆上印刷粘接材料的半导体封装及其制造方法
EP2768015A1 (en) Gold/silicon eutectic chip soldering method and transistor
US9165872B2 (en) Chip scale diode package no containing outer lead pins and process for producing the same
US8900926B2 (en) Chip package method

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant