CN108493121B - 一种解决双面电路晶元焊料短路的载板制作及封装方法 - Google Patents

一种解决双面电路晶元焊料短路的载板制作及封装方法 Download PDF

Info

Publication number
CN108493121B
CN108493121B CN201810241152.9A CN201810241152A CN108493121B CN 108493121 B CN108493121 B CN 108493121B CN 201810241152 A CN201810241152 A CN 201810241152A CN 108493121 B CN108493121 B CN 108493121B
Authority
CN
China
Prior art keywords
wafer
support plate
pad
double
sided circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810241152.9A
Other languages
English (en)
Other versions
CN108493121A (zh
Inventor
吴现伟
龙华
郭嘉帅
郑瑞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Fei Xiang Electronic Technology Co Ltd
Original Assignee
Shanghai Fei Xiang Electronic Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Fei Xiang Electronic Technology Co Ltd filed Critical Shanghai Fei Xiang Electronic Technology Co Ltd
Priority to CN201810241152.9A priority Critical patent/CN108493121B/zh
Publication of CN108493121A publication Critical patent/CN108493121A/zh
Priority to PCT/CN2018/104481 priority patent/WO2019179062A1/zh
Application granted granted Critical
Publication of CN108493121B publication Critical patent/CN108493121B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/30Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/273Manufacturing methods by local deposition of the material of the layer connector
    • H01L2224/2731Manufacturing methods by local deposition of the material of the layer connector in liquid form
    • H01L2224/2732Screen printing, i.e. using a stencil
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199Material of the matrix
    • H01L2224/29294Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/292 - H01L2224/29291
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/3005Shape
    • H01L2224/30051Layer connectors having different shapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/305Material
    • H01L2224/30505Layer connectors having different materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205Shape
    • H01L2224/32057Shape in side view
    • H01L2224/32058Shape in side view being non uniform along the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32104Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/32105Disposition relative to the bonding area, e.g. bond pad the layer connector connecting bonding areas being not aligned with respect to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331Disposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • H01L2224/83815Reflow soldering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862Heat curing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83894Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/38Effects and problems related to the device integration
    • H01L2924/384Bump effects
    • H01L2924/3841Solder bridging

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

本发明涉及一种解决双面电路晶元焊料短路的载板制作及封装方法。该方法包括以下步骤:设计双面电路晶元;根据双面电路晶元的厚度、焊盘分布及封装单元空间排布,设计并制作载板;在侧装晶元对应的载板绿油表面位置涂覆非导电胶;在与晶元焊盘对应的载板焊盘涂覆导电胶;侧装粘贴双面电路晶元;载板退出工作台搁置一段时间;烤箱烘烤固化胶体,使非导电胶固化增强晶元与载板结合,使导电胶与载板焊盘及晶元焊盘固化;外观检验确认结合性。本发明所述的方法可以解决双面电路晶元侧装时双侧导电胶因毛细管效应通过接触位置相互爬胶导致的短路问题,提高封装良率;使晶元与载板结合更加稳固。

Description

一种解决双面电路晶元焊料短路的载板制作及封装方法
技术领域
本发明涉及焊接领域,具体涉及一种解决双面电路晶元焊料短路的载板制作及封装方法。
背景技术
晶元,是生产集成电路所用的载体,多指单晶硅圆片,还有砷化镓、碳化硅、氮化镓、磷化铟等化合物圆片。半导体制造工艺中,晶元通常为单面设计制造。但随着各类功能集成的需求越来越多越来越高,对晶体管集成密度要求也越来越高,越来越有挑战性。
侧装贴片,是将晶元吸取并通过两个真空导管支架配合,利用支架前端塑料吸嘴接触并吸附晶元表面,旋转90度,另一支架吸嘴吸取晶元上方侧面,移至贴片位置上方,根据设置下降速度,完成芯片侧装贴片的过程。
晶元表面非焊盘区域通常覆有一层油性有机钝化层,具有亲油性,能够防止非油性物质攀爬扩散,晶元贴装前需分离切割为单颗晶粒,切割道位置会将晶粒四周侧面单晶硅或化合物基底暴露出来,基底不具备亲油或疏油特性,流动性较强流体物质会在其表面攀爬扩散。双面电路晶元侧装过程中会遇到晶元同一侧电路相邻焊盘因焊料在晶元底部侧面基底攀爬短路,或晶元两侧电路焊盘因焊料在晶元底部侧面基底攀爬短路。本发明利用焊料成分特性、载板材料特性、载板结构设计、及封装非导电胶材料工艺运用等,可有效解决焊盘间短路问题。另外,非导电胶在双面电路侧装的封装工艺运用上还有效提升了晶元与载板之间的结合力,进一步提升了封装成品元件的防应力损坏及可靠性等。
发明内容
为了有效解决双面电路晶元焊料短路的问题,本发明拟提供一种解决双面电路晶元焊料短路的载板制作及封装方法,利用焊料成分特性、载板材料特性、载板结构设计、及封装非导电胶材料工艺运用等,可有效解决焊盘间短路问题,并进一步提升了封装成品元件的防应力损坏及可靠性等。
本发明提供一种解决双面电路晶元焊料短路的载板制作及封装方法,其特征在于,该方法包括以下步骤:
步骤S1,设计双面电路晶元;
步骤S2,根据双面电路晶元的厚度、焊盘分布及封装单元空间排布,设计并制作载板;
步骤S3,在晶元对应的载板绿油表面位置涂覆非导电胶;
步骤S4,在与晶元焊盘对应的载板焊盘涂覆导电胶;
步骤S5,侧装粘贴双面电路晶元,晶元自上向下贴装过程中,晶元底部先与非导电胶接触并向下挤压,使非导电胶充满晶元底部对应的载板绿油区域;晶元继续向下贴装,晶元侧面及侧面焊盘与导电胶接触,使导电胶快速与晶元焊盘结合;
步骤S6,载板退出工作台搁置一段时间;
步骤S7,烤箱烘烤固化胶体,使非导电胶固化增强晶元与载板结合,使导电胶与载板焊盘及晶元焊盘固化。
进一步地,所述方法还包括步骤S8,外观检验,确认结合性。
进一步地,所述方法可以用锡膏来代替导电胶,其中步骤S3-S7用如下步骤来代替:
S31、设计制作印刷电路板,根据载板焊锡位置及尺寸,设计并制作相同尺寸印刷钢网;在与晶元焊盘对应的载板焊盘印刷锡膏;
S41、在晶元对应的载板绿油表面位置涂覆非导电胶;
S51、侧装粘贴双面电路晶元,晶元自上向下贴装过程中,使非导电胶充满晶元底部对应载板绿油区域,同时使晶元底部接触位置锡膏塌陷,使晶元侧面电路焊盘与锡膏接触,此时,锡膏与晶元焊盘处于接触但未结合状态;
S61、回流焊导通固化晶元与载板焊盘,回流焊过程在升温区及保温区使半固化锡膏熔化,锡料通过金属间润湿性与载板焊盘及晶元焊盘有效结合,至降温区锡料固化,回流焊接缝焊完成;
S71、烤箱烘烤固化非导电胶,使非导电胶固化,增强晶元与载板结合。
进一步地,步骤S1中,所述晶元厚度在200um~300um之间。
进一步地,步骤S1中,所述晶元的双面电路的非焊盘区域涂覆油性钝化层,所述晶元的底部无涂覆油性钝化层。
进一步地,在步骤S2中,设计并制作载板时,将晶元焊盘处的载板绿油做开窗处理,并露出载板与晶元对应焊盘。
进一步地,步骤S6中,所述搁置时间为3~10分钟。
进一步地,在步骤S31中,所述印刷钢网厚度可选择60um、80um。
进一步地,所述锡膏包括锡银、锡银铜、锡铜,呈半固化形式。
进一步地,烤箱烘烤固化导电胶或非导电胶,烘烤条件相同,温度为175度,时间包含升温、恒温、降温共2小时。
本发明取得了以下有益效果:
解决双面电路晶元侧装时,双侧导电胶因毛细管效应通过晶元与载板接触位置相互爬胶导致的短路问题,从而可提高封装良率,降低不良损失;
使晶元与载板结合更加稳固,有效防止产品因内部或外部应力造成晶元与载板焊缝脱落,提升了封装成品元件的防应力损坏及可靠性。
附图说明
图1是本发明采用导电胶的方法流程示意图。
图2是本发明采用锡膏的方法流程示意图。
图3是本发明双面电路晶元侧装示意图。
图4是通用晶元焊盘尺寸及间距示意图。
图5是双面电路晶元侧装之载板焊盘开窗示意图。
图6是本发明双面电路晶元侧装之涂覆导电胶和涂覆非导电胶剖面图。
图7是本发明双面电路晶元侧装之印刷锡膏和涂覆非导电胶剖面图。
图8是本发明载板俯视图。
图9是本发明双面电路晶元侧装电路剖面图。
图10是本发明双面电路晶元侧装非电路面载板焊盘剖面图。
图11是本发明双面电路晶元侧装非电路面非载板焊盘剖面图。
具体实施方式
以下结合附图和实施例,对本发明的具体实施方式进行更加详细的说明,以便能够更好地理解本发明的方案及其各个方面的优涂覆。然而,以下描述的具体实施方式和实施例仅是说明的目的,而不是对本发明的限制。
一种解决双面电路晶元焊料短路的载板制作及封装方法,如图1所示,图1是本发明采用导电胶的方法流程示意图。该方法包括以下步骤:
步骤S1,设计双面电路晶元,所述晶元厚度在200um~300um之间。
受限于当前封装侧装吸嘴大小,所述晶元的厚度≥200um最佳,受限于晶元切割工艺,所述晶元的厚度≤300um最佳。随着技术提升,晶元切割工艺瓶颈或将拓宽,封装工艺也进一步加强,届时将更适合大面积晶元产品。
晶元两侧表面非焊盘区域通常会涂覆一层油性钝化层,无钝化层的焊盘区域通常是露出金属铝或金成分;晶元底部因分隔划片晶粒使单晶硅或化合物基底暴露,此处没有涂覆油性钝化层,没有明显亲油或疏油特性。
步骤S2,根据双面电路晶元的厚度、焊盘分布及封装单元空间排布,设计并制作载板。
如图5所示,图5是双面电路晶元侧装之载板焊盘开窗示意图。设计并制作载板时,将晶元焊盘处的载板绿油做开窗处理,并露出载板与晶元对应焊盘。
步骤S3,在晶元对应的载板绿油表面位置涂覆“一”字或“十”字非导电胶。
非导电胶有明显亲油性特征,涂覆胶后非导电胶会因其亲油性及毛细管效应,沿载板表面绿油缓慢扩散。
涂覆非导电胶其作用一,隔离两侧导电胶,避免双面晶元两侧导电胶因毛细管效应沿晶元底部相互爬胶导致短路;涂覆非导电胶其作用二,固定侧装晶元,通过非导电胶将晶元底部与载板表面绿油结合固化。
图6是本发明双面电路晶元侧装之涂覆导电胶和涂覆非导电胶剖面图。图8是本发明载板俯视图。由图6和图8可见,本发明的一个实施例,为了避免两侧位置的导电胶及焊盘发生短路,在载板中间大块的绿油表面位置涂覆的非导电胶,良好的隔离了两侧位置的导电胶及焊盘,避免了短路。并且使晶元和载板结合固化。
图9是本发明双面电路晶元侧装电路剖面图。由图9可见,本发明的另一个实施例,为了避免相邻位置的导电胶及焊盘发生短路,在载板焊盘与焊盘的中间位置的小区域绿油表面位置涂覆的非导电胶,良好的隔离了相邻位置的导电胶及焊盘,避免了短路。并且使晶元和载板结合固化。
图10是本发明双面电路晶元侧装非电路面载板焊盘剖面图。图11是本发明双面电路晶元侧装非电路面非载板焊盘剖面图。如图10、图11可见,本发明的另一个实施例,为了避免晶元电路与载板电路之间发生短路,在晶元和载板解决的侧面绿油表面位置涂覆的非导电胶,良好的隔离了晶元电路和载板电路,避免了短路。并且使晶元和载板结合固化。
步骤S4,在与晶元焊盘对应的载板焊盘涂覆导电胶。
所述导电胶需满足稀释剂含量低、银粉含量高、粘稠度高的特性。导电胶成分中的银金属疏油,不易导流至晶元表面钝化层,但因含有稀释剂等液态有机亲油性成分,会使导电胶沿晶元底部基底裸露表面导流,导致载板相邻焊盘短路。
如图3所示,图3是本发明双面电路晶元侧装示意图。晶元焊盘和载板焊盘通过焊料即导电胶进行粘贴结合。晶元电路为双面设计。
如图4所示,图4是通用晶元焊盘尺寸及间距示意图。所述焊盘间距≥60um,焊盘长度≥50um。
步骤S5,侧装粘贴双面电路晶元,晶元自上向下贴装过程中,晶元底部将先与非导电胶接触并向下挤压,使非导电胶充满晶元底部对应的载板绿油区域;晶元继续向下贴装,晶元侧面及侧面焊盘将与导电胶接触,因银金属疏油特性及与晶元焊盘表面金属铝或金的高润湿性,导电胶将快速与晶元焊盘结合。
如图3所示,图3是本发明双面电路晶元侧装示意图。晶元焊盘和载板焊盘位置相对应,通过焊料即导电胶进行粘贴结合。
步骤S6,载板退出工作台搁置3到10分钟,此过程使导电胶与晶元焊盘充分接触。
步骤S7,烤箱烘烤固化胶体,使非导电胶固化增强晶元与载板结合,使导电胶与载板焊盘及晶元焊盘固化。
烤箱烘烤固化导电胶或非导电胶,烘烤条件相同,温度为175度,时间包含升温、恒温、降温共2小时。
步骤S8,外观检验,确认结合性。
所述方法可以用锡膏来代替导电胶,如图2所示,图2是本发明采用锡膏的方法流程示意图。上述方法中的步骤S3-S7用如下步骤S31-S71来代替。
S31、设计制作印刷电路板,根据载板焊锡位置及尺寸,设计并制作相同尺寸印刷钢网。所述印刷钢网厚度可选择60um、80um;在与晶元焊盘对应的载板焊盘印刷锡膏。所述锡膏包括锡银、锡银铜、锡铜等。所述锡膏呈半固化形式,粘稠度高。
S41、在晶元对应的载板绿油表面位置涂覆“一”字或“十”字非导电胶。
非导电胶有明显亲油性特征,涂覆胶后非导电胶会因其亲油性及毛细管效应,沿载板表面绿油缓慢扩散。
涂覆非导电胶其作用一,隔离两侧导电胶,避免双面晶元两侧导电胶因毛细管效应沿晶元底部相互爬胶导致短路;涂覆非导电胶其作用二,固定侧装晶元,通过非导电胶将晶元底部与载板表面绿油结合固化。
图7是本发明双面电路晶元侧装之印刷锡膏和涂覆非导电胶剖面图。如图7可见,本发明的一个实施例,为了避免两侧位置的锡膏及焊盘发生短路,在载板中间大块的绿油表面位置涂覆的非导电胶,良好的隔离了两侧位置的锡膏及焊盘,避免了短路。并且使晶元和载板结合固化。
S51、侧装粘贴双面电路晶元,晶元自上向下贴装过程中,因锡膏电路板厚度不同选择,晶元底部将可能先与非导电胶接触,也可能先与锡膏接触,晶元继续向下贴装挤压,使非导电胶充满晶元底部对应载板绿油区域,同时使晶元底部接触位置锡膏塌陷,使晶元侧面线路焊盘与锡膏接触,此时,锡膏与晶元焊盘处于接触但未结合状态。
S61、回流焊导通固化晶元与载板焊盘,考虑到若先进行烤箱加热固化非导电胶,会导致晶元焊盘及锡膏在烤箱加热过程被氧化,需先进性锡膏的回流焊接流程,回流焊过程在升温区及保温区使半固化锡膏熔化,锡料通过金属间润湿性与载板焊盘及晶元焊盘有效结合,至降温区锡料固化,回流焊接缝焊完成。
S71、烤箱烘烤固化非导电胶,使非导电胶固化,增强晶元与载板结合,非导电胶烘烤条件通常温度通常为175度,时间包含升温、恒温、降温共2小时。
S8、外观检验,确认结合性。
需要说明的是,以上参照附图所描述的各个实施例仅用以说明本发明而非限制本发明的范围,本领域的普通技术人员应当理解,在不脱离本发明的精神和范围的前提下对本发明进行的修改或者等同替换,均应涵盖在本发明的范围之内。此外,除上下文另有所指外,以单数形式出现的词包括复数形式,反之亦然。另外,除非特别说明,那么任何实施例的全部或一部分可结合任何其它实施例的全部或一部分来使用。

Claims (10)

1.一种解决双面电路晶元焊料短路的载板制作及封装方法,其特征在于,该方法包括以下步骤:
步骤S1,设计双面电路晶元;
步骤S2,根据双面电路晶元的厚度、焊盘分布及封装单元空间排布,设计并制作载板;
步骤S3,在晶元对应的载板绿油表面位置涂覆非导电胶;
步骤S4,在与晶元焊盘对应的载板焊盘涂覆导电胶;
步骤S5,侧装粘贴双面电路晶元,晶元自上向下贴装过程中,晶元底部先与非导电胶接触并向下挤压,使非导电胶充满晶元底部对应的载板绿油区域;晶元继续向下贴装,晶元侧面及侧面焊盘与导电胶接触,使导电胶快速与晶元焊盘结合;
步骤S6,载板退出工作台搁置一段时间;
步骤S7,烤箱烘烤固化胶体,使非导电胶固化增强晶元与载板结合,使导电胶与载板焊盘及晶元焊盘固化。
2.根据权利要求1所述的解决双面电路晶元焊料短路的载板制作及封装方法,其特征在于,所述方法还包括步骤S8,外观检验,确认结合性。
3.根据权利要求1所述的解决双面电路晶元焊料短路的载板制作及封装方法,其特征在于,用锡膏代替导电胶,其中步骤S3-S7用如下步骤来代替:
S31、设计制作印刷电路板,根据载板焊锡位置及尺寸,设计并制作相同尺寸印刷钢网;在与晶元焊盘对应的载板焊盘印刷锡膏;
S41、在晶元对应的载板绿油表面位置涂覆非导电胶;
S51、侧装粘贴双面电路晶元,晶元自上向下贴装过程中,使非导电胶充满晶元底部对应载板绿油区域,同时使晶元底部接触位置锡膏塌陷,使晶元侧面电路焊盘与锡膏接触,此时,锡膏与晶元焊盘处于接触但未结合状态;
S61、回流焊导通固化晶元与载板焊盘,回流焊过程在升温区及保温区使半固化锡膏熔化,锡料通过金属间润湿性与载板焊盘及晶元焊盘有效结合,至降温区锡料固化,回流焊接缝焊完成;
S71、烤箱烘烤固化非导电胶,使非导电胶固化,增强晶元与载板结合。
4.根据权利要求1所述的解决双面电路晶元焊料短路的载板制作及封装方法,其特征在于,步骤S1中,所述晶元厚度在200um~300um之间。
5.根据权利要求1所述的解决双面电路晶元焊料短路的载板制作及封装方法,其特征在于,步骤S1中,所述晶元的双面电路的非焊盘区域涂覆油性钝化层,所述晶元的底部无涂覆油性钝化层。
6.根据权利要求1所述的解决双面电路晶元焊料短路的载板制作及封装方法,其特征在于,在步骤S2中,设计并制作载板时,将晶元焊盘处的载板绿油做开窗处理,并露出载板与晶元对应焊盘。
7.根据权利要求1所述的解决双面电路晶元焊料短路的载板制作及封装方法,其特征在于,步骤S6中,所述搁置时间为3~10分钟。
8.根据权利要求3所述的解决双面电路晶元焊料短路的载板制作及封装方法,其特征在于,在步骤S31中,所述印刷钢网厚度为60um或80um。
9.根据权利要求3所述的解决双面电路晶元焊料短路的载板制作及封装方法,其特征在于,所述锡膏包括锡银、锡银铜、锡铜,呈半固化形式。
10.根据权利要求3所述的解决双面电路晶元焊料短路的载板制作及封装方法,其特征在于,烤箱烘烤固化非导电胶,温度为175度,时间包含升温、恒温、降温共2小时。
CN201810241152.9A 2018-03-22 2018-03-22 一种解决双面电路晶元焊料短路的载板制作及封装方法 Active CN108493121B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201810241152.9A CN108493121B (zh) 2018-03-22 2018-03-22 一种解决双面电路晶元焊料短路的载板制作及封装方法
PCT/CN2018/104481 WO2019179062A1 (zh) 2018-03-22 2018-09-07 一种解决双面电路晶元焊料短路的载板制作及封装方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810241152.9A CN108493121B (zh) 2018-03-22 2018-03-22 一种解决双面电路晶元焊料短路的载板制作及封装方法

Publications (2)

Publication Number Publication Date
CN108493121A CN108493121A (zh) 2018-09-04
CN108493121B true CN108493121B (zh) 2019-09-20

Family

ID=63319310

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810241152.9A Active CN108493121B (zh) 2018-03-22 2018-03-22 一种解决双面电路晶元焊料短路的载板制作及封装方法

Country Status (2)

Country Link
CN (1) CN108493121B (zh)
WO (1) WO2019179062A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108493121B (zh) * 2018-03-22 2019-09-20 上海飞骧电子科技有限公司 一种解决双面电路晶元焊料短路的载板制作及封装方法
CN109650323B (zh) * 2018-12-24 2020-11-03 烟台艾睿光电科技有限公司 一种焊料隔离结构以及电子器件
CN116314539B (zh) * 2023-03-31 2023-11-21 广东省旭晟半导体股份有限公司 一种具有增强led可靠性的封装结构及其制备工艺

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002198463A (ja) * 2000-12-26 2002-07-12 Canon Inc チップサイズパッケージおよびその製造方法
US9101058B2 (en) * 2012-07-17 2015-08-04 Marvell World Trade Ltd. IC package and assembly
TWI446844B (zh) * 2012-07-25 2014-07-21 Wistron Corp 印刷電路板及印刷電路板之製造方法
CN103311205A (zh) * 2013-05-16 2013-09-18 华天科技(西安)有限公司 一种防止芯片凸点短路的封装件及其制造工艺
CN104486907B (zh) * 2014-12-10 2017-08-11 华进半导体封装先导技术研发中心有限公司 高频ipd模块三维集成晶圆级封装结构及封装方法
CN108493121B (zh) * 2018-03-22 2019-09-20 上海飞骧电子科技有限公司 一种解决双面电路晶元焊料短路的载板制作及封装方法

Also Published As

Publication number Publication date
WO2019179062A1 (zh) 2019-09-26
CN108493121A (zh) 2018-09-04

Similar Documents

Publication Publication Date Title
CN103811449B (zh) 焊球凸块结构及其形成方法
CN108493121B (zh) 一种解决双面电路晶元焊料短路的载板制作及封装方法
CN101960586B (zh) 使用焊料和膜粘合剂将倒装片封装的散热片/加强片接地的方法
CN207743077U (zh) 一种金锡焊盘单层陶瓷电容器
CN107481977A (zh) 一种晶圆级扇出型封装结构及封装方法
CN207781646U (zh) 一种led芯片倒装焊接结构和led灯珠
CN102891240A (zh) 倒装结构的发光二极管及其制备方法
KR20100080352A (ko) 금속 범프를 가진 반도체 패키지 기판
CN206877985U (zh) 半导体封装装置和半导体引线框架
CN112271244A (zh) 一种新型的倒装led实现结构及方法
CN108183091A (zh) 一种封装结构及其工艺方法
CN110635016B (zh) 一种miniled基板封装方法
CN208889645U (zh) 高导电低阻值的芯片封装结构
TWI296839B (en) A package structure with enhancing layer and manufaturing the same
CN105355567A (zh) 双面蚀刻水滴凸点式封装结构及其工艺方法
CN102244021B (zh) Low-k芯片封装方法
CN104716129B (zh) 集成堆叠式多芯片的半导体器件及其制备方法
CN104465427A (zh) 封装结构及半导体工艺
CN208738287U (zh) 一种新型的led数码管数码屏生产固定装置
CN205789943U (zh) 一种半导体管脚贴装结构
CN109065515B (zh) 高导电低阻值的芯片封装结构及其制备方法
CN208655696U (zh) 一种led倒装芯片封装器件结构
CN105914268A (zh) 一种led倒装工艺及倒装结构
CN105206594A (zh) 单面蚀刻水滴凸点式封装结构及其工艺方法
CN104241236B (zh) 一种半导体倒装封装结构

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant