CN107689357A - 芯片附接方法和基于这种方法制造的半导体装置 - Google Patents

芯片附接方法和基于这种方法制造的半导体装置 Download PDF

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CN107689357A
CN107689357A CN201710650631.1A CN201710650631A CN107689357A CN 107689357 A CN107689357 A CN 107689357A CN 201710650631 A CN201710650631 A CN 201710650631A CN 107689357 A CN107689357 A CN 107689357A
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chip
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semiconductor
semiconductor chip
attached
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CN107689357B (zh
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G·R·加尔宾
C·W·李
J·马勒
B·赖歇特
P·施特罗贝尔
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

一种半导体装置，包括载体、半导体芯片和芯片附接材料，芯片附接材料布置在载体与半导体芯片之间。芯片附接材料的填角高度小于半导体芯片的高度的大约95％。芯片附接材料在半导体芯片的朝着芯片附接材料的主表面的边缘之上的最大延伸尺度小于大约200微米。

Description

芯片附接方法和基于这种方法制造的半导体装置
技术领域
本公开总体涉及半导体技术。更特别地，本公开涉及芯片附接方法和基于这种方法制造的半导体装置。
背景技术
在半导体装置的制造中，半导体芯片可借助于芯片附接材料附接至载体。芯片附接材料的不期望地沉积在半导体芯片的特定位置处的部分可能影响半导体装置的可靠性。在半导体技术中，半导体芯片的尺寸随着时间的推移一直在减小，且在未来的应用场合将进一步减小。半导体装置的制造商寻求能够提高可靠性、减小尺寸和降低制造成本的解决方案。
发明内容
各个方面涉及一种半导体装置，其包括载体、半导体芯片和芯片附接材料，芯片附接材料布置在载体与半导体芯片之间。芯片附接材料的填角高度小于半导体芯片的高度的大约95％，且芯片附接材料在半导体芯片的朝着芯片附接材料的主表面的边缘之上的最大延伸尺度小于大约200微米。
各个方面涉及一种方法，其包括以下措施：提供载体；将芯片附接材料沉积到载体上；和将半导体芯片布置在芯片附接材料上，其中，半导体芯片的朝着芯片附接材料的主表面至少部分地接触芯片附接材料，其中，在将半导体芯片布置在芯片附接材料上后紧接着，芯片附接材料在所述主表面的边缘之上的第一最大延伸尺度小于大约100微米。
各个方面涉及一种方法，其包括以下措施：提供载体；将芯片附接材料沉积到载体上；将半导体芯片布置在芯片附接材料上；和在半导体芯片的侧表面处形成芯片附接材料的填角，其中，形成填角唯一地基于芯片附接材料沿着半导体芯片的侧表面的蠕变。
附图说明
附图被包括以提供对各方面的进一步理解，并且被并入本说明书并构成本说明书的一部分。所述附图示出各方面并同描述一起起到解释各方面的原理的作用。当通过参照下文的详细描述更好地理解其他方面和各方面的许多预期的优点时，它们将被容易地领会。附图中的各元件不一定相对彼此按比例绘制。相似的附图标记表示相应的类似部分。
图1包括图1A和图1B，其中，图1A示意性地示出了根据本公开的半导体装置100的侧剖视图，且图1B示出了半导体装置100的俯视图。
图2示出了根据本公开的方法200的流程图。方法200提供了将半导体芯片附接至载体的可能性。
图3示出了根据本公开的方法300的流程图。方法300提供了将半导体芯片附接至载体的可能性。
图4包括图4A-4H，其示意性地示出了根据本公开用于制造半导体装置400的方法。方法400提供了将半导体芯片附接至载体的可能性。
具体实施方式
在以下详细说明中，参考附图，在附图中以图示的方式示出本公开可以实践的具体方面。就此而言，关于所描述的图的取向可以使用诸如“顶”、“底”、“前”、“后”等的方向术语。因为所描述的装置的部件可以定位在多个不同取向上，所以所述方向术语可以用于阐述目的并且绝不是限定性的。可以使用其他方面，并且可以做出结构改变或逻辑改变而不偏离本公开的构思。因此，以下详细说明不用于限制，并且本公开的构思由所附权利要求限定。
本文描述的器件可包括一个或更多个半导体芯片(或半导体芯片件)。所述半导体芯片可以是不同类型的，并且可通过不同的技术来制造。通常，半导体芯片可包括集成电路、无源电子部件、有源电子部件等。集成电路可设计成逻辑集成电路、模拟集成电路、混合信号集成电路、功率集成电路等。半导体芯片不需要由特定的半导体材料制造，并且可包含不是半导体的无机和/或有机材料，例如绝缘体、塑料、金属等。在一示例中，半导体芯片可由元素半导体材料、例如Si等制成。在另一示例中，半导体芯片可由化合物半导体材料、例如GaN、SiC、SiGe、GaAs等制成。半导体芯片在半导体芯片的背侧上可附加地包括一个或更多个金属层，例如以用于具有垂直电流流动的、在半导体芯片背侧处需要欧姆接触的半导体装置。
半导体芯片可具有两个相反的主表面以及连接主表面的侧表面。半导体芯片的电极可布置在半导体芯片的一个主表面或两个主表面上。半导体芯片的有源主表面可包括电极和/或有源结构，例如微电子部件和集成电路。通常，半导体芯片可以是任意尺寸。尤其地，半导体芯片(的侧表面)的高度可小于大约400微米，更特别地小于大约150微米，甚至更特别地小于大约100微米至大约20微米。半导体芯片的主表面可具有矩形形状，更特别地具有平方形形状。半导体芯片的主表面的表面面积可处于大约0.5平方毫米至大约50平方毫米的范围内，更特别地处于大约1.5平方毫米至大约25平方毫米的范围内。
本文描述的装置可包括载体，一个或更多个半导体芯片可布置在所述载体之上。通常，载体可由金属、合金、电介质、塑料、陶瓷等中的至少一种来制造。载体可具有均匀结构，但是也可提供内部结构，比如具有电重新分配功能的传导路径。在一个示例中，载体可包括引线、芯片焊盘或者具有一个或更多个引线和一个或更多个芯片焊盘的引线框架。引线框架可由金属和/或金属合金制造，尤其由铜、铜合金、镍、铁镍、铝、铝合金、钢、不锈钢等中的至少一种制造。引线框架可以是镀有导电材料的预镀式引线框架，所述导电材料例如是铜、银、钯、金、镍、铁镍、镍磷等中的至少一种。引线框架的表面、尤其是芯片焊盘的芯片安装表面，可粗糙化或结构化。在另一示例中，载体可包括印刷电路板。在另一示例中，载体可包括陶瓷和镀有金属的陶瓷中的至少一种。在又一示例中，载体可包括功率电子衬底，例如直接结合铜衬底、有源金属钎焊衬底、隔离金属衬底等。在又一示例中，载体可包括(例如陶瓷)衬底，该衬底可配置成：能借助于衬底中所包括的重新分布结构来提供衬底内的或通过衬底的电信号的重新分布。
本文所描述的装置可包括芯片附接材料。通常，芯片附接材料可以是配置成能将半导体芯片附接或固定至载体的任何类型的材料。尤其地，芯片附接材料可配置成：能以液态或粘性形式沉积到物体、例如载体的表面上。芯片附接材料可在它沉积后、尤其在将半导体芯片布置在芯片附接材料后硬化。在一个示例中，芯片附接材料的硬化可基于可在炉中实施的固化过程。固化时间可处于大约10分钟至大约3小时的范围内，且固化温度可处于大约100摄氏度至大约300摄氏度的范围内。
在一个示例中，芯片附接材料可以是粘合膏，尤其是是聚合物基粘合膏或环氧树脂基粘合膏。未改性的聚合物基粘合膏可以是绝缘性的或可呈现低导电和/或导热性。合适的填充颗粒可用于使传导性粘合膏具有增加的导电和/或导热性。填充颗粒可添加成在聚合物基质内形成网络，从而电子和/或热量可流动穿过颗粒接触点，以便使该混合物导电和/或导热。填充颗粒例如可包括银、铜、镍、金、铝、它们的混合物中的至少一种。填充颗粒例如也可包括二氧化硅、氧化铝、矾土、氮化硼、碳化硅、氮化镓、它们的混合物中的至少一种。对于银填充颗粒的情况，芯片附接材料可特别地包括或可对应于银导电粘合膏。填充颗粒的直径可处于大约50纳米至大约10微米的范围内。在另一示例中，芯片附接材料可包括焊接材料、焊膏、烧结膏中的至少一种。
芯片附接材料的热导率可大于大约0.5W/(m·K)，更特别地大于大约5W/(m·K)，甚至更特别地大于大约10W/(m·K)。热导率可具有达大约250W/(m·K)的值。
图1包括图1A和图1B，其中，图1A示意性地示出了根据本公开的半导体装置100的侧剖视图，且图1B示出了半导体装置100的俯视图。半导体装置100以总体的方式示出，以便定性地说明本公开的多个方面。半导体装置100可包括为清楚起见而未示出的其他部件。
半导体装置100可包括载体10、半导体芯片12和芯片附接材料14，芯片附接材料14布置在载体10与半导体芯片12之间。芯片附接材料14的填角高度A可小于半导体芯片12的高度B的大约95％。芯片附接材料14可在半导体芯片12的侧表面16处形成填角，其中，填角高度A可规定为侧表面16的被芯片附接材料14覆盖的部分的高度。即，如果侧表面16完全未被芯片附接材料14覆盖，填角高度A就可以是半导体芯片12的高度B的0％；且如果侧表面16被芯片附接材料14完全覆盖，填角高度A就可以是半导体芯片12的高度B的100％。替代性地，填角高度A可规定为半导体芯片12的高度B与侧表面16的未被芯片附接材料14覆盖的部分的高度C之间的差。如图1B所示，尤其当在大致垂直于半导体芯片12的主表面18的方向上观看时，芯片附接材料14在半导体芯片12的朝着芯片附接材料14的主表面18边缘之上的最大延伸尺度D可小于大约200微米。
图2和图3示意性地示出了根据本公开的方法200和300的流程图。方法200和300以总体的方式示出，以便定性地说明本公开的多个方面。方法200和300中的每个均可包括为清楚起见而未示出的其他方面。例如，方法200和300中的每个均可通过联系图4A-4H所描述的任何方面而扩展。
图2的方法200可包括以下措施。在措施20，可提供载体。在措施22，可将芯片附接材料沉积到载体上。在措施24，可将半导体芯片布置在芯片附接材料上，其中，半导体芯片的朝着芯片附接材料的主表面至少部分地接触芯片附接材料。在将半导体芯片布置在芯片附接材料上后紧接着，芯片附接材料在所述主表面的边缘之上的第一最大延伸尺度小于大约100微米。
图3的方法300可包括以下措施。在措施26，可提供载体。在措施28，可将芯片附接材料沉积到载体上。在措施30，可将半导体芯片布置在芯片附接材料上。在措施32，在半导体芯片的侧表面处形成芯片附接材料的填角，其中，形成填角唯一地基于芯片附接材料沿着半导体芯片的侧表面的蠕变。
图4A-4H示意性地示出了用于制造半导体装置400的方法，半导体装置400的剖视图在图4G中示出。半导体装置400可视为半导体装置100的一个实施方式，从而以下所描述的半导体装置400的细节可类似地应用于半导体装置100。此外，图4A-4H的方法可视为图2和图3所示的方法的一个实施方式。以下所描述的方法400的细节因而可类似地应用于图2和图3的方法。
图4A中，可提供载体10。载体10可以是配置成能承载半导体芯片的任何类型的物体，并在半导体技术中用于该目的。载体10可提供适合于安装半导体芯片的至少一个芯片安装表面34。载体100可包括或可对应于引线、芯片焊盘、引线框架、印刷电路板、陶瓷、镀有金属的陶瓷、衬底、功率电子衬底中的至少一种。
图4B中，可将芯片附接材料14沉积在载体10的芯片安装表面34上。芯片附接材料14可以是配置成能将半导体芯片附接或固定至载体10的任何类型的材料。例如，芯片附接材料14可包括或可对应于粘合膏、导电粘合膏、银导电粘合膏、焊接材料、焊膏、烧结膏中的至少一种。在一个示例中，芯片附接材料14可包括导电和导热填充颗粒中的至少一种(未示出)以及聚合材料。在此，填充颗粒例如可包括银、铜、镍、金、铝、它们的混合物中的至少一种。填充颗粒例如也可包括二氧化硅、氧化铝、矾土、氮化硼、碳化硅、氮化镓、它们的混合物中的至少一种。芯片附接材料14的热导率可大于大约0.5W/(m·K)，更特别地大于大约5W/(m·K)，甚至更特别地大于大约10W/(m·K)。热导率可具有达大约250W/(m·K)的值。
芯片附接材料14例如可通过使用刮涂技术、印刷技术、分配技术等中的至少一种来沉积。所选的技术可取决于所用芯片附接材料14的类型。尤其地，芯片附接材料14可以以液态形式沉积在芯片安装表面34上，且可随后在将半导体芯片布置在芯片附接材料14上后硬化或固化。
图4C示出了图4B的平面俯视图。虚线矩形R表示要在载体10之上安装在芯片附接材料14上的半导体芯片的主表面的轮廓或形状。通常，当在大致垂直于芯片安装表面34的方向上观看时，沉积在载体10上的芯片附接材料14的轮廓或形状可以是任意的。图4C示出了一个可使用的示例性轮廓S。示例性轮廓S可包括中间部分和多个臂部，所述中间部分可大致布置在矩形R的中心，所述多个臂部从中间部分延伸至矩形R的角落。尤其地，沉积的芯片附接材料14的轮廓S可完全处于半导体芯片的轮廓R内。芯片附接材料14的覆盖芯片安装表面34的表面面积(即，轮廓S内的面积)可处于半导体芯片的主表面的表面面积(即，轮廓R内的面积)的大约20％至大约80％的范围内，更特别地处于大约40％至大约60％的范围内。
图4D中，可提供任意类型的半导体芯片12。半导体芯片12的高度B可小于大约400微米，更特别地小于大约150微米，更特别地小于大约120微米，更特别地小于大约100微米，甚至更特别地小于大约60微米至大约20微米。半导体芯片12的朝着芯片附接材料14的主表面18可具有矩形形状，更特别地具有平方形形状。主表面18的表面面积可处于大约0.5平方毫米至大约50平方毫米的范围内，更特别地处于大约1.5平方毫米至大约25平方毫米的范围内。例如，主表面18可对应于银层、金层、二氧化硅层中的一种。
半导体芯片12可通过任何合适的技术来提供。在图4D的示例中，半导体芯片12可借助于臂38来提供，臂38可配置成能保持半导体芯片12并使它沿着任何空间方向移动，尤其朝着芯片附接材料14移动。在一个示例中，臂38可以是抓放机械(未示出)的臂。半导体芯片12可移动至图4D所示的位置，其中，半导体芯片12的主表面18可布置成大致平行于芯片安装表面34和/或芯片附接材料14的上表面。
图4E中，半导体芯片12可从臂38释放。从臂38的释放可尤其在半导体芯片12的主表面18已经至少部分地接触芯片附接材料14时实施。在一个示例中，图4E可示出在将半导体芯片12附接至芯片附接材料14后紧接着的布置情况。在另一示例中，图4E可示出在将半导体芯片12附接至芯片附接材料14之后不久的布置情况，例如不多于大约5秒之后，更特别地不多于大约3秒之后，甚至更特别地不多于大约1秒之后。
图4F示出了图4E的平面俯视图。芯片附接材料14的在半导体芯片12的主表面18的边缘之上的第一最大延伸尺度D1可小于大约100微米，更特别地小于大约80微米，更特别地小于大约60微米，甚至更特别地小于大约40微米。
图4G中，芯片附接材料14的填角40可在半导体芯片12的侧表面16处形成。尤其地，图4G可示出静止状态下的布置情况，其中，芯片附接材料14的自流动可结束。因此，填角40可在芯片附接材料14的自流动过程中形成。形成填角40可(尤其唯一地)基于芯片附接材料14沿着半导体芯片12的侧表面16在向上方向上的蠕变。即，无附加力可施加来将半导体芯片12推入芯片附接材料14。芯片附接材料14沿着半导体芯片12的侧表面16的蠕变可基于芯片附接材料14与半导体芯片12的侧表面16之间的粘附力。换言之，芯片附接材料14的蠕变可基于毛细作用。因此，填角40可具有弯月面的形状，尤其是凹形弯月面的形状。
芯片附接材料14的布置在载体10与半导体芯片12之间的部分可称为粘合层。粘合层的厚度F在半导体芯片12的主表面18上可基本上不变，但由于过程误差可自然地变化。粘合层厚度F的平均值可处于大约10微米至大约80微米的范围内，更特别地处于大约20微米至大约50微米的范围内。在图4G的示例中，最左的粘合层厚度FL可不同于最右的粘合层厚度FR。所产生的半导体芯片12和/或芯片附接材料14的倾斜度(即，差FL-FR)可小于大约15微米。
图4H以芯片附接材料14的静止状态示出了的图4G的平面俯视图。在如上所述的芯片附接材料14的自流动和芯片附接材料14的蠕变过程中，芯片附接材料14的部分可在半导体芯片12的主表面18的边缘之上进一步延伸。芯片附接材料14在半导体芯片12的主表面18的边缘之上的第二最大延伸尺度D2可小于大约200微米，更特别地小于大约150微米，甚至更特别地小于100微米。尤其地，第二最大延伸尺度D2可大于或等于第一最大延伸尺度D1。图4H的第二最大延伸尺度D2可对应于图1的最大延伸尺度D。
在主表面18的边缘的部分上，芯片附接材料14可能不在边缘之上延伸。在图4G的示例中，芯片附接材料14在主表面18的三个角落(左下，右下，右上)处可不在主表面18的边缘上延伸。芯片附接材料14在半导体芯片12的主表面18的边缘之上可在边缘的整个长度的大约50％以上延伸，更特别地在边缘的整个长度的大约75％以上延伸，更特别地在边缘的整个长度的大约90％以上延伸，甚至更特别地在边缘的整个长度的大约95％以上延伸。参照图1B的示例，芯片附接材料14在主表面18的边缘之上可在边缘的整个长度的100％上延伸，即，在边缘的每个位置处都延伸。
图4A-4H的方法也可包括为清楚起见而未示出的措施。例如，该方法可包括另一措施，在该另一措施中，芯片附接材料14可在芯片附接材料14达到静止状态后硬化。芯片附接材料14的硬化例如可基于固化过程。固化时间可处于大约10分钟至大约3小时的范围内，且固化温度可处于大约100摄氏度至大约300摄氏度的范围内。另外，该布置结构的一个或更多个部件可嵌入包封材料中，所述包封材料可包括层压材料、环氧树脂、填充的环氧树脂、玻璃纤维填充的环氧树脂、酰亚胺、热塑性塑料、热固性聚合物、聚合物混合物中的至少一种。参照图4G，包封材料尤其可布置在半导体芯片12、芯片附接材料14和芯片安装表面34之上。
与其他装置和方法相比，根据本公开的装置和方法可提供以下效果和/或优点。所列出的效果既不是排他的，也不是限制性的。
根据本公开，可减小芯片附接材料在半导体芯片的主表面的边缘之上的最大延伸尺度。因此，更大的半导体芯片可布置在给定尺寸的载体上。另外，可减少所需的芯片附接材料的量。此外，可降低由芯片附接材料的溢流所引起的污染。另外，可降低包封材料从芯片附接材料层离的风险。
根据本公开，可省去芯片附接材料在半导体芯片的上主表面上的溢流。因此，可降低芯片附接材料损害半导体芯片的上主表面上的接合线连接的风险。另外，可降低半导体芯片的上主表面上的短路风险。因此，可将高度减小的半导体芯片牢固地附接至载体。根据本公开的装置可提高装置可靠性。
根据本公开，可提高粘合层厚度的均匀性。另外，可减少粘合层中的空隙的量。
如本说明书中所使用的，术语“连接的”、“耦接的”、“电连接的”和/或“电耦接的”不一定表示元件必须直接连接或耦接在一起。可在“连接的”、“耦接的”、“电连接的”或“电耦接的”元件之间设置中间元件。
此外，关于例如形成或定位在物体的表面“之上”的材料层而使用的词语“之上”在此可用于表示材料层可定位(例如形成、沉积等)在相关表面的“直接上方”、例如与相关表面直接接触。关于例如形成或定位在一表面之上的材料层所使用的词语“之上”在此也可用于表示材料层可定位(例如形成、沉积等)在相关表面的“间接上方”且在相关的表面与所述材料层之间布置有例如一个或一个以上的附加的层。
此外，在说明书或权利要求书中使用术语“具有”、“包含”、“含有”，“带有”或其变体，这些术语旨在以类似于术语“包括”的方式包括在内。也就是说，如本文所使用的，术语“具有”、“包含”、“含有”、“带有”、“包括”等是开放式术语，其表示所述的元件或特征的存在，但不排除还有附加元件或特征。冠词“一个”、“该”旨在包括复数和单数，除非上下文另有明确说明。
此外，词语“示例性”在本文中用于表示用作示例、实例或展示。本文“示例性”描述的任何方面或设计不一定理解为优于其他方面或设计。而是，使用词语“示例性”旨在以具体的方式呈现概念。如本申请中所使用的，术语“或”旨在表示包容性的“或”而不是排他性的“或”。也就是说，除非另有说明或者从上下文中显然可见，“X使用A或B”旨在表示任何自然包括的排列。也就是说，如果X使用A；X使用B；或者X使用A和B，则在任何前述情况下，“X使用A或B”都是满足的。此外，本申请和所附权利要求中使用的冠词“一个”通常可理解为表示“一个或一个以上”，除非另有说明或从上下文中显然可见地指向单数形式。此外，A和B中的至少一种等通常意味着A或B或者A和B两者。
本文描述了器件和用于制造器件的方法。与所描述的器件相关的解释对于相应的方法也可能是正确的，反之亦然。例如，如果描述了器件的特定部件，则用于制造器件的相应方法可包括以合适的方式提供所述部件的行为，即使这些行为未作明确描述或未在图中示出。此外，除非另有明确说明，否则本文所述的各种示例性方面的特征可彼此组合。
尽管已经就一个或一个以上的实施方式示出和描述了本公开，但至少部分地基于对本说明书和附图的阅读和理解，本领域技术人员将想到等同的改变和修改。本公开包括所有这些修改和改变，并且仅受所附权利要求的概念的限制。特别是关于由上述部件(例如元件、资源等)执行的各种功能，除非另有说明，用于描述这些部件的术语旨在对应于执行所述部件的特定功能的(例如，功能上等效的)即使结构上不等同于本公开的在本文所示的示例性实施方式中执行所述功能的所公开的结构的任何部件。此外，虽然本公开的特定特征可能仅针对多个实施方式中的一个而公开，但是，如可能对于任何给定的或特别的应用而言期望的或有利的那样，这样的特征可与其他实施方式的其他特征中的一个或一个以上组合。

Claims (20)

1.一种半导体装置，包括：
载体；
半导体芯片；和
芯片附接材料，其布置在载体与半导体芯片之间，其中，
芯片附接材料的填角高度小于半导体芯片的高度的大约95％，且
芯片附接材料在半导体芯片的朝着芯片附接材料的主表面的边缘之上的最大延伸尺度小于大约200微米。
2.根据权利要求1所述的半导体装置，其特征在于，芯片附接材料在半导体芯片的侧表面处形成填角，其中，填角高度是侧表面的被芯片附接材料所覆盖的部分的高度。
3.根据权利要求1或2所述的半导体装置，其特征在于，所述填角具有弯月面的形状。
4.根据前述权利要求中任一项所述的半导体装置，其特征在于，半导体芯片的高度小于大约400微米。
5.根据前述权利要求中任一项所述的半导体装置，其特征在于，芯片附接材料的平均粘合层厚度处于大约10微米至大约80微米范围内。
6.根据前述权利要求中任一项所述的半导体装置，其特征在于，半导体芯片或芯片附接材料的倾斜度小于大约15微米。
7.根据前述权利要求中任一项所述的半导体装置，其特征在于，芯片附接材料在半导体芯片的朝着芯片附接材料的主表面的边缘之上在该边缘的整个长度的大约50％以上延伸。
8.根据前述权利要求中任一项所述的半导体装置，其特征在于，芯片附接材料的热导率大于大约0.5W/(m·K)。
9.根据前述权利要求中任一项所述的半导体装置，其特征在于，芯片附接材料包括粘合膏、导电粘合膏、银导电粘合膏、焊接材料、焊膏、烧结膏中的至少一种。
10.根据前述权利要求中任一项所述的半导体装置，其特征在于，芯片附接材料包括导电和导热填充颗粒中的至少一种以及聚合材料。
11.根据权利要求10所述的半导体装置，其特征在于，填充颗粒包括银、铜、镍、金、铝、它们的混合物中的至少一种。
12.根据权利要求10或11所述的半导体装置，其特征在于，填充颗粒包括二氧化硅、氧化铝、矾土、氮化硼、碳化硅、氮化镓、它们的混合物中的至少一种。
13.根据前述权利要求中任一项所述的半导体装置，其特征在于，所述载体包括引线、芯片焊盘、引线框架、印刷电路板、陶瓷、镀有金属的陶瓷、衬底、功率电子衬底中的至少一种。
14.一种方法，包括：
提供载体；
将芯片附接材料沉积到载体上；和
将半导体芯片布置在芯片附接材料上，其中，半导体芯片的朝着芯片附接材料的主表面至少部分地接触芯片附接材料，其中，在将半导体芯片布置在芯片附接材料上后紧接着，芯片附接材料在所述主表面的边缘之上的第一最大延伸尺度小于大约100微米。
15.根据权利要求14所述的方法，其特征在于，该方法还包括：
在半导体芯片的侧表面处形成芯片附接材料的填角，其中，形成填角基于芯片附接材料沿着半导体芯片的侧表面的蠕变。
16.根据权利要求14或15所述的方法，其特征在于，芯片附接材料的蠕变基于芯片附接材料与半导体芯片之间的粘附力。
17.根据权利要求14-16中任一项所述的方法，其特征在于，该方法还包括：
在将半导体芯片布置在芯片附接材料上后，使芯片附接材料在主表面的边缘之上进一步延伸，其中，芯片附接材料在所述主表面的边缘之上的第二最大延伸尺度小于大约200微米。
18.根据权利要求14-17中任一项所述的方法，其特征在于，该方法还包括固化芯片附接材料，其中，固化时间处于大约10分钟至大约3小时的范围内，固化温度处于大约100摄氏度至大约300摄氏度的范围内。
19.一种方法，包括：
提供载体；
将芯片附接材料沉积到载体上；
将半导体芯片布置在芯片附接材料上；和
在半导体芯片的侧表面处形成芯片附接材料的填角，其中，形成填角唯一地基于芯片附接材料沿着半导体芯片的侧表面的蠕变。
20.根据权利要求19所述的方法，其特征在于，该方法还包括：
形成芯片附接材料在半导体芯片的朝着芯片附接材料的主表面的边缘之上延伸的部分，其中，芯片附接材料在所述主表面的边缘之上的最大延伸尺度小于大约200微米。
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