CN1615545A - 为减少晶粒的剪应力而控制晶粒固定用嵌角的方法与装置 - Google Patents

为减少晶粒的剪应力而控制晶粒固定用嵌角的方法与装置 Download PDF

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CN1615545A
CN1615545A CNA028272730A CN02827273A CN1615545A CN 1615545 A CN1615545 A CN 1615545A CN A028272730 A CNA028272730 A CN A028272730A CN 02827273 A CN02827273 A CN 02827273A CN 1615545 A CN1615545 A CN 1615545A
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R·A·纽曼
J·D·韦德勒
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Innovation Core Making Co ltd
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Abstract

本发明系藉由控制黏晶圆角(30)高度(Z)，以避免在一封装的半导体芯片中，造成破裂及脱层的方法与装置。具体地说，本发明藉由控制该黏晶材料(20)的高度，而控制该黏晶圆角(die attach fillet)(30)高度(Z)，进而减少在晶粒(5)本身的剪应力。本发明的优点包括，在不需对现存产品进行重新评估的情况下，可增加焊接导线可靠度及封装可靠度。藉由结合本发明的技术，并使用现行合格的封装材料及黏晶环氧树脂，可控制黏晶环氧树脂高度，进而控制黏晶圆角(30)高度(Z)，使该整体组装过程得以维持。所以，无论热效率或电效率都未因此而牺牲。

Description

为减少晶粒的剪应力而控制晶粒固定用嵌角的方法与装置
技术领域
本发明相关于半导体芯片的组装与封装，尤其相关于半导体芯片中的焊接导线晶粒的组装与封装，更确切地说，相关于在半导体芯片中减少晶粒的剪应力。
背景技术
目前，半导体工业需要更好的黏晶技术、更好的封装技术以及更好的焊接导线技术等以增进产品的可靠度。每一个晶粒一般都系使用一共晶材料层(eutectic material layer)而与半导体封装的黏晶区域相黏结，该共晶材料层可为金-硅(Au-Si)及银-硅(Ag-Si)共晶层或有机黏晶材料，例如，环氧树脂(epoxy)或聚亚醯胺(polyimide)。一般说来，一焊线的两端分别连结有一晶粒及一导线。一芯片通常系完善安置于该封装件内，且该晶粒黏结区域可提供该芯片电性耦接至该剩余的导线系统。针对该晶粒黏结区域，必须要求其为极度的平坦，方能使该芯片密切地保持在封装件之中。
关于晶粒的黏结，其基本的目标在于提供芯片及封装件间所可能的最佳黏结，并提供最佳的导电也或导热路径，或甚至提供材料间的最佳绝缘效果，端视该特定芯片的应用范围而定。由此可知，该晶粒的黏结应当十分紧致以避免在后续制程中或使用中造成脱层(delamination)。最广为使用的黏晶材料包括可导电及导热的填金(gold-filled)及填银(silver-filled)聚亚醯胺与环氧树脂。为达绝缘的目的，则可使用载氧化硅(silica-loaded)聚合物来当作黏晶材料。然而，不幸的是，由于黏晶材料既有的内应力，造成无论填充绝缘体也或填充导体的黏晶材料，在硬化之后都倾向脱层或破裂。此外，在温度循环期间，大部分的封装材料(molding compound)都倾向在晶粒周围弯曲，也导致破裂或已存在裂缝的扩张。
该相关的技艺试图藉由提供具有较低应力的封装材料以及具有较低应力的黏晶环氧树脂来解决上述的问题。然而，使用具有较低应力的封装材料必须要求重新评估许多既存的产品。这种产品的转换是非常困难及要求过高的。此外，使用具有较低应力的封装材料必须要求减少所加载的氧化硅(SiO2)粒子数，如此，便牺牲了导热效率。同样地，使用具有较低应力的黏晶环氧树脂必须要求减少所加载的金(Au)或银(Ag)粒子数，不只牺牲了导热效率，也牺牲了导电效率。
另一个相关技艺的作法系使用一具有非常低的圆角高度的环氧树脂，而仅在晶粒/封胶接口上，减低任何热引起的应力，其中，该封胶特别包含有一种覆顶式封装材料(glob-top material)，而该圆角高度大约在小于晶粒厚度的33.33％的范围(即对于一15密尔(mil)(381um)相当于厚的晶粒而言，该圆角高度小于5密尔(127um)。一般说来，一覆顶式封胶在晶粒/覆顶式封装材料的接口上，具有现有的内在弱点，因该覆顶式封胶系藉由一配置器根据周遭情形而将的配置在晶粒的上表面上。如此，该覆顶式封胶内将布满空隙，牺牲了黏性，并因此造成脱层的现象。然而，该项相关技艺的作法并未提到在较厚的晶粒中的破裂以及在晶粒上的金属电路及硅块体之间的破裂，所造成的圆角中剪应力的问题。同样地，这些相关技艺并未提到除了关联于该等覆顶式种类的相关封装材料。因此，必须发展一种控制晶粒黏着过程的方法与装置，以于许多不同的制程及使用条件下，避免半导体芯片封装的破裂或脱层。
发明内容
根据以上的讨论，本发明提供一种在半导体芯片封装中避免产生破裂及脱层现象的方法与装置，尤其在一种所谓的塑料(plastic)封装之中，例如，塑料扁平四方分支封装(plastic quad flat package，PQFP)，薄四方扁平封装(thin quad flat package，TQFP)，塑料无引线芯片载子封装(plastic leadless chip carrier，PLCC)，小型化集成电路封装(small outlineintegrated circuit，SOIC)，虽然较没问题，但仍然存在些许不想要的剪应力，以及任何其它的标准或非标准塑料封装。尤其是，一具有过模压封装材料(或封装材料)的球门阵列(BGA)封装也将于热循环、热冲击、或正常操作期间，经历破裂或脱层过程。
本发明系藉由控制黏晶圆角高度进而减少晶粒中的剪应力的方式以解决这些塑料封装的问题。例如用于球门阵列封装的该封装材料，可通过一转移模具(transfer mold)(例如，树脂转移成形法(resin transfermolding，RTM))中的闸，将的配置于其上。在以封装材料将模具填满之后，可在该封装材料上加热或加压使其得以硬化、加大密度并消除。当使用本方法以控制圆角高度时，这个技术可导致一无脱层的半导体封装，尤其对于BGA而言。
举例说明，本发明的经验数据对应于不同的圆角高度，其中该圆角高度系依据例如热循环及热冲击等不同的实验条件，等比于包装于BGA封装中的不同的晶粒厚度，其范围约在4密尔(101um)至30密尔(762um)之间。藉由使用范围约在大于33％至75％的晶粒厚度的圆角高度，本发明可避开(1)相关技艺中，封装的装置中各组件间的热膨胀系数(CTE)不相匹配的问题，其中，若该相关技艺中的圆角高度范围为小于晶粒厚度的33％，则有可能发生上述问题进而导致黏晶材料中的空隙及破裂，以及较差的导热性；以及(2)相关技艺中高剪应力所导致的失败问题，例如，在黏晶材料及晶粒本身上由剪应力所导致的破裂，其中，若该相关技艺中的圆角高度范围为大于晶粒厚度的75％，则有可能发生上述问题。令人惊讶的是，本发明的实验可靠度数据显示，一约为50％晶粒厚度的圆角高度在一较厚的硅晶粒中可导致最小的剪应力(例如，在约为8密尔至14密尔的范围中，最好在约为10密尔至14密尔的范围中)。更令人惊讶的是，一具有厚度范围小于8密尔的较薄晶粒，事实上产生了与半导体封装产业的共识背道而驰的相反结果。在本发明中，可使用例如ESEC 2007TM的黏晶取放装置。更确切的说，本发明提供一种方法及装置，藉由控制黏晶环氧树脂高度以控制黏晶圆角高度，并进而减少晶粒上的剪应力大小。
本发明的优点包括在于不需要重新评估现存产品的条件下增加焊接导线可靠度及封装可靠度。藉由结合本技术而使用现行合格的封装材料及黏晶环氧树脂，以控制黏晶环氧树脂高度，进而控制黏晶圆角高度，则得以维持整体的组装过程。因此，本发明也有不致于牺牲热效率及电效率的优点。此外，藉由规定应使用的黏晶材料的量以控制圆角的高度，可减少封装过程中黏晶材料的消耗。如此，本发明的方法与装置尤其可避免一BGA封装在热循环、热冲击及正常使用期间，在半导体芯片封装中造成破裂及脱层，使得该封装更为坚固。
附图说明
为了方便理解本发明，故于以下所附图标中分别赋予一参考标号。在以下的数个图标中，各参考数字分别代表本发明的相同或等同的部分。
第1图为依照本发明的一较佳实施例，显示晶粒系以一标准黏晶圆角在一晶粒黏着区域中，黏着于一半导体芯片封装的平面图。
第2图为第1图所显示的特点的剖面图，其中，依照本发明的一较佳实施例，进一步显示一黏晶材料形成有一具有大约50％晶粒高度的标准黏晶圆角。
第3图为第1图所显示的特点的侧视剖面图，其中，依照本发明的一较佳实施例，进一步显示一黏晶材料形成有一具有大约50％晶粒高度的标准黏晶圆角。
第4图为第1图所显示的特点的反向侧视剖面图，其中，依照本发明的一较佳实施例，进一步显示一黏晶材料形成有一具有大约50％晶粒高度的标准黏晶圆角。
第5图为依照相关技艺，显示晶粒系以一高/平整黏晶圆角在一晶粒黏着区域中，黏着于一半导体芯片封装的平面图。
第6图为第5图所显示的特点的剖面图，其中，依照相关技艺，进一步显示一黏晶材料形成有一具有大约90％晶粒高度的高/平整黏晶圆角。
第7图为第5图所显示的特点的侧视剖面图，其中，依照相关技艺，进一步显示一黏晶材料形成有一具有大约90％晶粒高度的高/平整黏晶圆角。
第8图为第5图所显示的特点的反向侧视剖面图，其中，依照相关技艺，进一步显示一黏晶材料形成有一具有大约90％晶粒高度的高/平整黏晶圆角。
第9图为依照相关技艺，显示晶粒系以一高/低黏晶圆角在一晶粒黏着区域中，黏着于一半导体芯片封装的平面图。
第10图为第9图所显示的特点的剖面图，其中，依照相关技艺，进一步显示一黏晶材料形成有一高/低黏晶圆角，于较高一侧的黏晶圆角具有约为90％晶粒厚度的高度，而较低一侧的黏晶圆角则具有约为25％晶粒厚度的高度。
第11图为第9图所显示的特点的侧视剖面图，其中，依照相关技艺，进一步显示一黏晶材料形成有一高/低黏晶圆角，于较高一侧的黏晶圆角具有约为90％晶粒厚度的高度，而较低一侧的黏晶圆角则具有约为25％晶粒厚度的高度。
第12图为第9图所显示的特点的反向侧视剖面图，其中，依照相关技艺，进一步显示一黏晶材料形成有一高/低黏晶圆角，于较高一侧的黏晶圆角具有约为90％晶粒厚度的高度，而较低一侧的黏晶圆角则具有约为25％晶粒厚度的高度。
第13图为依照本发明的晶粒系以一黏晶圆角在一晶粒黏着区域中黏着于一半导体芯片封装基底的部份剖面图，而该图标则显示黏晶圆角高度Z＝B-A及晶粒厚度B之间的临界尺度关系，其中，A＝未被圆角涵盖的晶粒厚度B的部份。
第14图为依照本发明的晶粒系以一黏晶圆角在一晶粒黏着区域中黏着于一BGA半导体芯片封装的部份剖面图，而该图标则显示黏晶圆角及晶粒之间的临界结构关系。
第15图为依照本发明的晶粒系以一黏晶圆角在一晶粒黏着区域中黏着于例如BGA封装的半导体芯片封装基底的部份剖面图，而该图标则显示黏晶圆角及晶粒之间的临界结构关系(也即，该圆角高度约为50％的晶粒厚度)，进一步在该晶粒上、在该圆角上、在该黏晶材料的一部份上及在该封装基底的一部份上，布设有封装材料。
第16图为依照本发明的晶粒具有一黏晶圆角的剖面图，而该图标则显示该较佳的结构关系(也即，于该晶粒的任一给定边约为中心50％的晶粒宽，圆角高度范围约为晶粒厚度的0％至75％)。
具体实施方式
在第5图至第12图中，说明了半导体封装相关技艺的问题特点，并在接下来，以第1图至第4图及第12图至第15图讨论本发明所解决的问题与相关技艺的问题间的关系。
依照本发明的一较佳实施例，第1图以一平面图说明一晶粒5系以一标准黏晶圆角(未图标)在一晶粒黏着区域中黏着于一半导体芯片封装基底10之上。
依照本发明的一较佳实施例，第2图以一剖面图说明如第1图所显示的特点，并进一步显示一以大约50％该晶粒5厚度的高度而形成一标准黏晶圆角30的黏晶材料20，其中，该标准黏晶圆角高度具有围绕该晶粒5周围近乎一致的高度分布。
依照本发明的一较佳实施例，第3图以一侧视剖面图说明如第1图所显示的特点，并进一步显示一以大约50％该晶粒5厚度的高度而形成一标准黏晶圆角30的黏晶材料20，其中，该标准黏晶圆角高度具有围绕该晶粒5周围近乎一致的高度分布。
依照本发明的一较佳实施例，第4图以一反向侧视剖面图说明如第1图所显示的特点，并进一步显示一以大约50％该晶粒5厚度的高度而形成一标准黏晶圆角30的黏晶材料20，其中，该标准黏晶圆角高度具有围绕该晶粒5周围近乎一致的高度分布。
依照相关技艺，第5图以一平面图说明一晶粒5系以一高/平整黏晶圆角(未图标)在一晶粒黏着区域中黏着于一半导体芯片封装基底10之上。
依照相关技艺，第6图以一剖面图说明如第5图所显示的特点，并进一步显示一以大约90％该晶粒5厚度的高度而形成一高/平整黏晶圆角30的黏晶材料20，其中，该高/平整黏晶圆角高度具有围绕该晶粒5周围近乎一致的高度分布。
依照相关技艺，第7图以一侧视剖面图说明如第5图所显示的特点，并进一步显示一以大约90％该晶粒5厚度的高度而形成一高/平整黏晶圆角30的黏晶材料20，其中，该高/平整黏晶圆角高度具有围绕该晶粒5周围近乎一致的高度分布。
依照相关技艺，第8图以一反向侧视剖面图说明如第5图所显示的特点，并进一步显示一以大约90％该晶粒5厚度的高度而形成一高/平整黏晶圆角30的黏晶材料20，其中，该高/平整黏晶圆角高度具有围绕该晶粒5周围近乎一致的高度分布。
依照相关技艺，第9图以一平面图说明一晶粒5系以一高/低黏晶圆角(未图标)在一晶粒黏着区域中黏着于一半导体芯片封装基底10之上。
依照相关技艺，第10图以一剖面图说明如第9图所显示的特点，并进一步显示在黏晶圆角30较高的一侧具有约为90％晶粒厚度的高度且在黏晶圆角30的较低的一侧具有约为25％晶粒厚度的高度，进而形成一高/低黏晶圆角30的黏晶材料20，其中，该高/低黏晶圆角高度具有围绕该晶粒5周围非均匀的高度分布。
依照相关技艺，第11图以一侧视剖面图说明如第9图所显示的特点，并进一步显示在黏晶圆角30较高的一侧具有约为90％晶粒厚度的高度且在黏晶圆角30的较低的一侧具有约为25％晶粒厚度的高度，进而形成一高/低黏晶圆角30的黏晶材料20，其中，该高/低黏晶圆角高度具有围绕该晶粒5周围非均匀的高度分布。
依照相关技艺，第12图以一反向侧视剖面图说明如第9图所显示的特点，并进一步显示在黏晶圆角30较高的一侧具有约为90％晶粒厚度的高度且在黏晶圆角30的较低的一侧具有约为25％晶粒厚度的高度，进而形成一高/低黏晶圆角30的黏晶材料20，其中，该高/低黏晶圆角高度具有围绕该晶粒5周围非均匀的高度分布。
依照本发明，第13图以一部份剖面图说明一晶粒5系以一黏晶圆角30在一晶粒黏着区域中黏着于一半导体芯片封装基底10之上，而该图标则显示黏晶圆角高度Z＝B-A及晶粒厚度B之间的临界尺度关系，其中，A＝未被圆角30涵盖的晶粒厚度B的部份。
依照本发明，第14图以一部份剖面图说明一晶粒5系在一例如BGA封装的半导体芯片封装基底10上，以一黏晶圆角30黏着于一晶粒黏着区域中，而该图标则显示黏晶圆角30及晶粒5之间的临界结构(也即，该圆角高度约为50％的晶粒厚度)关系。
依照本发明，第15图以一部份剖面图说明一晶粒5系在一例如BGA封装的半导体芯片封装基底10上，以一黏晶圆角30黏着于一晶粒黏着区域中，而该图标则显示黏晶圆角30及晶粒5之间的临界结构关系(也即，该圆角高度约为50％的晶粒厚度)，进一步在该晶粒5上、在该圆角30上、在该黏晶材料20的一部份上及在该封装基底10的一部份上，布设有封装材料60。
依照本发明的较佳实施例，第16图以一剖面图说明一具有一黏晶圆角30的晶粒5，而该图标则显示该临界结构关系(也即，沿着任何已知晶粒5的一边，约为中心50％的晶粒宽X，圆角高度Z＝B-A约在晶粒厚度Y＝B的0％至75％的范围之间)。基本上，Z-(0％至75％)Y-(0％至75％)B作为一大约($)25％X的位置(也即，于该晶粒5的任何给定侧各边6向内至少25％)的限制条件。最好的情况则是以Z-(＞33％至75％)Y-(＞33％至75％)B作为一大约($)25％X的位置(也即，于该晶粒5的任何给定侧各边6向内至少25％)的限制条件。对于该较佳实施例而言，这样的限制条件对于在封装装置中减少整体剪应力方面具有惊人的效果。在组装过程中，在一外侧区域(也即，小于25％X)控制该圆角高度是非常困难的。因此，本方法将圆角高度局限于内侧区域(也即，于该晶粒5的任何给定侧各边6向内至少25％)，否则，由剪应力所造成的可能伤害则为最大者。若这么作的话，则可大量减少封装装置中的剪应力。
本发明的在一封装的半导体芯片中减少剪应力的方法，一般包括以下步骤：提供一半导体芯片封装基底10，其中布设有一半导体芯片并具有一晶粒黏着区域；提供一具有厚度Y、宽度X及至少一侧边的晶粒5；提供一黏晶材料20；控制该黏晶材料20布设于该晶粒5及该半导体芯片封装基底10之间的量，其中，至少一部份的黏晶材料20在晶粒5的至少一边形成至少一弯月面，其中，该至少一弯月面透过对该黏晶材料20的硬化而形成至少一黏晶圆角30，进而控制该至少一黏晶圆角30的至少一高度Z＝B-A，并减少晶粒5中的剪应力；然后完成该半导体芯片的封装。
本发明的减少剪应力的已封装半导体芯片，一般包括：一半导体芯片封装基底10，其中布设有一半导体芯片及一晶粒黏着区域；一晶粒5，具有至少一侧边；一黏晶材料20，其份量受到控制并布设于该晶粒5及该半导体芯片封装基底10之间；至少一部份的黏晶材料20在该晶粒5的至少一边形成至少一弯月面该至少一弯月面透过该黏晶材料20的硬化以形成至少一黏晶圆角30，该至少一黏晶圆角30具有至少一受控制的高度Z＝B-A，而该晶粒5具有较少的剪应力。
在本发明的为减少封装半导体芯片中的剪应力的方法与装置中，该晶粒5可包括硅，且该晶粒5的厚度可以在大约4密尔至30密尔的范围之间，而最好是在大约10密尔至14密尔的范围之间，主要是因为对于稍微较厚的晶粒具有令人讶异的较佳破裂阻抗。藉由切割步骤，一晶粒5最好具有较少的预存的内应力，且最好具有大约367密尔平方的平面面积。该黏晶材料20可包括一环氧树脂，也可包括一从导体及绝缘体群组中所选出的填充剂。
该黏晶圆角高度(也即，圆角百分比)系藉由以下的简单关系式计算出来的，圆角％＝100(B-A)/B，其中，B＝晶粒厚度，A＝未被涂上黏晶材料的晶粒一边的垂直距离。该黏晶圆角30也得包括一标准高度Z，其范围约在该晶粒厚度Y＝B的40％至60％之间(一般约为50％)。藉由刻意地将该黏晶圆角局限在该晶粒厚度的大约50％，本发明也可减低晶粒中的剪应力，进而减低该封装的半导体芯片的整体应力。该较佳实施例(也即，大于晶粒厚度的大约33％至75％)已与于先前第16图中加以讨论。
本说明书中所详细展示及描述的信息完全可以达到本发明上述的目的，此外，在此所展示的本发明的较佳实施例也可代表藉由本发明在广泛思考后所能达到的课题范围。本发明的范围完全涵盖该些熟悉本技术领域者所显而易见的实施例，并且，并非据此而局限所附的申请专利范围，其中，除非特别指明，否则，若以单数指称一组件时，则并非意味着一个且仅有一个，而是指一个或多个。在本技术领域内具有一般技艺者所熟知的上述较佳实施例及其它实施例中，所有与其中的组件具有相同或等同的结构及功能者，均以参考描述的方式纳入并视为涵盖于本发明的申请专利范围中。
此外，本发明所欲解决的每一个问题，对于一装置或方法而言，并不存在任何必备条件，才能将的涵盖于本申请专利范围中。另外，本发明所揭露的组件、部件、或方法步骤，均并非意图开放作公众用途，无论该组件、部件、或方法步骤是否明确地列举于该申请专利范围中。然而，对于那些在本技术领域中具有一般技艺者而言，可藉由附录于本发明的申请专利范围中的内容，轻易地在形式上、在半导体材料上及在制造材料细节上进行不同的变更及修改而不违背本发明的精神与范畴。
本发明在产业上可运用于半导体芯片的组装及封装。更确切地说，本发明在产业上可运用于在半导体芯片中焊接导线晶粒。又更确切地说，本发明可藉由提供一方法及一装置以减低半导体芯片中的剪应力，而在产业上运用于半导体芯片封装之中以避免造成破裂及脱层的现象。本发明可藉由控制黏晶圆角高度，进而减少晶粒自身的剪应力，而在产业上运用于解决塑料封装的问题。

Claims (10)

1.一种减少剪应力的封装半导体芯片，其特征包括：
一半导体芯片封装基底(10)，其中布设有一半导体芯片并具有一黏晶区域；
一晶粒(5)，具有至少一侧边，该晶粒(5)包括有选自硅(Si)、锗(Ge)及砷化镓(GaAs)所构成群组的半导体材料，且每一该至少一侧边具有一厚度(Y)及一宽度(X)；
以及一份量受控制的黏晶材料(20)，其布设于该晶粒(5)及该半导体芯片封装基底(10)之间；
至少一部份的该黏晶材料(20)形成至少一半弯月面于该晶粒(5)的至少一侧边上，
该至少一弯月面于该黏晶材料的硬化过程中形成至少一黏晶圆角(30)，
该至少一黏晶圆角具有至少一控制高度，且该晶粒具有较少的剪应力。
2.如权利要求1所述的封装半导体芯片，其特征在于，该晶粒(5)系由一厚度(Y)所构成，其范围约在4密尔(101um)至30密尔(762)之间。
3.如权利要求1所述的封装半导体芯片，其特征在于，该黏晶材料(20)系由一环氧树脂所构成。
4.如权利要求1所述的封装半导体芯片，其特征在于，该至少一黏晶圆角(30)包含一标准高度(Z)，其范围约在该晶粒厚度(Y)的0％至75％之间。
5.如权利要求4所述的封装半导体芯片，其特征在于，该半导体芯片封装基底(10)包含一球门阵列(BGA)。
6.如权利要求1所述的封装半导体芯片，其特征在于，该至少一黏晶圆角(30)包含一标准高度(Z)，其范围约在大于该晶粒厚度(Y)的33％至75％之间。
7.如权利要求6所述的封装半导体芯片，其特征在于，该标准高度(Z)是沿着该晶粒宽度(X)的中心约50％的位置而局限于约大于该晶粒厚度(Y)的33％至75％的范围之间。
8.如权利要求1所述的封装半导体芯片，其特征进一步在于，一封装材料可布设置于该晶粒(5)、该圆角(30)、该至少一部份的黏晶材料及该至少一部份的封装基底(10)上。
9.如权利要求8所述的封装半导体芯片，其特征在于，该半导体芯片封装基底(10)系包含一球门阵列(BGA)。
10.如权利要求1所述的封装半导体芯片，其特征在于，该半导体芯片封装基底(10)包含一球门阵列(BGA)。
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