US20070096342A1 - Method for reducing or eliminating semiconductor device wire sweep in a multi-tier bonding device and a device produced by the method - Google Patents

Method for reducing or eliminating semiconductor device wire sweep in a multi-tier bonding device and a device produced by the method Download PDF

Info

Publication number
US20070096342A1
US20070096342A1 US11/561,577 US56157706A US2007096342A1 US 20070096342 A1 US20070096342 A1 US 20070096342A1 US 56157706 A US56157706 A US 56157706A US 2007096342 A1 US2007096342 A1 US 2007096342A1
Authority
US
United States
Prior art keywords
semiconductor device
insulative material
insulative
conductors
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/561,577
Inventor
Rakesh Batish
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/686,892 external-priority patent/US6847122B1/en
Priority claimed from US10/686,974 external-priority patent/US6955949B2/en
Application filed by Individual filed Critical Individual
Priority to US11/561,577 priority Critical patent/US20070096342A1/en
Publication of US20070096342A1 publication Critical patent/US20070096342A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H01L23/295—Organic, e.g. plastic containing a filler
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49558—Insulating layers on lead frames, e.g. bridging members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/4556—Disposition, e.g. coating on a part of the core
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H01L2224/49176—Wire connectors having the same loop shape and height
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01077—Iridium [Ir]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/386—Wire effects
    • H01L2924/3862—Sweep

Definitions

  • This invention relates to packaging semiconductor devices, and more particularly to a method of reducing or eliminating wire sweep and sway in packaged semiconductor devices.
  • FIG. 1 illustrates a portion of conventional semiconductor device 100 .
  • Semiconductor device 100 includes leadframe 102 and leadframe contact(s) 102 a.
  • Semiconductor element (e.g., die) 104 is mounted on leadframe 102 .
  • Bonding wire 106 provides interconnection between semiconductor element 104 and leadframe contact 102 a.
  • Overmold 108 i.e., a mold compound
  • bonding wire 106 may be included in semiconductor device 100 to provide interconnection between various connection points on semiconductor element 104 and corresponding leadframe contacts 102 a.
  • short circuits between adjacent bonding wires 106 , or open circuits in connection with one or more bonding wires 106 may occur.
  • movement e.g., sway, sweep, etc.
  • bonding wires 106 may result in a short circuit between adjacent bonding wires 106 .
  • movement of bonding wires may cause one or more bonding wires 106 to break, thus, causing an open circuit.
  • FIG. 2 illustrates a conventional semiconductor device 200 including an encapsulant 210 over bonding wire 106 .
  • Encapsulant 210 also covers the connection points between bonding wire 106 and each of semiconductor element 104 and leadframe contact 102 a.
  • the elements illustrated in FIG. 2 are very similar to those illustrated and described above with respect to FIG. 1 .
  • FIG. 3 is a perspective view of a conventional semiconductor device 100 , similar to the device illustrated in FIG. 1 .
  • Semiconductor element 104 is illustrated mounted on leadframe 102 .
  • a plurality of bonding wires 106 provide interconnection between semiconductor element 104 and corresponding leadframe contacts 102 a.
  • Overmold 108 (partially cut away in FIG. 3 ) is provided over semiconductor element 104 and bonding wires 106 .
  • FIG. 4 is a cut away side view of a conventional semiconductor device 400 .
  • semiconductor element 104 is mounted on leadframe 102 , and bonding wires 106 provide interconnection between semiconductor element 104 and leadframe contacts 102 a.
  • Encapsulant 410 is provided over semiconductor element 104 , and bonding wires 106 .
  • Overmold 108 is provided above and below semiconductor element 104 in the illustration of FIG. 4 .
  • bonding wires 106 may be become loose (i.e., open circuit) at one of the connection points (i.e., at semiconductor element 104 or leadframe contact 102 a ). Further, adjacent bonding wires 106 may move (e.g., sway) towards each other, thereby creating short circuits in the semiconductor device.
  • These issues are particularly problematic in view of the desire to decrease the size of semiconductor devices (and the corresponding desire to increase conductor density in semiconductor devices).
  • a method of packaging a multi-tier wire bonded semiconductor device includes applying an insulative material across only a portion of at least two of a plurality of conductors per layer providing interconnection between elements in the multi-tier wire bonded semiconductor device.
  • an encapsulant is applied to the conductors and elements, thereby packaging the semiconductor device.
  • the insulative compound comprises spherical silica particles to maintain a predetermined separation between adjacent ones of the plural conductors.
  • the insulative compound is applied in a substantially circumferential manner about the at least one the semiconductor element.
  • the insulative compound is applied in at least two geometric shape structures, each of the geometric shape structures substantially surrounding the at least one the semiconductor element in a circumferential manner.
  • the insulative material is applied in at least two distinct structures around a peripheral portion of the at least one the semiconductor element, the two structures not being in contact with one another.
  • a semiconductor device comprises a plurality of semiconductor elements; a plurality of conductors arranged in a multiple tier configuration providing interconnection between the plurality of semiconductor elements; and an insulative material applied across only a portion of at least two of the plurality of conductors in at least two tiers of the multiple tiers.
  • FIG. 1 is a cut away side view of an interconnection between semiconductor elements in a prior art semiconductor device
  • FIG. 2 is a cut away side view of an encapsulated interconnection between semiconductor elements in a prior art semiconductor device
  • FIG. 3 is a perspective view of a plurality of interconnections between semiconductor elements in a prior art semiconductor device
  • FIG. 4 is a cut away side view of an encapsulated interconnection between semiconductor elements in a prior art semiconductor device
  • FIG. 5 is a cut away side view of an interconnection between semiconductor elements in a semiconductor device in accordance with an exemplary embodiment of the present invention
  • FIG. 6 is a cut away side view of an interconnection between semiconductor elements in a semiconductor device in accordance with another exemplary embodiment of the present invention.
  • FIG. 7 is a perspective view of an interconnection between semiconductor elements in a semiconductor device in accordance with an exemplary embodiment of the present invention.
  • FIG. 8 is a perspective view of an interconnection between semiconductor elements in a semiconductor device in accordance with another exemplary embodiment of the present invention.
  • FIG. 9 is a cut away view of conductors separated by an insulative material in accordance with an exemplary embodiment of the present invention.
  • FIG. 10 is a chart illustrating a silica particle size distribution in an insulative material in accordance with an exemplary embodiment of the present invention.
  • FIG. 11 is another chart illustrating a silica particle size distribution in an insulative material in accordance with an exemplary embodiment of the present invention.
  • FIG. 12 is a flow diagram illustrating a method of packaging a semiconductor device in accordance with an exemplary embodiment of the present invention.
  • FIG. 13A is a cut away side view of an interconnection between semiconductor elements in a multi-tier wire bonded semiconductor device in accordance with an exemplary embodiment of the present invention
  • FIG. 13B is a top plan view of the device illustrated in FIG. 13A ;
  • FIG. 14A is a cut away side view of an interconnection between semiconductor elements in a multi-tier wire bonded semiconductor device in accordance with another exemplary embodiment of the present invention.
  • FIG. 14B is a top plan view of the device illustrated in FIG. 14A .
  • the term semiconductor device relates to a broad category of devices including packaged semiconductor devices such as integrated circuits, memory devices, DSPs (i.e., digital signal processors), QFP (i.e., quad-flat package), PBGA (i.e., plastic ball grid array), BOC (board on chip), COB (i.e., chip on board), CABGA (chip array ball grid array), and discrete devices (i.e., non-packaged devices, may be more than one device on one board).
  • the term semiconductor element refers to any portion of a semiconductor device, including substrates, dies, chips, leadframes, leadframe contacts, etc.
  • the present invention relates to placing a insulative material (e.g., in the form of a polymer bead, strip, or preformed shape) across bonding conductors (i.e., bonding wires) that provide interconnection between various semiconductor elements in a semiconductor device.
  • a insulative material e.g., in the form of a polymer bead, strip, or preformed shape
  • bonding conductors i.e., bonding wires
  • the insulative material e.g., a polymer bridge
  • creates a lattice i.e., a lattice bridge
  • structure which will provide additional stability to the conductors such that the conductors are separated (i.e., not short-circuited) during further processing (e.g., during transfer molding).
  • the insulative material may distribute, through fluid forces, throughout the interconnected conductor network during molding of the semiconductor device. This separation and force transfer reduces wire sweep and sway, and reduces or eliminates short circuiting resulting from an overmolding process.
  • the resin is cured using at least one of heat or ultraviolet energy.
  • An overmold may then be applied to provide a packaged semiconductor device without the wires moving or “sweeping” toward one another.
  • the methods and devices disclosed herein are particularly suited to the assembly of bonding wired semiconductor devices fabricated by contract and integrated device manufacturers. Certain embodiments of the present invention are particularly useful in relation to semiconductor devices having long conductors/bonding wires, or having complex bonding wired geometries (e.g., QFPs, stacked die devices, and BGAs).
  • various embodiments of the present invention utilize very little insulative material (e.g., a polymer material) in ring, rectangular, and/or any suitable configurations around or about a semiconductor element included in the semiconductor device.
  • insulative material e.g., a polymer material
  • certain embodiments of the present invention provide additional advantages over prior art fabrication techniques, including: additional flexibility in the fabrication process, minimization of expensive polymer used for stabilizing the conductors, and universal semiconductor device application.
  • Exemplary embodiments of the present invention reduce sweep on complex semiconductor device types (e.g., stacked die devices), and allow for extended conductor lengths in, for example, QFPs and BGAs.
  • FIG. 5 illustrates a cut away side view of semiconductor device 500 in accordance with an exemplary embodiment of the present invention.
  • Semiconductor device 500 includes semiconductor element 504 (e.g., a die) mounted on leadframe 502 .
  • semiconductor element 504 may be mounted to leadframe 502 using an adhesive.
  • Bonding wires 506 provide interconnection between semiconductor element 504 and leadframe contacts 502 a.
  • insulative material 512 is applied to a portion of bonding wires 506 .
  • insulative material 512 may be applied in a rectangular, ring, and/or any suitable shape around or about semiconductor element 504 .
  • insulative material 512 may be positioned closer to semiconductor element 504 (as opposed to leadframe contacts 502 a ), because bonding wires 506 have a closer pitch (i.e., are closer to adjacent bonding wires 506 ) at semiconductor element 504 than at leadframe contacts 502 a.
  • insulative material 512 may be positioned midway between semiconductor element 504 and leadframe contacts 502 a. Further still, insulative material 512 may be positioned at any of a number of locations between semiconductor element 504 and leadframe contacts 502 a, as desired in a given device.
  • Insulative material 512 may be, for example, a polymer material such as an epoxy resin. Additionally, insulative material 512 may include insulative particles or beads that distribute between bonding wires 506 during application of insulative material 512 to bonding wires 506 . Such insulative beads further stabilize bonding wires 506 with respect to one another. According to an exemplary embodiment of the present invention, the insulative beads distributed in the insulative material have a mean particle size of approximately 4.1 ⁇ m, a median particle size of 4.5 ⁇ m, and a maximum particle size of 20 ⁇ m. These insulative beads may be, for example, spherical silica particles.
  • FIG. 6 is a cut away side view of semiconductor device 600 , where semiconductor device 600 is similar to the semiconductor device 500 illustrated in FIG. 5 .
  • FIG. 6 illustrates insulative material 512 provided across a portion of bonding wires 506 .
  • FIG. 6 also illustrates insulative material 514 provided across another portion of bonding wires 506 .
  • Insulative material 514 may be provided in a similar configuration to insulative material 512 (e.g., in a rectangular, ring, and/or any suitable shape around or about semiconductor element 504 ).
  • insulative material 514 may be a polymer material such as an epoxy resin, and may include insulative beads as described above with respect to FIG. 5 .
  • FIG. 7 illustrates a semiconductor device 700 including semiconductor element 704 mounted on leadframe 702 .
  • Bonding wires 706 provide interconnection between semiconductor element 704 and leadframe contacts 702 a.
  • Insulative material 712 is provided across a portion of bonding wires 706 to stabilize bonding wires 706 with respect to one another.
  • insulative material 712 is provided in a substantially ring shape (and/or any suitable shape) around or about semiconductor element 704 . By providing insulative material 712 across a portion of bonding wires 706 , open or short circuiting of bonding wires 706 may be substantially reduced prior to and during application of overmold 708 .
  • FIG. 8 is a perspective view of semiconductor device 800 similar to the device illustrated in FIG. 7 .
  • FIG. 8 illustrates insulative material 814 provided across a portion of bonding wires 706 .
  • bonding wires 706 are further stabilized with respect to one another.
  • FIG. 7 illustrates semiconductor device 700 including single insulative material ring 712
  • FIG. 8 illustrates semiconductor device 800 including insulative material ring 712 and insulative material ring 814
  • additional rings or other shaped portions of an insulative material may be provided.
  • one, two, three, or any of a number of rings/beads of insulative material may be applied to a given semiconductor device, as desired.
  • FIG. 9 is a cut away view of bonding wires 906 a, 906 b, and 906 c.
  • bonding wires 906 a, 906 b, and 906 c provide interconnection between a semiconductor element (not shown in FIG. 9 ) and leadframe contacts (not shown in FIG. 9 ) in a semiconductor device.
  • Insulative material 912 is provided across a portion of bonding wires 906 a, 906 b, and 906 c.
  • insulative material 912 includes insulative beads.
  • the insulative beads may be of a variety of different sizes, and because the insulative beads are smaller than the distance between adjacent bonding wires (e.g., between bonding wire 906 a and 906 b ), the insulative beads disperse into a position between adjacent bonding wires, thereby providing enhanced stability and insulation between adjacent bonding wires.
  • FIG. 9 illustrates a distance “d 1 ” representing a center-to-center distance (i.e., pitch) between bonding wires 906 a and 906 b. Further, FIG. 9 illustrates a distance “d 2 ” representing a spacing between bonding wires 906 a and 906 b.
  • the insulative material may be applied to ultrafine pitch bonding wired semiconductor devices. For example, distance d 1 in such a device may be approximately 35 ⁇ m or less, and distance d 2 in such a device may be approximately 15 ⁇ m or less.
  • the improved bonding wire stability of the present invention may be applied to ultrafine pitch bonding wired semiconductor devices with small values for distances d 1 and d 2 .
  • conductor density within a semiconductor device may be increased, desirably resulting in a semiconductor device of decreased size.
  • an additional benefit of fabricating semiconductor devices according to the present invention is that because of the inclusion of the insulative material across a portion of the bonding wires, the overmold/encapsulation material used to encapsulate the device may be constructed of a less expensive material and process (e.g., mold type encapsulation as opposed to “glob-topping”) because the encapsulant does not necessarily need to stabilize the bonding wires.
  • the beads included in the insulative material utilized according to various exemplary embodiments of the present invention may be any of a number of types of insulative beads.
  • the beads may be constructed of a silica filler.
  • the insulative beads may be of varying types having varying sizes and shapes.
  • the insulative material of the present invention may include a high viscosity, ultraviolet curable silica.
  • the insulative material may be filled with silica at a weight percentage between 50-85%.
  • FIG. 10 is a bar chart illustrating an exemplary particle size (i.e., particle size diameter) distribution of two distinct silica fillers (e.g., SiO 2 ) used in an insulative material according to an exemplary embodiment of the present invention.
  • the silica 2 particle size beads range from approximately 0.05 microns to approximately 0.5 microns.
  • the distribution of silica 1 particle size beads ranges from approximately 0.5 microns to approximately 20 microns.
  • the y-axis of the bar chart of FIG. 10 illustrates the percentage of each size of each of the silica 1 and silica 2 particles.
  • the silica fillers charted in FIG. 10 have proven to be particularly useful when dispersed within insulative materials (e.g., epoxy resin) according to certain exemplary embodiments of the present invention.
  • the individual distribution of the silica diameter sizes for the type of spherical silica designated silica 1 is: 0% are greater than 24 microns, 1.1% are less than 24 microns and greater than 16 microns, 4.0% are less than 16 microns and greater than 12 microns, 11.5% are less than 12 microns and greater than 8 microns, 12.8% are less than 8 microns and greater than 6 microns, 35.8% are less than 6 microns and greater than 3 microns, 13.3% are less than 3 microns and greater than 2 microns, 12.5% are less than 2 microns and greater than 1 microns, 7.0% are less than 1 microns and greater than 0.5 microns, and 2.0% are less than 0.5 microns and greater than 0 microns.
  • the individual distribution of the silica diameter sizes for the type of spherical silica designated silica 2 is: 0% are greater than 0.6 microns, 0.5% are less than 0.6 microns and greater than 0.5 microns, 7.03% are less than 0.5 microns and greater than 0.45 microns, 9.13% are less than 0.45 microns and greater than 0.4 microns, 12.83% are less than 0.4 microns and greater than 0.35 microns, 13.43% are less than 0.35 microns and greater than 0.3 microns, 13.33% are less than 0.3 microns and greater than 0.25 microns, 9.33% are less than 0.25 microns and greater than 0.2 microns, 5.83% are less than 0.2 microns and greater than 0.15 microns, 4.33% are less than 0.15 microns and greater than 0.1 microns, 5.83% are less than 0.1 microns and greater than 0.09 microns, 5.93% are less than 0.09 microns and greater than 0.
  • insulative material is applied across a plurality of bonding wire layers in a multi-tier wire bonded semiconductor device.
  • the insulative material may be applied across the multiple bonding wire layers in addition to application of the insulative material across adjacent conductors as described above.
  • FIG. 13A illustrates a cut away side view of semiconductor device 1300 in accordance with an exemplary embodiment of the present invention
  • FIG. 13B is a top view thereof.
  • Semiconductor device 1300 includes semiconductor element 1304 (e.g., a die) mounted on leadframe 1302 .
  • semiconductor element 1304 may be mounted to leadframe 1302 using an adhesive.
  • Bonding wires 1306 provide interconnection between semiconductor element 1304 and another portion of semiconductor device 1300 , for example, leadframe contacts not illustrated in FIG. 13A .
  • insulative material 1312 is applied to a portion of bonding wires 1306 .
  • insulative material 1312 may be applied in a rectangular, ring, and/or any suitable shape around or about semiconductor element 1304 . As provided above, insulative material 1312 may be positioned at any of a number of locations between semiconductor element 1304 and the other connection point of bonding wires 1306 , as desired in a given device.
  • insulative material 1312 may be positioned at any of number of locations between semiconductor element 1304 and the other connection point of bonding wires 1306 , as desired in a given device.
  • insulative material 1312 may be disposed at any of number of locations and any number of times between semiconductor element 1304 and the other connection point of bonding wires 1306 , as desired in a given device. It is also contemplated that insulative material may or may not contact semiconductor element 1304 and/or lead frame 1302 , as illustrated in FIG. 14A .
  • bonding wires 1306 are provided in layers or tiers (i.e., device 1300 is a multi-tier wire bonded semiconductor device). Insulative material 1312 is provided across each of the bonding wire layers, thereby reducing or substantially eliminating short circuiting due to wire sweep and other associated problems as described herein. Of course, insulative material 1312 is not necessarily provided across each of the bonding wire layers. For example, in certain configurations with four layers of bonding wires (as illustrated in FIG. 13A ), insulative material 1312 may be provided across 2, 3, or all 4 layers, as desired in the specific application.
  • the position of each layer of the bonding wires 1306 with respect to one another is stabilized.
  • the risk of short circuiting adjacent layers of bonding wires 1306 e.g., during application of an overmold
  • the risk of short circuiting adjacent layers of bonding wires 1306 is substantially reduced if not eliminated.
  • the position of the layers of bonding wires 1306 open circuiting of bonding wires 1306 during fabrication may also be substantially reduced.
  • insulative material 1312 may be, for example, a polymer material such as an epoxy resin. Additionally, insulative material 1312 may include insulative particles or beads that distribute between layers of bonding wires 1306 during application of insulative material 1306 . Such insulative beads further stabilize layers of bonding wires 1306 with respect to one another. These insulative beads may be, for example, spherical silica particles.
  • insulative beads e.g., silica particles
  • the silica 1 distribution of particles may be mixed with the silica 2 distribution of particles.
  • 10 parts of the silica 1 distribution of particles is mixed with 3 parts of the type silica 2 distribution of particles.
  • a bar chart illustrating the SiO 2 particle size distribution of such a mixture is provided in FIG. 11 .
  • the individual distribution of the silica diameter sizes for the mixture of spherical silica illustrated in FIG. 11 is: 0% are greater than 24 microns, 0.85% are less than 24 microns and greater than 16 microns, 3.08% are less than 16 microns and greater than 12 microns, 8.85% are less than 12 microns and greater than 8 microns, 9.85% are less than 8 microns and greater than 6 microns, 27.54% are less than 6 microns and greater than 3 microns, 10.23% are less than 3 microns and greater than 2 microns, 9.62% are less than 2 microns and greater than 1 microns, 5.5% are less than 1 microns and greater than 0.6 microns, 3.16% are less than 0.6 microns and greater than 0.5 microns, 2.11% are less than 0.5 microns and greater than 0.45 microns, 2.96% are less than 0.45 microns and greater than 0.4 microns, 3.1% are less than 0.4 microns and greater than 0.
  • an insulative material according to the present invention is particularly useful in protecting bonding wires in semiconductor packages from wire sweep during fabrication (e.g., during the overmolding process after application of the insulative material), where the length to diameter ratio of the longest bonding wires is greater than 250.
  • the process includes dispensing the insulative material (e.g., while the semiconductor device is still on the wirebonding machine), and thereafter a period of time is provided for the material to flow.
  • the flow time can be, for example, from two to 50 seconds (and more specifically between 7 and 25 seconds) depending on several conditions such as size of the semiconductor device, temperature of the semiconductor device, temperature of the insulative material during dispensing, and the density of the conductors providing interconnection between the elements. Thereafter, the insulative material is cured using some combination of heat, UV radiation, visible radiation, and IR radiation.
  • the application of the insulative material including insulative particles of specific sizes and quantities is particularly useful in improving the ability of the insulative material to flow between and separate, short-circuited bonding wire pairs.
  • small diameter inorganic particles may be used to fill in between the bonding wires.
  • the type of insulative material e.g., polymer resin
  • the scale of the insulative particles is explicitly smaller than the desired gaps between adjacent bonding wires, and is added in specific sizes and quantities to improve the flow of the insulative material.
  • the insulative material/encapsulant may be rapidly cured through exposure to a UV source of radiation, or to a combination of UV radiation, visible radiation, and infrared radiation. The methods disclosed herein are particularly useful when the insulative material is applied immediately or shortly after wirebonding, and when the bonding wire lengths are at least 250 times larger than the bonding wire diameter.
  • the present invention may provide packaged semiconductor devices with longer, thinner, bonding wires, and with a higher density of I/O connections, at smaller pad pitch.
  • the yield of the semiconductor devices is also increased, particularly with respect to post-bond substrate handling, overmolding, and globtop encapsulation.
  • the yield of the semiconductor devices is increased by preventing shorts of fine pitch, small diameter wirebonded semiconductor devices through the application of the insulative material including a combination of small and intermediate size insulative particles (e.g., spherical silica particles) to the device for dispersion and distribution between adjacent bonding wires, and subsequently curing/gelling the insulative material (e.g., on the wirebonder) using heat, exposure to radiation (ultraviolet, visible, and/or infrared), and/or through a thermal batch process.
  • the insulative material including the combination of small and intermediate size spherical silica, is applied using an automatic dispensing machine as soon as is practical after wirebonding.
  • the curing and/or gelling of the insulative material may vary depending upon the embodiment of the present invention utilized.
  • the insulative material may be cured/gelled directly on the wirebonder using heat and exposure to ultraviolet radiation.
  • the insulative material may be cured/gelled on the wirebonder by heat and exposure to one of more of ultraviolet, visible, and infrared radiation.
  • the insulative material may be cured/gelled using a thermal batch process.
  • the insulative material may be an epoxy encapsulant material including substantially spherical silica particles that are, at least partially, smaller than the desired space between adjacent bonding wires in an ultrafine pitch wirebonded semiconductor device.
  • the encapsulant material may be designed such that a specific intensity, duration, and wavelength distribution of ultraviolet radiation, visible radiation, and/or infrared radiation, rapidly gels or at least partially cures the encapsulant material.
  • the characteristics of the insulative material, and the application process parameters thereof may be designed such that as the insulative material is dispensed onto the wirebonded semiconductor device, it covers the entire bonding wire(s), or a portion of the bonding wire(s).
  • the insulative material may be applied in any of a number of directions.
  • the insulative material may be applied from a leadframe contact towards an inner semiconductor element of the semiconductor device (e.g., a die).
  • the insulative material may be applied from an inner semiconductor element of the semiconductor device (e.g., a die) towards a leadframe contact of the semiconductor device.
  • Yet another alternative would be to apply the insulative material from directly above (or below) the bonding wires themselves.
  • the semiconductor device Before application of the insulative material, the semiconductor device is preferably heated, for example, to a temperature between 50° C. and 125° C., and more specifically to a temperature between 80° C. and 100° C. Further, the insulative material dispenser is also preferably heated, for example, to a temperature between 35° C. and 85° C., and more specifically to a temperature between 50° C. and 70° C. By heating the insulative material in the insulative material dispenser, it is easier to dispense the insulative material.
  • the insulative material preferably includes a filler material including insulative particles.
  • the filler material may be assembled from combinations of silica with size distributions determined based on various criteria.
  • the size distribution may be based on the following objectives: (1) to carry small silica particles into the narrow space between adjacent bonding wires, thereby driving the bonding wires apart; (2) to force the silica (e.g., by a capillary force) to provide a relatively high level of electrical isolation between adjacent bonding wires; (3) to fix the silica and the remainder of the insulative material (e.g., polymer) in place to stabilize the bonding wires, thereby sustaining the electrically insulative capabilities of the insulative material; (4) to minimally interfere with the fragile wire loops during the application of the insulative material; (5) to increase the packing density of the silica particles to achieve a low CTE; and (6) to provide smooth flowing capabilities of the insulative material.
  • the process of applying the insulative material may include dispensing of the insulative material, and curing the insulative material while the semiconductor device is on the wirebonding machine, such that the delicate loops of the thin bonding wire are stabilized and preserved immediately after (or shortly thereafter) the wirebonding process is complete.
  • the dispensing of the insulative material may occur while successive semiconductor devices are being wirebonded, such that a relatively quick and efficient fabrication process may be accomplished.
  • a first semiconductor device is receiving the insulative material from the insulating material dispenser (and subsequently being cured/gelled)
  • a second semiconductor device is being wirebonded.
  • Such operations i.e., application of insulative material, and curing/gelling of the insulative material
  • the insulative material/encapsulant is applied immediately after wirebonding (or almost immediately after, or as soon as practical after wirebonding using an automatic dispensing machine), and the curing/gelling is performed by application of heat and at least one of radiant energy exposure (e.g., ultraviolet, visible, or infrared), or by a thermal batch process.
  • the thermal process used to cure the insulative material may include: (1) a ramp in temperature; (2) a soaking period; and (3) a ramp down in temperature.
  • the dispensing means for heating and dispensing the insulative material may be provided as a new subsystem added to an existing wirebonding device, or may be provided as a stand alone system.
  • the insulative particles allow the insulative material to fill in between the bonding wires (which is particularly valuable in a semiconductor device that utilizes ultra fine pitch wirebonding); (2) a semiconductor device requiring substantially less volume of a potentially higher cost encapsulating material is provided, as opposed to a semiconductor device where the entire package is molded with the same material; and (3) a relatively low cost conventional molding compound or glob top encapsulation material (and associated equipment) may be used to overmold the package.
  • the application systems used to facilitate the various embodiments of the present invention may be designed to ensure that the packaging process does not suffer a reduction in productivity by the inclusion of the application of the insulative material.
  • the system can integrate the functions of dispensing and curing the insulative material while concurrently performing wirebonding operations.
  • the fine bonding wires are protected from motion that have resulted in short-circuiting of adjacent bonding wires. This is at least partially due to the rapid flow of the insulative material (e.g., molding compound or encapsulant).
  • FIG. 12 is a flow diagram illustrating a method of packaging a semiconductor device.
  • an insulative material is applied across only a portion of at least two of a plurality of conductors providing interconnection between elements in the semiconductor device.
  • the conductors and semiconductor elements are encapsulated, thereby packaging the semiconductor device.
  • the insulative material is cured after the applying step and before the encapsulating step.
  • the present invention has been described primarily in relation to a ring or rectangular shaped insulative material around or about a semiconductor element included in the semiconductor device, it is not limited thereto.
  • the insulative material may be provided in a number or configurations (e.g., a linear bridge of insulating material), so long as the conductors are stabilized to reduce wire sweep.
  • the insulative compound may be applied in a substantially circumferential shape about an inner element of the semiconductor device.
  • the substantially circumferential shape may be any of a number of geometric shapes such as a ring, a circle, an oval, a square or a rectangle. Further still, because the geometric shape is substantially circumferential, it does not necessarily completely surround the inner element of the semiconductor device.
  • an insulative material being a polymer material such as an epoxy resin
  • Various alternative insulative materials may be utilized so long as the material provides stability to conductors providing interconnection between elements of the semiconductor device.
  • the particles have been described primarily in relation to silica particles; however, the particles are not limited thereto.
  • Various alternative particles or beads may be utilized in the insulative material so long as the particles may disperse between adjacent conductors providing interconnection between elements of the semiconductor device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

A method of packaging a multi-tier wire bonded semiconductor device is provided. The method includes applying an insulative material across only a portion of at least two of a plurality of conductors per layer providing interconnection between elements in the multi-tier wire bonded semiconductor device. The method also includes encapsulating the conductors and elements, thereby packaging the semiconductor device.

Description

    CROSS REFERENCE TO RELATED APPLICATION
  • This application is a divisional of co-pending U.S. patent application Ser. No. 11/004,750, filed on Dec. 3, 2004 which is a continuation-in-part of co-pending U.S. patent application Ser. No. 10/686,892, filed on Oct. 16, 2003 and a continuation-in-part of co-pending U.S. patent application Ser. No. 10/686,974, filed on Oct. 16, 2003, and also claims the benefit of priority to U.S. Provisional Patent Application No. 60/587,678, filed on Jul. 14, 2004, the contents of which are incorporated in this application by reference.
    • FIELD OF THE INVENTION
  • This invention relates to packaging semiconductor devices, and more particularly to a method of reducing or eliminating wire sweep and sway in packaged semiconductor devices.
    • BACKGROUND OF THE INVENTION
  • In the fabrication of semiconductor devices, conductors (e.g., bonding wires) are often utilized to provide interconnection between elements of the semiconductor device. For example, FIG. 1 illustrates a portion of conventional semiconductor device 100. Semiconductor device 100 includes leadframe 102 and leadframe contact(s) 102 a. Semiconductor element (e.g., die) 104 is mounted on leadframe 102. Bonding wire 106 provides interconnection between semiconductor element 104 and leadframe contact 102 a. Overmold 108 (i.e., a mold compound) is provided over bonding wire 106, semiconductor element 104, and leadframe contact 102 a. In the configuration illustrated in FIG. 1, a number of bonding wires 106 may be included in semiconductor device 100 to provide interconnection between various connection points on semiconductor element 104 and corresponding leadframe contacts 102 a.
  • During the process of fabricating semiconductor device 100, short circuits between adjacent bonding wires 106, or open circuits in connection with one or more bonding wires 106 may occur. For example, during fabrication, movement (e.g., sway, sweep, etc.) of bonding wires 106 may result in a short circuit between adjacent bonding wires 106. Further, such movement of bonding wires may cause one or more bonding wires 106 to break, thus, causing an open circuit.
  • FIG. 2 illustrates a conventional semiconductor device 200 including an encapsulant 210 over bonding wire 106. Encapsulant 210 also covers the connection points between bonding wire 106 and each of semiconductor element 104 and leadframe contact 102 a. In other respects, the elements illustrated in FIG. 2 are very similar to those illustrated and described above with respect to FIG. 1.
  • FIG. 3 is a perspective view of a conventional semiconductor device 100, similar to the device illustrated in FIG. 1. Semiconductor element 104 is illustrated mounted on leadframe 102. A plurality of bonding wires 106 provide interconnection between semiconductor element 104 and corresponding leadframe contacts 102 a. Overmold 108 (partially cut away in FIG. 3) is provided over semiconductor element 104 and bonding wires 106.
  • FIG. 4 is a cut away side view of a conventional semiconductor device 400. As in FIGS. 1-3, semiconductor element 104 is mounted on leadframe 102, and bonding wires 106 provide interconnection between semiconductor element 104 and leadframe contacts 102 a. Encapsulant 410 is provided over semiconductor element 104, and bonding wires 106. Overmold 108 is provided above and below semiconductor element 104 in the illustration of FIG. 4.
  • Various problems have been found in the conventional semiconductor device configurations illustrated in FIGS. 1-4. As provided above, during fabrication and movement of the semiconductor devices, bonding wires 106 may be become loose (i.e., open circuit) at one of the connection points (i.e., at semiconductor element 104 or leadframe contact 102 a). Further, adjacent bonding wires 106 may move (e.g., sway) towards each other, thereby creating short circuits in the semiconductor device. These issues are particularly problematic in view of the desire to decrease the size of semiconductor devices (and the corresponding desire to increase conductor density in semiconductor devices). These fabrication shortcomings result in defective components within semiconductor lots, resulting in higher manufacturing costs and poor reliability. As such, it would be desirable to provide improved methods of fabricating semiconductor devices.
    • SUMMARY OF THE INVENTION
  • To overcome the deficiencies of the prior art, in an exemplary embodiment of the present invention, a method of packaging a multi-tier wire bonded semiconductor device is provided. The method includes applying an insulative material across only a portion of at least two of a plurality of conductors per layer providing interconnection between elements in the multi-tier wire bonded semiconductor device.
  • According to another aspect of the present invention, an encapsulant is applied to the conductors and elements, thereby packaging the semiconductor device.
  • According to yet another aspect of the present invention, the insulative compound comprises spherical silica particles to maintain a predetermined separation between adjacent ones of the plural conductors.
  • According to still another aspect of the present invention, the insulative compound is applied in a substantially circumferential manner about the at least one the semiconductor element.
  • According to a further aspect of the present invention, the insulative compound is applied in at least two geometric shape structures, each of the geometric shape structures substantially surrounding the at least one the semiconductor element in a circumferential manner.
  • According to still a further aspect of the present invention, the insulative material is applied in at least two distinct structures around a peripheral portion of the at least one the semiconductor element, the two structures not being in contact with one another.
  • According to yet a further aspect of the present invention, a semiconductor device comprises a plurality of semiconductor elements; a plurality of conductors arranged in a multiple tier configuration providing interconnection between the plurality of semiconductor elements; and an insulative material applied across only a portion of at least two of the plurality of conductors in at least two tiers of the multiple tiers.
  • These and other aspects will become apparent from the detailed description provided below.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The invention is best understood from the following detailed description when read in connection with the accompanying drawing. It is emphasized that, according to common practice, the various features of the drawing are not to scale. On the contrary, the dimensions of the various features are arbitrarily expanded or reduced for clarity. Included in the drawing are the following Figures:
  • FIG. 1 is a cut away side view of an interconnection between semiconductor elements in a prior art semiconductor device;
  • FIG. 2 is a cut away side view of an encapsulated interconnection between semiconductor elements in a prior art semiconductor device;
  • FIG. 3 is a perspective view of a plurality of interconnections between semiconductor elements in a prior art semiconductor device;
  • FIG. 4 is a cut away side view of an encapsulated interconnection between semiconductor elements in a prior art semiconductor device;
  • FIG. 5 is a cut away side view of an interconnection between semiconductor elements in a semiconductor device in accordance with an exemplary embodiment of the present invention;
  • FIG. 6 is a cut away side view of an interconnection between semiconductor elements in a semiconductor device in accordance with another exemplary embodiment of the present invention;
  • FIG. 7 is a perspective view of an interconnection between semiconductor elements in a semiconductor device in accordance with an exemplary embodiment of the present invention;
  • FIG. 8 is a perspective view of an interconnection between semiconductor elements in a semiconductor device in accordance with another exemplary embodiment of the present invention;
  • FIG. 9 is a cut away view of conductors separated by an insulative material in accordance with an exemplary embodiment of the present invention;
  • FIG. 10 is a chart illustrating a silica particle size distribution in an insulative material in accordance with an exemplary embodiment of the present invention;
  • FIG. 11 is another chart illustrating a silica particle size distribution in an insulative material in accordance with an exemplary embodiment of the present invention;
  • FIG. 12 is a flow diagram illustrating a method of packaging a semiconductor device in accordance with an exemplary embodiment of the present invention;
  • FIG. 13A is a cut away side view of an interconnection between semiconductor elements in a multi-tier wire bonded semiconductor device in accordance with an exemplary embodiment of the present invention;
  • FIG. 13B is a top plan view of the device illustrated in FIG. 13A;
  • FIG. 14A is a cut away side view of an interconnection between semiconductor elements in a multi-tier wire bonded semiconductor device in accordance with another exemplary embodiment of the present invention; and
  • FIG. 14B is a top plan view of the device illustrated in FIG. 14A.
    • DETAILED DESCRIPTION OF THE INVENTION
  • Preferred features of selected embodiments of this invention will now be described with reference to the figures. It will be appreciated that the spirit and scope of the invention is not limited to the embodiments selected for illustration. Also, it should be noted that the drawings are not rendered to any particular scale or proportion. It is contemplated that any of the configurations and materials described hereafter can be modified within the scope of this invention.
  • As used herein, the term semiconductor device relates to a broad category of devices including packaged semiconductor devices such as integrated circuits, memory devices, DSPs (i.e., digital signal processors), QFP (i.e., quad-flat package), PBGA (i.e., plastic ball grid array), BOC (board on chip), COB (i.e., chip on board), CABGA (chip array ball grid array), and discrete devices (i.e., non-packaged devices, may be more than one device on one board). Further, the term semiconductor element refers to any portion of a semiconductor device, including substrates, dies, chips, leadframes, leadframe contacts, etc.
  • Generally speaking, the present invention relates to placing a insulative material (e.g., in the form of a polymer bead, strip, or preformed shape) across bonding conductors (i.e., bonding wires) that provide interconnection between various semiconductor elements in a semiconductor device.
  • The insulative material (e.g., a polymer bridge) creates a lattice (i.e., a lattice bridge) or structure which will provide additional stability to the conductors such that the conductors are separated (i.e., not short-circuited) during further processing (e.g., during transfer molding). Further, if the insulative material is applied as at least partially fluid, it may distribute, through fluid forces, throughout the interconnected conductor network during molding of the semiconductor device. This separation and force transfer reduces wire sweep and sway, and reduces or eliminates short circuiting resulting from an overmolding process.
  • After application of the insulative material (e.g., a polymer material such as an epoxy resin), the resin is cured using at least one of heat or ultraviolet energy. An overmold may then be applied to provide a packaged semiconductor device without the wires moving or “sweeping” toward one another.
  • According to certain embodiments of the present invention, the methods and devices disclosed herein are particularly suited to the assembly of bonding wired semiconductor devices fabricated by contract and integrated device manufacturers. Certain embodiments of the present invention are particularly useful in relation to semiconductor devices having long conductors/bonding wires, or having complex bonding wired geometries (e.g., QFPs, stacked die devices, and BGAs).
  • In contrast to prior art fabrication methods, various embodiments of the present invention utilize very little insulative material (e.g., a polymer material) in ring, rectangular, and/or any suitable configurations around or about a semiconductor element included in the semiconductor device.
  • As will be explained herein, certain embodiments of the present invention provide additional advantages over prior art fabrication techniques, including: additional flexibility in the fabrication process, minimization of expensive polymer used for stabilizing the conductors, and universal semiconductor device application. Exemplary embodiments of the present invention reduce sweep on complex semiconductor device types (e.g., stacked die devices), and allow for extended conductor lengths in, for example, QFPs and BGAs.
  • FIG. 5 illustrates a cut away side view of semiconductor device 500 in accordance with an exemplary embodiment of the present invention. Semiconductor device 500 includes semiconductor element 504 (e.g., a die) mounted on leadframe 502. For example, semiconductor element 504 may be mounted to leadframe 502 using an adhesive. Bonding wires 506 provide interconnection between semiconductor element 504 and leadframe contacts 502 a. Before overmold 508 is applied to the device, insulative material 512 is applied to a portion of bonding wires 506. For example, insulative material 512 may be applied in a rectangular, ring, and/or any suitable shape around or about semiconductor element 504. Further, insulative material 512 may be positioned closer to semiconductor element 504 (as opposed to leadframe contacts 502 a), because bonding wires 506 have a closer pitch (i.e., are closer to adjacent bonding wires 506) at semiconductor element 504 than at leadframe contacts 502 a. Alternatively, insulative material 512 may be positioned midway between semiconductor element 504 and leadframe contacts 502 a. Further still, insulative material 512 may be positioned at any of a number of locations between semiconductor element 504 and leadframe contacts 502 a, as desired in a given device.
  • By providing insulative material 512 across bonding wires 506, the position of each of the bonding wires 506 with respect to one another is stabilized. By stabilizing bonding wires 506 with respect to one another using insulative material 512, the risk of short circuiting adjacent bonding wires 506 during application of overmold 508 is substantially reduced if not eliminated. Additionally, by stabilizing the position of bonding wires 506, open circuiting of bonding wires 506 during fabrication may also be substantially reduced.
  • Insulative material 512 may be, for example, a polymer material such as an epoxy resin. Additionally, insulative material 512 may include insulative particles or beads that distribute between bonding wires 506 during application of insulative material 512 to bonding wires 506. Such insulative beads further stabilize bonding wires 506 with respect to one another. According to an exemplary embodiment of the present invention, the insulative beads distributed in the insulative material have a mean particle size of approximately 4.1 μm, a median particle size of 4.5 μm, and a maximum particle size of 20 μm. These insulative beads may be, for example, spherical silica particles.
  • FIG. 6 is a cut away side view of semiconductor device 600, where semiconductor device 600 is similar to the semiconductor device 500 illustrated in FIG. 5. As with the exemplary embodiment of the present invention illustrated in FIG. 5, FIG. 6 illustrates insulative material 512 provided across a portion of bonding wires 506. However, in additional to insulative material 512, FIG. 6 also illustrates insulative material 514 provided across another portion of bonding wires 506. Insulative material 514 may be provided in a similar configuration to insulative material 512 (e.g., in a rectangular, ring, and/or any suitable shape around or about semiconductor element 504). Additionally, insulative material 514 may be a polymer material such as an epoxy resin, and may include insulative beads as described above with respect to FIG. 5.
  • FIG. 7 illustrates a semiconductor device 700 including semiconductor element 704 mounted on leadframe 702. Bonding wires 706 provide interconnection between semiconductor element 704 and leadframe contacts 702 a. Insulative material 712 is provided across a portion of bonding wires 706 to stabilize bonding wires 706 with respect to one another. In the exemplary embodiment of the present invention illustrated in FIG. 7, insulative material 712 is provided in a substantially ring shape (and/or any suitable shape) around or about semiconductor element 704. By providing insulative material 712 across a portion of bonding wires 706, open or short circuiting of bonding wires 706 may be substantially reduced prior to and during application of overmold 708.
  • FIG. 8 is a perspective view of semiconductor device 800 similar to the device illustrated in FIG. 7. In addition to the ring shaped insulative material 712 provided in FIG. 7, FIG. 8 illustrates insulative material 814 provided across a portion of bonding wires 706. By providing insulative material 814 in addition to insulative material 712, bonding wires 706 are further stabilized with respect to one another.
  • Although FIG. 7 illustrates semiconductor device 700 including single insulative material ring 712, and FIG. 8 illustrates semiconductor device 800 including insulative material ring 712 and insulative material ring 814, additional rings (or other shaped portions) of an insulative material may be provided. As such, one, two, three, or any of a number of rings/beads of insulative material may be applied to a given semiconductor device, as desired.
  • FIG. 9 is a cut away view of bonding wires 906 a, 906 b, and 906 c. For example, bonding wires 906 a, 906 b, and 906 c provide interconnection between a semiconductor element (not shown in FIG. 9) and leadframe contacts (not shown in FIG. 9) in a semiconductor device. Insulative material 912 is provided across a portion of bonding wires 906 a, 906 b, and 906 c. In the exemplary embodiment of the present invention illustrated in FIG. 9, insulative material 912 includes insulative beads. The insulative beads may be of a variety of different sizes, and because the insulative beads are smaller than the distance between adjacent bonding wires (e.g., between bonding wire 906 a and 906 b), the insulative beads disperse into a position between adjacent bonding wires, thereby providing enhanced stability and insulation between adjacent bonding wires.
  • FIG. 9 illustrates a distance “d1” representing a center-to-center distance (i.e., pitch) between bonding wires 906 a and 906 b. Further, FIG. 9 illustrates a distance “d2” representing a spacing between bonding wires 906 a and 906 b. According to an exemplary embodiment of the present invention, the insulative material may be applied to ultrafine pitch bonding wired semiconductor devices. For example, distance d1 in such a device may be approximately 35 μm or less, and distance d2 in such a device may be approximately 15 μm or less. By providing insulative material (e.g., with insulative beads dispersed therein) across a portion of the bonding wires, the improved bonding wire stability of the present invention may be applied to ultrafine pitch bonding wired semiconductor devices with small values for distances d1 and d2.
  • By fabricating semiconductor devices according to the methods described herein, conductor density within a semiconductor device may be increased, desirably resulting in a semiconductor device of decreased size.
  • An additional benefit of fabricating semiconductor devices according to the present invention is that because of the inclusion of the insulative material across a portion of the bonding wires, the overmold/encapsulation material used to encapsulate the device may be constructed of a less expensive material and process (e.g., mold type encapsulation as opposed to “glob-topping”) because the encapsulant does not necessarily need to stabilize the bonding wires.
  • The beads included in the insulative material utilized according to various exemplary embodiments of the present invention may be any of a number of types of insulative beads. For example, the beads may be constructed of a silica filler. Further, the insulative beads may be of varying types having varying sizes and shapes.
  • The insulative material of the present invention may include a high viscosity, ultraviolet curable silica. For example, the insulative material may be filled with silica at a weight percentage between 50-85%.
  • FIG. 10 is a bar chart illustrating an exemplary particle size (i.e., particle size diameter) distribution of two distinct silica fillers (e.g., SiO2) used in an insulative material according to an exemplary embodiment of the present invention. In the exemplary distribution illustrated in FIG. 10, the silica 2 particle size beads range from approximately 0.05 microns to approximately 0.5 microns. Further, the distribution of silica 1 particle size beads ranges from approximately 0.5 microns to approximately 20 microns. The y-axis of the bar chart of FIG. 10 illustrates the percentage of each size of each of the silica 1 and silica 2 particles.
  • The silica fillers charted in FIG. 10 have proven to be particularly useful when dispersed within insulative materials (e.g., epoxy resin) according to certain exemplary embodiments of the present invention. The individual distribution of the silica diameter sizes for the type of spherical silica designated silica 1 is: 0% are greater than 24 microns, 1.1% are less than 24 microns and greater than 16 microns, 4.0% are less than 16 microns and greater than 12 microns, 11.5% are less than 12 microns and greater than 8 microns, 12.8% are less than 8 microns and greater than 6 microns, 35.8% are less than 6 microns and greater than 3 microns, 13.3% are less than 3 microns and greater than 2 microns, 12.5% are less than 2 microns and greater than 1 microns, 7.0% are less than 1 microns and greater than 0.5 microns, and 2.0% are less than 0.5 microns and greater than 0 microns. The individual distribution of the silica diameter sizes for the type of spherical silica designated silica 2 is: 0% are greater than 0.6 microns, 0.5% are less than 0.6 microns and greater than 0.5 microns, 7.03% are less than 0.5 microns and greater than 0.45 microns, 9.13% are less than 0.45 microns and greater than 0.4 microns, 12.83% are less than 0.4 microns and greater than 0.35 microns, 13.43% are less than 0.35 microns and greater than 0.3 microns, 13.33% are less than 0.3 microns and greater than 0.25 microns, 9.33% are less than 0.25 microns and greater than 0.2 microns, 5.83% are less than 0.2 microns and greater than 0.15 microns, 4.33% are less than 0.15 microns and greater than 0.1 microns, 5.83% are less than 0.1 microns and greater than 0.09 microns, 5.93% are less than 0.09 microns and greater than 0.08 microns, 5.53% are less than 0.08 microns and greater than 0.07 microns, 4.93% are less than 0.07 microns and greater than 0.06 microns, 1.73% are less than 0.06 microns and greater than 0.05 microns, and 0.31% are less than 0.05 microns.
  • According to yet another exemplary embodiment of the present invention, insulative material is applied across a plurality of bonding wire layers in a multi-tier wire bonded semiconductor device. Thus, short circuiting and other problems associated with wire sweep and sway are reduced and/or eliminated in a multi-tier wire bonded semiconductor device. In certain exemplary embodiments of the present invention, the insulative material may be applied across the multiple bonding wire layers in addition to application of the insulative material across adjacent conductors as described above.
  • FIG. 13A illustrates a cut away side view of semiconductor device 1300 in accordance with an exemplary embodiment of the present invention, and FIG. 13B is a top view thereof. Semiconductor device 1300 includes semiconductor element 1304 (e.g., a die) mounted on leadframe 1302. For example, semiconductor element 1304 may be mounted to leadframe 1302 using an adhesive. Bonding wires 1306 provide interconnection between semiconductor element 1304 and another portion of semiconductor device 1300, for example, leadframe contacts not illustrated in FIG. 13A. Before an overmold may be applied to the device, insulative material 1312 is applied to a portion of bonding wires 1306. For example, insulative material 1312 may be applied in a rectangular, ring, and/or any suitable shape around or about semiconductor element 1304. As provided above, insulative material 1312 may be positioned at any of a number of locations between semiconductor element 1304 and the other connection point of bonding wires 1306, as desired in a given device.
  • As illustrated in FIGS. 14A and 14B, in device 1400, insulative material 1312 may be positioned at any of number of locations between semiconductor element 1304 and the other connection point of bonding wires 1306, as desired in a given device.
  • It is also contemplated to have more than one disposition of insulative material on a single semiconductor device at different location or, more specifically, insulative material 1312 may be disposed at any of number of locations and any number of times between semiconductor element 1304 and the other connection point of bonding wires 1306, as desired in a given device. It is also contemplated that insulative material may or may not contact semiconductor element 1304 and/or lead frame 1302, as illustrated in FIG. 14A.
  • Referring again to FIG. 13A, bonding wires 1306 are provided in layers or tiers (i.e., device 1300 is a multi-tier wire bonded semiconductor device). Insulative material 1312 is provided across each of the bonding wire layers, thereby reducing or substantially eliminating short circuiting due to wire sweep and other associated problems as described herein. Of course, insulative material 1312 is not necessarily provided across each of the bonding wire layers. For example, in certain configurations with four layers of bonding wires (as illustrated in FIG. 13A), insulative material 1312 may be provided across 2, 3, or all 4 layers, as desired in the specific application.
  • By providing insulative material 1312 across bonding wires 1306, the position of each layer of the bonding wires 1306 with respect to one another is stabilized. By stabilizing the layers of the bonding wires 1306 with respect to one another using insulative material 1312, the risk of short circuiting adjacent layers of bonding wires 1306 (e.g., during application of an overmold) is substantially reduced if not eliminated. Additionally, by stabilizing the position of the layers of bonding wires 1306, open circuiting of bonding wires 1306 during fabrication may also be substantially reduced.
  • As provided above in connection with alternative embodiments of the present invention, insulative material 1312 may be, for example, a polymer material such as an epoxy resin. Additionally, insulative material 1312 may include insulative particles or beads that distribute between layers of bonding wires 1306 during application of insulative material 1306. Such insulative beads further stabilize layers of bonding wires 1306 with respect to one another. These insulative beads may be, for example, spherical silica particles.
  • As provided above, insulative beads (e.g., silica particles) or varying types and sizes may be mixed in an insulative material according to certain exemplary embodiments of the present invention. For example, the silica 1 distribution of particles may be mixed with the silica 2 distribution of particles. In one embodiment, 10 parts of the silica 1 distribution of particles is mixed with 3 parts of the type silica 2 distribution of particles. A bar chart illustrating the SiO2 particle size distribution of such a mixture is provided in FIG. 11.
  • The individual distribution of the silica diameter sizes for the mixture of spherical silica illustrated in FIG. 11 is: 0% are greater than 24 microns, 0.85% are less than 24 microns and greater than 16 microns, 3.08% are less than 16 microns and greater than 12 microns, 8.85% are less than 12 microns and greater than 8 microns, 9.85% are less than 8 microns and greater than 6 microns, 27.54% are less than 6 microns and greater than 3 microns, 10.23% are less than 3 microns and greater than 2 microns, 9.62% are less than 2 microns and greater than 1 microns, 5.5% are less than 1 microns and greater than 0.6 microns, 3.16% are less than 0.6 microns and greater than 0.5 microns, 2.11% are less than 0.5 microns and greater than 0.45 microns, 2.96% are less than 0.45 microns and greater than 0.4 microns, 3.1% are less than 0.4 microns and greater than 0.35 microns, 3.08% are less than 0.35 microns and greater than 0.3 microns, 2.15% are less than 0.3 microns and greater than 0.25 microns, 1.35% are less than 0.25 microns and greater than 0.2 microns, 1.0% are less than 0.2 microns and greater than 0.15 microns, 1.35% are less than 0.15 microns and greater than 0.1 microns, 1.37% are less than 0.1 microns and greater than 0.09 microns, 1.28% are less than 0.09 microns and greater than 0.08 microns, 1.14% are less than 0.08 microns and greater than 0.07 microns, 0.4% are less than 0.07 microns and greater than 0.06 microns, 0.07% are less than 0.06 microns and greater than 0.05 microns, and 0% are less than 0.05 microns.
  • It has been found that the application of an insulative material according to the present invention is particularly useful in protecting bonding wires in semiconductor packages from wire sweep during fabrication (e.g., during the overmolding process after application of the insulative material), where the length to diameter ratio of the longest bonding wires is greater than 250. In certain embodiments, the process includes dispensing the insulative material (e.g., while the semiconductor device is still on the wirebonding machine), and thereafter a period of time is provided for the material to flow. The flow time can be, for example, from two to 50 seconds (and more specifically between 7 and 25 seconds) depending on several conditions such as size of the semiconductor device, temperature of the semiconductor device, temperature of the insulative material during dispensing, and the density of the conductors providing interconnection between the elements. Thereafter, the insulative material is cured using some combination of heat, UV radiation, visible radiation, and IR radiation.
  • As provided herein, the application of the insulative material including insulative particles of specific sizes and quantities is particularly useful in improving the ability of the insulative material to flow between and separate, short-circuited bonding wire pairs. For example, small diameter inorganic particles may be used to fill in between the bonding wires. Furthermore, the type of insulative material (e.g., polymer resin) utilized may enhance the surface energy properties of the insulative material/encapsulant to maximize the short-circuit prevention and reduction properties.
  • For example, the scale of the insulative particles (i.e., filler particles) is explicitly smaller than the desired gaps between adjacent bonding wires, and is added in specific sizes and quantities to improve the flow of the insulative material. The insulative material/encapsulant may be rapidly cured through exposure to a UV source of radiation, or to a combination of UV radiation, visible radiation, and infrared radiation. The methods disclosed herein are particularly useful when the insulative material is applied immediately or shortly after wirebonding, and when the bonding wire lengths are at least 250 times larger than the bonding wire diameter.
  • Through the various exemplary embodiments disclosed herein, the present invention may provide packaged semiconductor devices with longer, thinner, bonding wires, and with a higher density of I/O connections, at smaller pad pitch. The yield of the semiconductor devices is also increased, particularly with respect to post-bond substrate handling, overmolding, and globtop encapsulation. The yield of the semiconductor devices is increased by preventing shorts of fine pitch, small diameter wirebonded semiconductor devices through the application of the insulative material including a combination of small and intermediate size insulative particles (e.g., spherical silica particles) to the device for dispersion and distribution between adjacent bonding wires, and subsequently curing/gelling the insulative material (e.g., on the wirebonder) using heat, exposure to radiation (ultraviolet, visible, and/or infrared), and/or through a thermal batch process. According to an exemplary embodiment of the present invention, the insulative material, including the combination of small and intermediate size spherical silica, is applied using an automatic dispensing machine as soon as is practical after wirebonding.
  • The curing and/or gelling of the insulative material may vary depending upon the embodiment of the present invention utilized. For example, the insulative material may be cured/gelled directly on the wirebonder using heat and exposure to ultraviolet radiation. According to another exemplary embodiment of the present invention, the insulative material may be cured/gelled on the wirebonder by heat and exposure to one of more of ultraviolet, visible, and infrared radiation. According to yet another exemplary embodiment of the present invention, the insulative material may be cured/gelled using a thermal batch process.
  • The insulative material may be an epoxy encapsulant material including substantially spherical silica particles that are, at least partially, smaller than the desired space between adjacent bonding wires in an ultrafine pitch wirebonded semiconductor device. In such an embodiment, the encapsulant material may be designed such that a specific intensity, duration, and wavelength distribution of ultraviolet radiation, visible radiation, and/or infrared radiation, rapidly gels or at least partially cures the encapsulant material. Further, the characteristics of the insulative material, and the application process parameters thereof, may be designed such that as the insulative material is dispensed onto the wirebonded semiconductor device, it covers the entire bonding wire(s), or a portion of the bonding wire(s).
  • Further still, the insulative material may be applied in any of a number of directions. For example, the insulative material may be applied from a leadframe contact towards an inner semiconductor element of the semiconductor device (e.g., a die). Alternatively, the insulative material may be applied from an inner semiconductor element of the semiconductor device (e.g., a die) towards a leadframe contact of the semiconductor device. Yet another alternative would be to apply the insulative material from directly above (or below) the bonding wires themselves.
  • Before application of the insulative material, the semiconductor device is preferably heated, for example, to a temperature between 50° C. and 125° C., and more specifically to a temperature between 80° C. and 100° C. Further, the insulative material dispenser is also preferably heated, for example, to a temperature between 35° C. and 85° C., and more specifically to a temperature between 50° C. and 70° C. By heating the insulative material in the insulative material dispenser, it is easier to dispense the insulative material.
  • As provided above, the insulative material preferably includes a filler material including insulative particles. For example, the filler material may be assembled from combinations of silica with size distributions determined based on various criteria. For example, the size distribution may be based on the following objectives: (1) to carry small silica particles into the narrow space between adjacent bonding wires, thereby driving the bonding wires apart; (2) to force the silica (e.g., by a capillary force) to provide a relatively high level of electrical isolation between adjacent bonding wires; (3) to fix the silica and the remainder of the insulative material (e.g., polymer) in place to stabilize the bonding wires, thereby sustaining the electrically insulative capabilities of the insulative material; (4) to minimally interfere with the fragile wire loops during the application of the insulative material; (5) to increase the packing density of the silica particles to achieve a low CTE; and (6) to provide smooth flowing capabilities of the insulative material.
  • The process of applying the insulative material may include dispensing of the insulative material, and curing the insulative material while the semiconductor device is on the wirebonding machine, such that the delicate loops of the thin bonding wire are stabilized and preserved immediately after (or shortly thereafter) the wirebonding process is complete.
  • Further still, the dispensing of the insulative material may occur while successive semiconductor devices are being wirebonded, such that a relatively quick and efficient fabrication process may be accomplished. For example, while a first semiconductor device is receiving the insulative material from the insulating material dispenser (and subsequently being cured/gelled), a second semiconductor device is being wirebonded. Such operations (i.e., application of insulative material, and curing/gelling of the insulative material) may be applied to both the first and second semiconductor devices on the same wirebonding apparatus.
  • As provided above, the insulative material/encapsulant is applied immediately after wirebonding (or almost immediately after, or as soon as practical after wirebonding using an automatic dispensing machine), and the curing/gelling is performed by application of heat and at least one of radiant energy exposure (e.g., ultraviolet, visible, or infrared), or by a thermal batch process. For example, the thermal process used to cure the insulative material may include: (1) a ramp in temperature; (2) a soaking period; and (3) a ramp down in temperature.
  • The dispensing means for heating and dispensing the insulative material (including the insulative particles) may be provided as a new subsystem added to an existing wirebonding device, or may be provided as a stand alone system.
  • Through the various embodiments of the present invention disclosed herein, the following benefits are achieved: (1) the insulative particles allow the insulative material to fill in between the bonding wires (which is particularly valuable in a semiconductor device that utilizes ultra fine pitch wirebonding); (2) a semiconductor device requiring substantially less volume of a potentially higher cost encapsulating material is provided, as opposed to a semiconductor device where the entire package is molded with the same material; and (3) a relatively low cost conventional molding compound or glob top encapsulation material (and associated equipment) may be used to overmold the package.
  • The application systems used to facilitate the various embodiments of the present invention may be designed to ensure that the packaging process does not suffer a reduction in productivity by the inclusion of the application of the insulative material. For example, through the use of software controls and sensor fusion, the system can integrate the functions of dispensing and curing the insulative material while concurrently performing wirebonding operations. Further, after application of the insulative material, as the packaging process continues (e.g., through resin transfer molding, glob top encapsulation, etc.), the fine bonding wires are protected from motion that have resulted in short-circuiting of adjacent bonding wires. This is at least partially due to the rapid flow of the insulative material (e.g., molding compound or encapsulant).
  • FIG. 12 is a flow diagram illustrating a method of packaging a semiconductor device. At step 1202, an insulative material is applied across only a portion of at least two of a plurality of conductors providing interconnection between elements in the semiconductor device. At step 1204, the conductors and semiconductor elements are encapsulated, thereby packaging the semiconductor device. At optional step 1206, the insulative material is cured after the applying step and before the encapsulating step.
  • Although the present invention has been described primarily in relation to a ring or rectangular shaped insulative material around or about a semiconductor element included in the semiconductor device, it is not limited thereto. The insulative material may be provided in a number or configurations (e.g., a linear bridge of insulating material), so long as the conductors are stabilized to reduce wire sweep.
  • Further, the insulative compound may be applied in a substantially circumferential shape about an inner element of the semiconductor device. The substantially circumferential shape may be any of a number of geometric shapes such as a ring, a circle, an oval, a square or a rectangle. Further still, because the geometric shape is substantially circumferential, it does not necessarily completely surround the inner element of the semiconductor device.
  • Although the present invention has been described primarily in relation to an insulative material being a polymer material such as an epoxy resin, it is not limited thereto. Various alternative insulative materials may be utilized so long as the material provides stability to conductors providing interconnection between elements of the semiconductor device.
  • In embodiments of the present invention including insulative particles in the insulative material, the particles have been described primarily in relation to silica particles; however, the particles are not limited thereto. Various alternative particles or beads may be utilized in the insulative material so long as the particles may disperse between adjacent conductors providing interconnection between elements of the semiconductor device.
  • It will be appreciated that other modifications can be made to the illustrated embodiments without departing from the scope of this invention, which is separately defined in the appended claims.

Claims (24)

1. A semiconductor device comprising:
a plurality of semiconductor elements;
a plurality of conductors arranged in a multiple tier configuration providing interconnection between the plurality of semiconductor elements; and
an insulative material applied across only a portion of at least two of the plurality of conductors in at least two tiers of multiple tiers, the insulative material comprising insulative particles having a diameter smaller than a gap between adjacent ones of the conductors.
2. The semiconductor device of claim 1 further comprising an encapsulation layer encapsulating the conductors and elements for packaging the semiconductor device.
3. The semiconductor device of claim 1 wherein the plurality of semiconductor elements includes at least one semiconductor die having a plurality of first contacts, and a lead frame having a plurality of second contacts, the plurality of conductors providing interconnection between the plurality of first contacts and the plurality of second contacts.
4. The semiconductor device of claim 3 wherein the insulative material is disposed across the portion of the at least two of the plurality of conductors adjacent the semiconductor die.
5. The semiconductor device of claim 3 wherein the insulative material is disposed across the portion of the at least two of the plurality of conductors approximately midway between the semiconductor die and the leadframe.
6. The semiconductor device of claim 1 wherein the insulative material is a curable insulative material.
7. The semiconductor device of claim 1 wherein the insulative material has a bead or bead-like form.
8. The semiconductor device of claim 1 wherein the insulative material is at least one of a heat induced curable insulative material and a UV radiation curable insulative material.
9. The semiconductor device of claim 1 wherein the insulative material is comprised of a plurality of spherical silica particles.
10. The semiconductor device of claim 1 wherein the insulative material is applied around a peripheral portion of an inner element of the semiconductor device.
11. The semiconductor device of claim 1 wherein the insulative material is at least two distinct substantially circumferential structures around a peripheral portion of an inner element of the semiconductor device, the two structures not being in contact with one another.
12. The semiconductor device of claim 11 wherein at a first one of the at least two distinct substantially circumferential structures contacts a portion of the inner element and/or a second one of the at least two distinct substantially circumferential structures contacts a portion of a carrier supporting the inner element.
13. A semiconductor device comprising:
at least one semiconductor element;
a carrier for supporting the at least one semiconductor element;
a plurality of conductors arranged in a multiple tier configuration providing interconnection between the at least one semiconductor element and the carrier; and
an insulative material comprising insulative particles having a diameter smaller than a desired predetermined gap between adjacent ones of the plurality of conductors, the insulative material applied across only a portion of at least two of the plurality of conductors in at least two tiers of the multiple tiers for reducing a potential for short circuiting between adjacent ones of the plurality of conductors.
14. The semiconductor device of claim 13 wherein the insulative material includes a polymer resin, and the insulative particles are silica particles.
15. The semiconductor device of claim 13 wherein the insulative material is at least partially cured by at least one of ultraviolet, visible, and infrared radiation.
16. The semiconductor device of claim 13 wherein the insulative particles occupy between 50 and 85 percent of the weight of the insulative material.
17. The semiconductor device of claim 13 wherein the insulative particles have a maximum diameter of 20 microns.
18. The semiconductor device of claim 13 wherein the insulative particles have a median diameter of approximately 4.5 microns.
19. The semiconductor device of claim 13 wherein the insulative particles have a mean diameter of approximately 4.1 microns.
20. The semiconductor device of claim 13 wherein the insulative particles provide insulated separation between at least two of the plurality of conductors.
21. The semiconductor device of claim 13 further comprising an encapsulation layer encapsulating the at least one semiconductor element, the carrier, the plurality of conductors, and the insulative material.
22. The semiconductor device of claim 21 wherein the encapsulation layer includes an overmold encapsulant.
23. The semiconductor device of claim 21 wherein the encapsulation layer includes a globtop encapsulant.
24. The semiconductor device of claim 21 wherein each of the plurality of conductors have a length at least 250 times greater than a diameter of the respective conductor.
US11/561,577 2003-10-16 2006-11-20 Method for reducing or eliminating semiconductor device wire sweep in a multi-tier bonding device and a device produced by the method Abandoned US20070096342A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/561,577 US20070096342A1 (en) 2003-10-16 2006-11-20 Method for reducing or eliminating semiconductor device wire sweep in a multi-tier bonding device and a device produced by the method

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US10/686,892 US6847122B1 (en) 2003-10-16 2003-10-16 System and method for preventing and alleviating short circuiting in a semiconductor device
US10/686,974 US6955949B2 (en) 2003-10-16 2003-10-16 System and method for reducing or eliminating semiconductor device wire sweep
US58767804P 2004-07-14 2004-07-14
US11/004,750 US7179688B2 (en) 2003-10-16 2004-12-03 Method for reducing or eliminating semiconductor device wire sweep in a multi-tier bonding device and a device produced by the method
US11/561,577 US20070096342A1 (en) 2003-10-16 2006-11-20 Method for reducing or eliminating semiconductor device wire sweep in a multi-tier bonding device and a device produced by the method

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US11/004,750 Division US7179688B2 (en) 2003-10-16 2004-12-03 Method for reducing or eliminating semiconductor device wire sweep in a multi-tier bonding device and a device produced by the method

Publications (1)

Publication Number Publication Date
US20070096342A1 true US20070096342A1 (en) 2007-05-03

Family

ID=37995214

Family Applications (2)

Application Number Title Priority Date Filing Date
US11/004,750 Expired - Fee Related US7179688B2 (en) 2003-10-16 2004-12-03 Method for reducing or eliminating semiconductor device wire sweep in a multi-tier bonding device and a device produced by the method
US11/561,577 Abandoned US20070096342A1 (en) 2003-10-16 2006-11-20 Method for reducing or eliminating semiconductor device wire sweep in a multi-tier bonding device and a device produced by the method

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US11/004,750 Expired - Fee Related US7179688B2 (en) 2003-10-16 2004-12-03 Method for reducing or eliminating semiconductor device wire sweep in a multi-tier bonding device and a device produced by the method

Country Status (1)

Country Link
US (2) US7179688B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080131999A1 (en) * 2006-12-01 2008-06-05 Hem Takiar Method of die stacking using insulated wire bonds
US11056457B2 (en) 2018-09-28 2021-07-06 Nxp Usa, Inc. Semiconductor device with bond wire reinforcement structure

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2909656B1 (en) * 2006-12-12 2009-12-04 Thales Sa WIRING RELAY AND PROTECTION HOUSING OF ELECTROMECHANICAL MICRO-SYSTEM.
US20090032972A1 (en) * 2007-03-30 2009-02-05 Kabushiki Kaisha Toshiba Semiconductor device
KR100874925B1 (en) * 2007-06-04 2008-12-19 삼성전자주식회사 Semiconductor package, manufacturing method thereof, card comprising same and system comprising same
JP2011077108A (en) * 2009-09-29 2011-04-14 Elpida Memory Inc Semiconductor device
US8536717B2 (en) * 2012-01-10 2013-09-17 Xilinx, Inc. Integrated circuit package and method of assembling an integrated circuit package
US10847488B2 (en) * 2015-11-02 2020-11-24 Mediatek Inc. Semiconductor package having multi-tier bonding wires and components directly mounted on the multi-tier bonding wires

Citations (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4523371A (en) * 1979-08-01 1985-06-18 Yoshiaki Wakashima Method of fabricating a resin mold type semiconductor device
US4788583A (en) * 1986-07-25 1988-11-29 Fujitsu Limited Semiconductor device and method of producing semiconductor device
US4974057A (en) * 1986-10-31 1990-11-27 Texas Instruments Incorporated Semiconductor device package with circuit board and resin
US5097317A (en) * 1989-09-08 1992-03-17 Mitsubishi Denki Kabushiki Kaisha Resin-sealed semiconductor device
US5206794A (en) * 1991-12-20 1993-04-27 Vlsi Technology, Inc. Integrated circuit package with device and wire coat assembly
US5310702A (en) * 1992-03-20 1994-05-10 Kulicke And Soffa Industries, Inc. Method of preventing short-circuiting of bonding wires
US5331205A (en) * 1992-02-21 1994-07-19 Motorola, Inc. Molded plastic package with wire protection
US5434105A (en) * 1994-03-04 1995-07-18 National Semiconductor Corporation Process for attaching a lead frame to a heat sink using a glob-top encapsulation
US5656830A (en) * 1992-12-10 1997-08-12 International Business Machines Corp. Integrated circuit chip composite having a parylene coating
US5736792A (en) * 1995-08-30 1998-04-07 Texas Instruments Incorporated Method of protecting bond wires during molding and handling
US5818105A (en) * 1994-07-22 1998-10-06 Nec Corporation Semiconductor device with plastic material covering a semiconductor chip mounted on a substrate of the device
US5863810A (en) * 1994-05-09 1999-01-26 Euratec B.V. Method for encapsulating an integrated circuit having a window
US6177726B1 (en) * 1999-02-11 2001-01-23 Philips Electronics North America Corporation SiO2 wire bond insulation in semiconductor assemblies
US6184587B1 (en) * 1993-11-16 2001-02-06 Formfactor, Inc. Resilient contact structures, electronic interconnection component, and method of mounting resilient contact structures to electronic components
US6215182B1 (en) * 1999-10-19 2001-04-10 Fujitsu Limited Semiconductor device and method for producing the same
US6297078B1 (en) * 1997-12-31 2001-10-02 Intel Corporation Integrated circuit package with bond wires at the corners of an integrated circuit
US6340846B1 (en) * 2000-12-06 2002-01-22 Amkor Technology, Inc. Making semiconductor packages with stacked dies and reinforced wire bonds
US6344401B1 (en) * 2000-03-09 2002-02-05 Atmel Corporation Method of forming a stacked-die integrated circuit chip package on a water level
US6368899B1 (en) * 2000-03-08 2002-04-09 Maxwell Electronic Components Group, Inc. Electronic device packaging
US6395807B1 (en) * 1998-08-21 2002-05-28 Nippon Chemical Industrial Co., Ltd Fine spherical silica and liquid sealing resin composition containing same
US6429044B1 (en) * 2000-08-31 2002-08-06 Micron Technology, Inc. Method and apparatus for magnetic shielding of an integrated circuit
US6847122B1 (en) * 2003-10-16 2005-01-25 Kulicke & Soffa Investments, Inc. System and method for preventing and alleviating short circuiting in a semiconductor device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03229433A (en) 1990-02-02 1991-10-11 Matsushita Electric Ind Co Ltd Semiconductor device
JPH04158557A (en) 1990-10-22 1992-06-01 Matsushita Electron Corp Reasin-sealed type semiconductor device and manufacture thereof
JP3400548B2 (en) 1993-06-29 2003-04-28 三菱レイヨン株式会社 Method for producing high-purity spherical silica
JPH1187424A (en) 1997-09-10 1999-03-30 Hitachi Ltd Semiconductor device and production thereof
JP2000332165A (en) 1999-05-17 2000-11-30 Toray Ind Inc Resin composition for sealing semiconductor and semiconductor device employing it
JP2001068802A (en) 1999-08-31 2001-03-16 Kyocera Corp Insulation sheet for wiring board and manufacture thereof
JP2002368029A (en) 2001-06-06 2002-12-20 Hitachi Ltd Method of manufacturing semiconductor device
US6608390B2 (en) * 2001-11-13 2003-08-19 Kulicke & Soffa Investments, Inc. Wirebonded semiconductor package structure and method of manufacture

Patent Citations (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4523371A (en) * 1979-08-01 1985-06-18 Yoshiaki Wakashima Method of fabricating a resin mold type semiconductor device
US4788583A (en) * 1986-07-25 1988-11-29 Fujitsu Limited Semiconductor device and method of producing semiconductor device
US4974057A (en) * 1986-10-31 1990-11-27 Texas Instruments Incorporated Semiconductor device package with circuit board and resin
US5097317A (en) * 1989-09-08 1992-03-17 Mitsubishi Denki Kabushiki Kaisha Resin-sealed semiconductor device
US5206794A (en) * 1991-12-20 1993-04-27 Vlsi Technology, Inc. Integrated circuit package with device and wire coat assembly
US5331205A (en) * 1992-02-21 1994-07-19 Motorola, Inc. Molded plastic package with wire protection
US5310702A (en) * 1992-03-20 1994-05-10 Kulicke And Soffa Industries, Inc. Method of preventing short-circuiting of bonding wires
US5656830A (en) * 1992-12-10 1997-08-12 International Business Machines Corp. Integrated circuit chip composite having a parylene coating
US5824568A (en) * 1992-12-10 1998-10-20 International Business Machines Corporation Process of making an integrated circuit chip composite
US6184587B1 (en) * 1993-11-16 2001-02-06 Formfactor, Inc. Resilient contact structures, electronic interconnection component, and method of mounting resilient contact structures to electronic components
US5434105A (en) * 1994-03-04 1995-07-18 National Semiconductor Corporation Process for attaching a lead frame to a heat sink using a glob-top encapsulation
US5863810A (en) * 1994-05-09 1999-01-26 Euratec B.V. Method for encapsulating an integrated circuit having a window
US5818105A (en) * 1994-07-22 1998-10-06 Nec Corporation Semiconductor device with plastic material covering a semiconductor chip mounted on a substrate of the device
US5736792A (en) * 1995-08-30 1998-04-07 Texas Instruments Incorporated Method of protecting bond wires during molding and handling
US6297078B1 (en) * 1997-12-31 2001-10-02 Intel Corporation Integrated circuit package with bond wires at the corners of an integrated circuit
US6395807B1 (en) * 1998-08-21 2002-05-28 Nippon Chemical Industrial Co., Ltd Fine spherical silica and liquid sealing resin composition containing same
US6177726B1 (en) * 1999-02-11 2001-01-23 Philips Electronics North America Corporation SiO2 wire bond insulation in semiconductor assemblies
US6215182B1 (en) * 1999-10-19 2001-04-10 Fujitsu Limited Semiconductor device and method for producing the same
US6368899B1 (en) * 2000-03-08 2002-04-09 Maxwell Electronic Components Group, Inc. Electronic device packaging
US6344401B1 (en) * 2000-03-09 2002-02-05 Atmel Corporation Method of forming a stacked-die integrated circuit chip package on a water level
US6429044B1 (en) * 2000-08-31 2002-08-06 Micron Technology, Inc. Method and apparatus for magnetic shielding of an integrated circuit
US6340846B1 (en) * 2000-12-06 2002-01-22 Amkor Technology, Inc. Making semiconductor packages with stacked dies and reinforced wire bonds
US6847122B1 (en) * 2003-10-16 2005-01-25 Kulicke & Soffa Investments, Inc. System and method for preventing and alleviating short circuiting in a semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080131999A1 (en) * 2006-12-01 2008-06-05 Hem Takiar Method of die stacking using insulated wire bonds
US11056457B2 (en) 2018-09-28 2021-07-06 Nxp Usa, Inc. Semiconductor device with bond wire reinforcement structure

Also Published As

Publication number Publication date
US20050121798A1 (en) 2005-06-09
US7179688B2 (en) 2007-02-20

Similar Documents

Publication Publication Date Title
US7102209B1 (en) Substrate for use in semiconductor manufacturing and method of making same
US20070096342A1 (en) Method for reducing or eliminating semiconductor device wire sweep in a multi-tier bonding device and a device produced by the method
US7109586B2 (en) System for reducing or eliminating semiconductor device wire sweep
US7211466B2 (en) Stacked die semiconductor device
US7595551B2 (en) Semiconductor package for a large die
US5817540A (en) Method of fabricating flip-chip on leads devices and resulting assemblies
US5897339A (en) Lead-on-chip semiconductor device package having an adhesive layer formed from liquid adhesive and method for manufacturing the same
US7301225B2 (en) Multi-row lead frame
US6040633A (en) Oxide wire bond insulation in semiconductor assemblies
CN106898591A (en) A kind of multi-chip framework encapsulation structure of radiating and preparation method thereof
US6054772A (en) Chip sized package
US7642638B2 (en) Inverted lead frame in substrate
KR20070015014A (en) Method of making a stacked die package
US6847122B1 (en) System and method for preventing and alleviating short circuiting in a semiconductor device
EP3163610A1 (en) Semiconductor package with coated bonding wires
KR20060063615A (en) Method for reducing or eliminating semiconductor device wire sweep in a multi-tier bonding device and a device produced by the method
US5759875A (en) Reduced filler particle size encapsulant for reduction in die surface damage in LOC packages and method of use
JP2003168696A (en) Method for manufacturing semiconductor device
TWI236107B (en) Semiconductor chip package and method for making the same
CN1722397A (en) Method for reducing or eliminating semiconductor device wire sweep and a device produced by the method
JP2006032955A5 (en)

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO PAY ISSUE FEE