TWI236107B - Semiconductor chip package and method for making the same - Google Patents
Semiconductor chip package and method for making the same Download PDFInfo
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- TWI236107B TWI236107B TW092120717A TW92120717A TWI236107B TW I236107 B TWI236107 B TW I236107B TW 092120717 A TW092120717 A TW 092120717A TW 92120717 A TW92120717 A TW 92120717A TW I236107 B TWI236107 B TW I236107B
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- wafer
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- horizontal plane
- lead frame
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
1236107 五、發明說明（1) 【發明所屬 本發明係 法。 【先前技術 習用半導 化過程黏著 複數個引腳 注膠封裝製 由於該半 此遇到溫度 晶片與導線 導致該晶片 的溫度越高 應力而彎翹 造成不利影 【發明内容 本發明之 方法以克服 根據本發 架、一半導 引腳、複數 水平面以及 該半導體晶 塾（bond i ng 之技術領域】 有關於一種半導體晶片封裝構造及其製造方 體晶片封裝構造係包含一晶片藉銀膠經由一固 固定於一導線架之晶片承座。該導線架尚包含 。該晶片係電性連接於该引腳5再以樹脂材料 成一半導體晶片封裝構造。 導體晶片與導線架熱膨脹係數差異相當大，因 快速改變時（例如前述之膠層固化製程），該 架會隨溫度變化而產生不同的膨脹或收縮量而 與導線架的結構彎赵（w a r p a g e );並且所需要 或時間越長，所產生的結構彎翹就越大。該因 之晶片與導線架，對晶片本身及後續製程皆會 響。 ] 主要目的係提供一種半導體封裝構造及其製造 並改善前述先前技術之問題。 明之半導體晶片封裝構造，其主要包含一導線 體晶片以及一封膠體。該導線架包含複數條内 條外引腳以及一晶片承座。該些内引腳界定一 一中央區域。該晶片承座設於該中央區域中。 片係設於該晶片承座上並且具有複數個晶片銲 pad)設於該半導體晶片之一正面（active1236107 V. Description of the invention (1) [The invention belongs to the present invention. [The prior art used a semiconducting process to adhere to a plurality of pin injection molding packages. Because the half encounters temperature chips and wires, the higher the temperature of the wafer, the higher the stress, the warpage will cause adverse effects. [Summary of the Invention The method to overcome According to the present invention, a half-lead pin, a plurality of horizontal planes, and the semiconductor wafer (the technical field of bond i ng) related to a semiconductor wafer package structure and its manufacturing cube-shaped chip package structure includes a chip by a silver glue through a solid A chip holder fixed to a lead frame. The lead frame still contains the chip. The chip is electrically connected to the pin 5 and then a semiconductor chip is packaged with a resin material. The difference in thermal expansion coefficient between the conductor chip and the lead frame is quite large due to rapid When changing (such as the aforementioned adhesive layer curing process), the frame will produce different expansion or contraction with temperature changes and warp with the structure of the lead frame; and the longer or longer the required structure, The larger the warpage. The chip and the lead frame will affect the chip itself and subsequent processes.] The purpose is to provide a semiconductor package structure and its manufacturing and improve the problems of the foregoing prior art. The semiconductor chip package structure of Ming mainly includes a lead body chip and a gel. The lead frame includes a plurality of inner and outer leads and a chip. The inner pins define a central area. The wafer holder is disposed in the central area. A wafer is provided on the wafer holder and has a plurality of wafer bonding pads) provided on a front surface of the semiconductor wafer. (Active
00710.ptd 第8頁 1236107 五、發明說明（2) surface)上。該半導體晶片之晶片焊塾係電性連接於該導 線架的該些内引腳。該封膠體（p a c k a g e b 〇 d y )包覆該導線 架之該些内腳部以及該半導體晶片。 本發明之特徵在於該晶片承座係低置（d 〇 w n s e t)於該封 膠體中以允許該半導體晶片的正面與該該水平面大致共平 面，並且該封膠體位於該水平面上方之封膠體厚度係大致 相同於該水平面下方之封膠體厚度。這種特徵使得該半導 體晶片封裝構造具有良好的平衡對稱性，可藉由此結構有 效改善在先前技術中半導體晶片封裝構造的變形彎翹 (warpage)問題 。 本發明另提供一種半導體晶片封裝構造的製造方法。首 先，製造一導線架。該導線架具有複數條引腳以及一晶片 承座（die pad)設於由該些内引腳界定之中央區域 (central region)中。該晶片承座係低置（downset)使得 該内引腳界定之水平面以及該晶片承座的表面之間具有一 深度。接著，將一半導體晶片貼於該晶片承座上。 應注意的是，為了使得該半導體晶片的正面與該内引腳 界定之水平面大致共平面，在製造該導線架時，可將該晶 片承座低置的深度製造成大致相同於該半導體晶片的厚 度。此外，也可以在導線架製造步驟之後以及半導體晶片 黏貼步驟之前，配合該導線架的晶片承座低置的深度，研 磨該半導體晶片的背面’使得該半導體晶片研磨後的厚度 與該晶片承座低置的深度大致相等。 然後，將該半導體晶片之晶片銲墊電性連接至該些内引00710.ptd Page 8 1236107 V. Description of the invention (2) surface). The wafer pads of the semiconductor wafer are electrically connected to the inner pins of the lead frame. The encapsulant (p a c k a g e b o d y) covers the inner legs of the lead frame and the semiconductor wafer. The invention is characterized in that the wafer holder is set in the sealing compound to allow the front side of the semiconductor wafer to be substantially coplanar with the horizontal plane, and the thickness of the sealing compound that the sealing compound is located above the horizontal plane is It is approximately the same as the thickness of the sealant under the horizontal plane. This feature makes the semiconductor chip package structure have a good balance symmetry, and can effectively improve the warpage problem of the semiconductor chip package structure in the prior art by this structure. The invention further provides a method for manufacturing a semiconductor chip package structure. First, a lead frame is manufactured. The lead frame has a plurality of pins and a die pad disposed in a central region defined by the inner pins. The wafer holder is downset so that there is a depth between the horizontal plane defined by the inner pins and the surface of the wafer holder. Next, a semiconductor wafer is attached to the wafer holder. It should be noted that, in order to make the front surface of the semiconductor wafer and the horizontal plane defined by the inner pins approximately coplanar, when manufacturing the lead frame, the depth of the wafer holder can be made substantially the same as that of the semiconductor wafer. thickness. In addition, after the lead frame manufacturing step and before the semiconductor wafer attaching step, the back surface of the semiconductor wafer can be ground with the low depth of the wafer holder of the lead frame, so that the thickness of the semiconductor wafer after grinding and the wafer holder can be polished. The lower depths are approximately equal. Then, the wafer pads of the semiconductor wafer are electrically connected to the internal leads.
00710.ptd 第9頁 1236107 五、發明說明（3) 腳。最後’封膠包覆（encapSUlate)該内引腳以及該半導 體晶片以形成一封膠體並使得該封膠體位於該水平面上方 之封膠體厚度係大致相同於該水平面下方之封膠體厚度。 【實施方式】 第1圖係為根據本發明一實施例之半導體晶片封裝構 造’其主要包含一導線架1 〇 〇、一半導體晶片丨丨0以及一封 膠體1 20。 該導線架1 0 0包含複數條引腳1 〇 2、一晶片承座1 〇 4以及 複數個連接肋條（未示於圖中）。該些引腳1〇2具有内引腳 1 0 2 a以及外引腳1 〇 2 b。該導線架1 0 0之該些内引腳1 〇 2 a界 疋一中央區域1 3 0以及一水平面，而該外引腳部1 〇 2 b係用 以電性連接至一外部電路。該晶片承座丨〇 4係設於該中央 區域1 3 0中，用以承載該半導體晶片1 1 〇。該連接肋條（未 示於圖中）係用以連接該晶片承座1 〇 4以及該導線架1 〇 〇。 該半導體晶片1 1 0包含一正面1 1 〇 a以及一背面1 1 〇 b。該 半導體晶片1 1 0係以其背面1 1 〇 b藉一黏著劑1 1 2黏著固定於 該導線架1 0 0之晶片承載件1 〇 4上，較佳地，該黏著劑1 1 2 係為銀膠。該半導體晶片2 0 2之正面1 1 〇 a具有複數個晶片 銲塾1 1 4利用複數條連接線（b ο n d i n g w i r e ) 1 1 6電性連接至 該導線架1 00之内引腳1 02a。 該半導體晶片1 1 〇、晶片承座1 0 4、導線架1 〇 〇之内引腳 1 0 2 a以及複數條連接線11 6係包覆於該封膠體1 2 0中。該封 膠體1 2 0係由絕緣材料例如環氧樹脂（e ρ ο X y )製成。該封膠 體1 2 0具有一上半部1 2 0 a位於該引腳1 0 2之内引腳1 〇 2 a所界00710.ptd Page 9 1236107 V. Description of the invention (3) Feet. Finally, the encapsulation covers the inner pin and the semiconductor wafer to form a colloid, and the thickness of the encapsulation gel above the horizontal plane is substantially the same as the thickness of the encapsulation gel below the horizontal plane. [Embodiment] FIG. 1 is a semiconductor wafer package structure according to an embodiment of the present invention, which mainly includes a lead frame 100, a semiconductor wafer 丨 0, and a colloid 120. The lead frame 100 includes a plurality of pins 102, a wafer holder 104, and a plurality of connecting ribs (not shown in the figure). These pins 102 have an inner pin 102a and an outer pin 102b. The inner pins 1 0 2 a of the lead frame 100 are a central region 1 30 and a horizontal plane, and the outer pin 1 2 b is used to be electrically connected to an external circuit. The wafer holder 04 is disposed in the central area 130, and is used to carry the semiconductor wafer 110. The connecting rib (not shown in the figure) is used to connect the wafer holder 104 and the lead frame 100. The semiconductor wafer 1 10 includes a front surface 1 10 a and a back surface 1 1 0 b. The semiconductor wafer 1 10 is adhered and fixed to the wafer carrier 1 104 of the lead frame 100 with an adhesive 1 12 on the back surface 1 1 0b. Preferably, the adhesive 1 1 2 is For silver glue. The front surface 1 1 0 a of the semiconductor wafer 202 has a plurality of wafers. The solder pads 1 1 4 are electrically connected to pins 102a within the lead frame 100 by using a plurality of connection wires (b o n d i n g w i r e) 1 1 6. The semiconductor wafer 110, the wafer holder 104, the lead frame 1002a, and the plurality of connecting wires 116 are coated in the sealing compound 120. The sealing compound 1 2 0 is made of an insulating material such as epoxy resin (e ρ ο X y). The sealing compound 1 2 0 has an upper half 1 2 0 a located within the pin 1 2 and bounded by the pin 1 2 a
00710.ptd 第10頁 1236107 五、發明說明（4) -- 疋之°亥水平面上以及一下半部1 2 0 b位於該引腳1 0 2之内引 腳1 0 2=所界定之該水平面之下。 本毛明之特徵在於該導線架1 0 0的晶片承座1 0 4係低置 d^J|Set)於該封膠體120中以允許該半導體晶片11〇的正 ，&與該引腳1〇2之内引腳丨〇2 &所界定之該水平面大致 、 政且該封膠體1 2 0的上半部1 2 0 a之厚度（d )係大致 H於該封膠體120的下半部12〇1)之厚度（d)(即是該封膠 、该水平面上方之封膠體1 2 0 a厚度係大致相同於 〜f平面下方之封膠體120b厚度）。 稱^種f彳ί使得該半導體晶片封裝構造具有良好的平衡對 Γ接、’可藉由此結構有效改善在先前技術中半導體晶片封 、^^的變形彎翹（w a r p a g e )問題。 昭發明另提供一種半導體晶片封裝構造的製造方法。參 二 圖’首先在步驟2 〇 2中，製造一導線架1 〇 〇。該導線 木 具有複數條引腳1 〇 2、一晶片承座1 〇 4設於由該引腳 的内_弓丨腳1 02a界定之該中央區域1 30以及複數個連接肋條 未^不於圖中）。該導線架構造1 0 0較佳係由銅、鐵、鎳或 :、a金製成。藉由一壓陷操作（depress 〇perai；i〇n)壓陷 該連接肋條使知其晶片承座1 〇 4係低置（d 〇 w n s e t)且與該引 腳102之内腳部1〇2&具有一高度差，也就是說將該晶片承 座1 〇 4低置至一深度。接著，在步驟2 〇 6中，將一半導體晶 片1 1 〇貼於該晶片承座1 〇 4上。 應注意的是’為了使得該半導體晶片丨丨〇的正面1丨0 a與 該引腳1 0 2之内引腳丨〇 2 a所界定之該水平面大致共平面，00710.ptd Page 10 1236107 V. Description of the invention (4)-°°° Horizontal plane and lower half 1 2 0 b is located within the pin 1 0 2 Pin 1 0 2 = the horizontal plane defined under. The feature of this Maoming is that the chip holder 100 of the lead frame 100 is a low-position d ^ J | Set) in the sealing compound 120 to allow the semiconductor wafer 110 to be positive, & and the pin 1 〇2 Within the pin 丨 〇2 & The horizontal plane defined by the & approximately, the upper part of the sealing gel 1 2 0 12 a thickness (d) is substantially H is lower than the sealing gel 120 The thickness (d) of the portion 1201) (that is, the thickness of the sealant and the sealant 120a above the horizontal plane is substantially the same as the thickness of the sealant 120b below the ~ f plane). It is said that the semiconductor chip package structure has a good balance. The structure can effectively improve the problem of warpage (wapar p age) of the semiconductor chip package in the prior art. Zhao invention also provides a method for manufacturing a semiconductor chip package structure. Referring to the second figure ', first, in step 202, a lead frame 100 is manufactured. The lead wire has a plurality of pins 102, and a wafer holder 104 is provided in the central region 1 30 and a plurality of connecting ribs, which are defined by the inner rim of the pin 1 02a, and a plurality of connecting ribs. in). The lead frame structure 100 is preferably made of copper, iron, nickel or:, a gold. By a depression operation (depress 〇perai; i〇n), the connection rib is depressed to make it known that the wafer holder 1 04 is low (d wnset) and is in contact with the inner leg portion 102 of the pin 102. Has a height difference, that is, the wafer holder 104 is lowered to a depth. Next, in step 2006, a semiconductor wafer 110 is attached to the wafer holder 104. It should be noted that, ′ In order to make the front surface 1 丨 0a of the semiconductor wafer 丨 丨 a and the horizontal plane defined by the pin 丨 〇2a within the pin 102, approximately coplanar,
00710.ptd 第11頁 1236107 五、發明說明（5) 在製造該導線架1 0 0時，可配合該半導體晶片1 1 0的正面 1 1 0 a與背面1 1 0 b之間的厚度將該晶片承座1 0 4低置的深度 製造成大致相同於該半導體晶片1 1 0的厚度。此外，也可 以在導線架製造步驟2 0 2之後以及半導體晶片黏貼步驟2 0 6 之前，另進行步驟2 0 4，即是配合該導線架1 0 0的晶片承座 1 0 4低置的深度，研磨該半導體晶片1 1 0的背面1 1 0 b，使得 該半導體晶片1 1 0研磨後的厚度與該晶片承座1 0 4低置的深 度大致相等。 然後，在步驟2 0 8中，以例如打線製程將該半導體晶片 1 1 0之晶片銲墊1 1 4電性連接至該引腳1 0 2的内引腳1 0 2 a。 最後，在步驟2 1 0中，利用習知的的技術，例如傳遞模 塑法（transfer molding)封膠包覆（encapsulate)該弓I 腳 1 0 2的内引腳1 0 2 a以及該半導體晶片1 1 0以形成一封膠體 1 2 0。更具體地說，傳遞模塑法（t r a n s f e r m ο 1 d i n g)係利 用一包含一上模以及一下模的模具進行封膠步驟。該上模 和下模分別具有彼此對應之凹槽，當該上模下模密合夾緊 時，其凹槽會共同形成一模穴。此外，該模具設有一罐 (ρ 〇 t)供封膠材料置放。該罐係經由一洗道（r u η n e r )以及 一洗道口（gate)連接該模穴（cavity)。該封膠步驟可包 含，將設有該半導體晶片的導線架置入該模具中，然後將 模具密合夾緊後，一壓注頭開始移動向上壓縮該罐中的封 膠材料，使其經由澆道以及澆道口而充滿模穴藉此形成該 封膠體1 2 0。應注意的是，由於該上模以及下模的凹槽的 深度大致一致可使得該封膠體1 2 0的上半部1 2 0 a之厚度係00710.ptd Page 11 1236107 V. Description of the invention (5) When manufacturing the lead frame 100, the thickness between the front surface 1 1 0 a and the back surface 1 1 0 b of the semiconductor wafer 1 1 0 The wafer holder 104 is manufactured at a low depth to be approximately the same as the thickness of the semiconductor wafer 110. In addition, after the lead frame manufacturing step 202 and before the semiconductor wafer sticking step 2 06, another step 2 0 4 can be performed, that is, the chip holder 1 0 4 of the lead frame 1 0 0 has a low depth. , Grinding the back surface 110 b of the semiconductor wafer 110, so that the thickness of the semiconductor wafer 110 after grinding is approximately equal to the depth at which the wafer holder 104 is lowered. Then, in step 208, the wafer pad 1 1 4 of the semiconductor wafer 110 is electrically connected to the inner pin 102 of the pin 102 by a wire bonding process. Finally, in step 2 10, a conventional technique is used, such as transfer molding to encapsulate the bow I 102 internal pin 1 0 2 a of the bow I 102 and the semiconductor. The wafer 1 1 0 forms a colloid 1 2 0. More specifically, the transfer molding method (t r a n s f e r m ο 1 d i n g) uses a mold including an upper mold and a lower mold to perform the sealing step. The upper mold and the lower mold respectively have grooves corresponding to each other. When the upper mold and the lower mold are tightly clamped, the grooves together form a cavity. In addition, the mold is provided with a pot (ρ 〇 t) for placing the sealant material. The tank is connected to the cavity via a washing channel (ru n n er) and a washing channel gate. The sealing step may include placing a lead frame provided with the semiconductor wafer into the mold, and then tightly clamping the mold, and an injection head begins to move upward to compress the sealing material in the can to pass it through. The gate and the gate of the gate are filled with mold cavities to form the sealing compound 1 2 0. It should be noted that, because the depths of the grooves of the upper mold and the lower mold are substantially the same, the thickness of the upper half 1 2 0 a of the sealing compound 1 2 0 is
00710.ptd 第12頁 1236107 五、發明說明（6) 大致相同於該封膝體的下半部12〇b之厚度。00710.ptd Page 12 1236107 V. Description of the invention (6) The thickness is approximately the same as the thickness of the lower half of the knee body 12Ob.
本發明所提供之新穎導線架可適用於薄小輪廓封裝構造 (thin small outline package，TSOP)、四邊扁平封裝構 造（quad flat package，QFP)、具有散熱片之四邊扁平封 裝構造（quad flat package with heatsink ’HSQFP)、小· 輪廓封裝構造（sinaH outline Package ’SOP)、小輪廓J 形腳封裝構造（sma11 outline J—leaded package ’S0J) 或是塑膠塑膠雙排列封裝構造（Plastic dual inline package ， P-DIP)等。 雖然本發明已以前述較佳實施例揭示，然其並非用以限 定本發明，任何熟習此技藝者，在不脫離本發明之精神和參 範圍内，當町作各種之更動與修改。因此本發明之保護範 圍當視後附之申請專利範圍所界定者為準。The novel lead frame provided by the present invention can be applied to thin small outline package (TSOP), quad flat package (QFP), quad flat package with heat sink heatsink 'HSQFP), small outline package structure (sinaH outline Package' SOP), small outline J-shaped package structure (sma11 outline J-leaded package 'S0J), or plastic dual inline package structure (Plastic dual inline package, P -DIP) and so on. Although the present invention has been disclosed in the aforementioned preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application.
00710.ptd 第13頁 1236107 圖式簡單說明 【圖式簡單說明】 為了讓本發明之上述和其他目的、特徵、和優點能更明 顯特徵，下文特舉本發明較佳實施例，並配合所附圖示， 作詳細說明如下。 第1圖：根據本發明一實施例之半導體晶片封裝構造之 剖視圖，以及 第2圖··根據本發明一實施例之半導體晶片封裝構造之 製造方法的主要步驟。 圖號說明： 100 導 線 架 102 引 腳 102a 内 腳 部 102b 内 腳 部 104 晶 片 承 座 106 連 接 肋 條 110 半 導 體 晶 片 110a 正 面 1 10b 背 面 112 黏 著 劑 1 14 晶 片 焊 墊 116 連 接 線 120 封 膠 體 120a 上 半 部 120b 下 半 部 130 中 央 區 域 202 製 造 導 線 架 2 0 4 研磨半導體晶片 2 0 6 黏貼半導體晶片 2 0 8 打線 210 封膠00710.ptd Page 13 1236107 Brief description of the drawings [Simplified description of the drawings] In order to make the above and other objects, features, and advantages of the present invention more obvious, the following describes the preferred embodiments of the present invention with the accompanying The figure is described in detail below. Fig. 1: A cross-sectional view of a semiconductor wafer package structure according to an embodiment of the present invention, and Fig. 2 · The main steps of a manufacturing method of a semiconductor wafer package structure according to an embodiment of the present invention. Description of drawing number: 100 lead frame 102 pin 102a inner leg portion 102b inner leg portion 104 chip holder 106 connection rib 110 semiconductor wafer 110a front side 1 10b back side 112 adhesive 1 14 wafer pad 116 connection line 120 sealing body 120a upper half Part 120b Lower half 130 Central area 202 Manufacture of lead frame 2 0 4 Polished semiconductor wafer 2 0 6 Bonded semiconductor wafer 2 0 8 Wire bonding 210 Sealant
0.0710.ptd 第14頁0.0710.ptd Page 14
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