TWI236123B - Semiconductor package with lead frame - Google Patents
Semiconductor package with lead frame Download PDFInfo
- Publication number
- TWI236123B TWI236123B TW092109030A TW92109030A TWI236123B TW I236123 B TWI236123 B TW I236123B TW 092109030 A TW092109030 A TW 092109030A TW 92109030 A TW92109030 A TW 92109030A TW I236123 B TWI236123 B TW I236123B
- Authority
- TW
- Taiwan
- Prior art keywords
- lead frame
- wafer
- semiconductor package
- connecting section
- mold
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
- H01L24/743—Apparatus for manufacturing layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29005—Structure
- H01L2224/29007—Layer connector smaller than the underlying bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3201—Structure
- H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
- H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/741—Apparatus for manufacturing means for bonding, e.g. connectors
- H01L2224/743—Apparatus for manufacturing layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
1236123 五、發明說明（1) 【發明所屬之技術領域】： 本舍明關於一種半導體封裝件，尤指一種具有導線架 (Lead Frame)，並以該導線架之晶片座（])i e pad)承 載半體晶片之半導體封裝件（Semic〇nduct〇r package )° 【先前技術】： 傳統導線架（Lead Frame)型態之半導體封裝件，如 四方扁平式半導體封裝件（Quad Flat Package， QFP)或 四方扁平無導腳式（Quad Flat Non-leaded，QFN)半導 體^寸裝件等’其製作方式均在一具晶片座及多數導腳之g 線条上母占接一半導體晶片（Semic〇nduct〇r Die)，復藉 複數條金線電性連接晶片表面上各晶片銲墊（Electrode Pads)至對應導腳，再以一封裝膠體包覆該半導體晶片及 金線而_形成一半導體封裝件。 然而’晶片與晶片座間因構成材質不同，兩者的熱膨 脹係數（Coefficient of Thermal Expansion，CTE)差 兴極大’故卩过者晶片尺寸變大，晶片接觸晶片座的面積也 會增加，使晶片在信賴性測試及後續製程之溫度循環 (Temperature Cycle)下，受到來自晶片座之熱應力效^ 度（Thermal Stress Effect)而導致脫層 (Delamination)或晶片碎裂（Die Crack)等不良情況 產生。 為解決上述問題，美國專利第5，3 7 8，6 5 6號案 n Leadframe, Semi conductor Integrated Circuit1236123 V. Description of the invention (1) [Technical field to which the invention belongs]: The present invention relates to a semiconductor package, in particular, a lead frame with a lead frame, and a pad (]) ie pad) Semi-semiconductor package (semiconductor package) ° [Prior technology]: Traditional lead frame type semiconductor packages, such as Quad Flat Package (QFP) Or Quad Flat Non-leaded (QFN) semiconductor ^ -inch packages, etc., 'The manufacturing methods are all in a wafer holder and the g-line of most of the guide pins to a semiconductor chip (Semic. nduct〇r Die), borrow a plurality of gold wires to electrically connect each of the wafer pads (Electrode Pads) on the surface of the wafer to the corresponding guide pins, and then cover the semiconductor wafer and gold wires with a packaging gel to form a semiconductor package Pieces. However, 'the coefficient of thermal expansion (CTE) between the wafer and the wafer holder is very different because of the different materials'. Therefore, the size of the wafer will increase, and the area of the wafer contacting the wafer holder will also increase, making the wafer Under the reliability test and the temperature cycle of the subsequent process, the thermal stress effect from the wafer holder (Thermal Stress Effect) causes delamination or die crack and other adverse conditions. To solve the above problems, US Patent No. 5, 3 7 8, 6 5 6 n Leadframe, Semi conductor Integrated Circuit
17209石夕品.ptd 第8頁 1236123 五、發明說明（2)17209 Shi Xipin.ptd Page 8 1236123 V. Description of the Invention (2)
Device Using the Same, and Method of and Process F〇r F a b r i c a t i n g t h e S a m e ”揭露一種將晶片承座部位之 大小設計成小於晶片尺寸2 3 0之導線架2 0，如第7圖所示。 該導線架2 0包含一提供半導體晶片（未圖示）接置之晶片 座2 1以及導腳2 2，為防止晶片（未圖示）與晶片座2 1之間 的因接觸面積過大造成脫層，該晶片座2 1將與晶片接合之 承座部2 1 0縮小（至少小於晶片尺寸2 3 0)，並藉由增長的 繫條211 ( Tie Bar)輔助該承座部210支撐，以使晶片座 2 1得連接至該導線架2 0上。 惟此方法，於實際生產上，用於固接該晶片至承座部上 之銀膠（Si lver Paste)塗佈量必須非常精準，若銀膠塗 佈量不足致使晶片與晶片座間留有間隙時，銀膠層間隙太 小（此間隙通常為1密爾）將導致封裝樹脂無法（封裝樹 脂的填料粒徑一般為2密爾）填滿而造成氣洞（V 〇 i d s); 又晶片座上塗佈的銀膠量如果過多時’晶片壓接到晶片座 上以後，多餘銀膠會溢流至晶片座周圍甚至背面，如此亦 會使得封裝膠體與銀膠間有脫層產生。 再者，如第8圖所糸，上述發明將晶片座2 1承座部分 縮小，並藉由增長的繫條2 1 1來協助承座部2 1 0分攤晶片重^ 量時，很難控制該承座部2 1 0與繫條2 1 1於同一平面，晶片 平面度（P 1 a n a r i t y)的控制力不足，往往導致晶片黏接 到晶片座上以後無法具備良好的平面度而影響到後續製程 的信賴性。此外，如第9圖所示，若以增長的繫條2 1 1來協 助承座部2 1 0分攤晶片重量時，相較於傳統晶片座（如第8"Device Using the Same, and Method of and Process F0bricating the Same" discloses a leadframe 20, which is designed to have a chip holder portion smaller than the chip size 230, as shown in Figure 7. The lead The rack 20 includes a wafer holder 21 and a guide pin 22 for providing a semiconductor wafer (not shown). To prevent delamination due to a large contact area between the wafer (not shown) and the wafer holder 21, The wafer holder 21 shrinks the holder portion 2 10 which is bonded to the wafer (at least smaller than the wafer size 2 3 0), and assists the holder portion 210 with a growing tie bar 211 (Tie Bar) to support the wafer. The base 21 must be connected to the lead frame 20. However, in actual production, the coating amount of silver paste (Silver Paste) used to fix the wafer to the base must be very accurate. Insufficient glue coating results in a gap between the wafer and the wafer holder, the gap between the silver glue layer is too small (this gap is usually 1 mil) will cause the encapsulation resin cannot be filled (the filler particle diameter of the encapsulation resin is generally 2 mils). And cause air holes (V 〇ids); If the amount of silver glue is too large, after the wafer is crimped to the wafer holder, the excess silver glue will overflow to the periphery of the wafer holder and even to the back, which will also cause delamination between the packaging gel and the silver glue. As shown in FIG. 8, the above-mentioned invention reduces the size of the wafer holder 2 1 and assists the holder 2 2 with the increased tie 2 1 1. It is difficult to control the holder 2 when sharing the weight of the wafer 2. 1 0 and tie bar 2 1 1 are on the same plane, the control of wafer flatness (P 1 anarity) is insufficient, which often causes the wafer to fail to have good flatness after being bonded to the wafer holder, which affects the reliability of subsequent processes. In addition, as shown in FIG. 9, if the increasing tie bar 2 1 1 is used to assist the seat portion 2 10 to share the wafer weight, compared with the conventional wafer seat (such as
17209矽品.ptd 第9頁 1236123 五、發明說明（3) ^^- 圖晶片2 3外之虛線2 1 0 ’表示），由於繫條2 1 1太長導致剛 性（R i g 1 d 11 y)欠佳，使得此種承座部2 1 0面積小於晶片 2 3之晶片座21進行模壓製程（Molding)時，易受模流衝 擊而導致承座部210移位（Shift)、浮動（Floating)， 或金線25外露（Wire Exposed)、斷裂等問題，而導致半 導體封裝件良率降低。 此外，第 5，623，12 3號美國專利’’861111(：〇]1(111(：1:〇1' Device Package with Small Die Pad and Method of Making Samen另提出一種可控制銀膠塗佈量，並且杜絕晶 片 . 與晶片座之間發生脫層之導線架。此種導線架之晶片座之 承座部面積亦小於晶片尺寸，並藉由增長的繫條協助該承 座部共同支撐晶片；如第1 〇圖及第11圖所示，該晶片座3 1 之承座·部3 1 0上開設有至少一凹部3 1 0 a，藉以容納多餘銀 膠3 4並且增加半導體晶片3 3與晶片座3 1間隙之高度，以免 銀膠3 4溢流至背面，並且減少脫層或氣洞發生。惟此方法 即便可以解決溢膠或脫層的問題，但以繫條3 1 1協助支撐 小尺寸承座部3 1 0其結構強度不足，仍然無法克服承座部 3 1 0移位或浮動的問題。 鑑於上述問題，研發出一種得避免晶片與晶片座接觸 面脫層、防止晶片座背面溢膠，並且能防止晶片座移位之 V線架式半導體封裝件（Lead Frame Based Semiconductor Package)實為急切之務。 【内容】：17209 硅 品 .ptd Page 9 1236123 V. Description of the invention (3) ^^-Figure 2 shows the dashed line outside 2 3 indicated by 2 1 0 '), because the tie bar 2 1 1 is too long resulting in rigidity (R ig 1 d 11 y ) Poor, such that when the mounting area of such a mounting portion 2 10 is smaller than that of the wafer 2 3 and the molding process (Molding), the mounting portion 210 is susceptible to the impact of the mold flow, causing the mounting portion 210 to shift (Floating) and floating (Floating). ), Or problems such as wire exposure and breakage of the gold wire 25, resulting in a decrease in the yield of the semiconductor package. In addition, U.S. Patent No. 5,623,123, `` 861111 (: 〇) 1 (111 (: 1: 1) Device Package with Small Die Pad and Method of Making Samen, has proposed another method to control the amount of silver glue coating And to prevent the wafer. Delamination between the lead frame and the lead frame. The lead frame of the lead frame has a smaller base area than the wafer size, and the increased tie bar assists the base to support the wafer together; As shown in FIG. 10 and FIG. 11, at least one recess 3 1 0 a is provided on the holder and part 3 1 0 of the wafer holder 3 1 to accommodate excess silver glue 3 4 and increase the semiconductor wafer 3 3 and The height of the gap of the wafer holder 31 to prevent the silver glue 34 from overflowing to the back and reduce the occurrence of delamination or air holes. However, even if this method can solve the problem of glue overflow or delamination, it is supported by a tie bar 3 1 1 Due to the insufficient structural strength of the small-sized pedestal portion 3 10, the problem of displacement or floating of the pedestal portion 3 10 still cannot be overcome. In view of the above-mentioned problems, a kind of contact surface between the wafer and the wafer holder to avoid delamination and prevent the wafer holder from being developed is developed. V wire rack with overflow on the back and preventing chip holder from shifting The semiconductor package (Lead Frame Based Semiconductor Package) actually works eagerness] SUMMARY:
17209石夕品.ptd 第10頁 123612317209 Shi Xipin.ptd Page 10 1236123
第11頁 五 、發明說明 (4) 本 發 明 之 主 要 目 的 即 在 提 供一 種利於 模 流 穿 越， 防 止 半 導 體 晶 片 與 晶 片 座 之 間 形 成 氣洞 ，並且 降 低 晶 片座 對 於 晶 片 的 軌 應 力 效 應 之 導 線 架 式 半導 體封裝 件 〇 本 發 明 之 另 一 § 的 在 於 提 供一 種可防 止 黏 接 晶片 之 膠 黏 劑 溢 流 至 晶 片 座 背 面 ， 並 且 降低 晶片座 對 於 晶 片的 粒 應 力 效 應 之 導 線 架 式 半 導 體 封 裝 件。 本 發 明 之 再 一 a 的 在 於 提 供一 種可避 免 晶 片 座於 模 壓 過 程 中 移 位 ( Shi ] ft) 或浮動 (Floating) ，俾減少金線 外 路 或 斷 裂 並 且 提 晶 片 封 裝良 率之導 線 架 式 半導 體 封 裝 件 〇 本 發 明 之 又 一 的 在 於 提 供一 種使晶 片 座 與 封裝 膠 體 接 合 介 面 不 致 因 為 孰 應 力 引 發 脫層 之導線 架 式 半 導體 封 裝 件 0 為f 達 成 上 揭 及 其 他 a 的 > 本發 明揭露 — 種 晶 片承 座 部 分 小 於 半 導 體 晶 片 之 導 線 架 式 半導 體封裝 件 ( Le )ad F 'rame Based Semi l conductor Package) c 1該導線架式半導體封 裝 件 包 括 有 一 導 線 架 其 具 有 至少 一晶片 座 及 多 數導 腳 y 至 少 一 接 置 於 該 導 線 架 上 之 半 導體 晶片 ， 一 提 供 晶片 與 導 線 架 黏 接 之 膠 黏 層 y 多 數 電 性 連接 晶片至 導 腳 之 金線 j 以 及 包 覆 該 晶 片 及 金 線 之 封 裝 膠 體。 惟 本 發 明 之 特 點 在 於 該 晶片 座係由 至 少 — 用於 承 接 晶 片 且 面 積 小 於 晶 片 尺 寸 之 承 座部 ，一體 成 型 於 該承 座 部 外 圍 並 且 向 下 凹 陷 之 階 梯 部 > 以及 複數條 將 該 階 梯部 一 體 連 接 至 導 線 架 上 之 支 撐 條 ( Suppor ting Bar 0 所 構成 其 17209石夕品.ptd . 1236123 丨五、發明說明（6) j |之兀件數量、種類以及佈局型態將更為複雜。 如第1圖所示’本發明係揭露一種承座部小於半導體 晶片之導線架式半導體封裝件1 ( Lead Frame Based Seim conductor Package)。該半導體封裝件丨包括有一導 線架1 0，其具有至少一晶片座丨丨及多數導腳（未圖示）； 至少一接置於該導線架1 0上之半導體晶片1 3 ; 一提供晶片 1 3與導線架1 〇黏接之膠黏層1 4 ;多數電性連接半導體晶片 1 3至導腳（未圖不）之金線i 5 ;以及包覆該晶片丨3及金線 I 5之封裝膠體1 6。 如第2圖及第3圖所示，該導線架1 〇係由銅、銅合金g 金屬材質製成，每一導線架10具有至少一晶片座u以及環 設於該晶片座1 1周圍之多數導腳丨2，且該晶片座J i包含有 至少一用以承接晶片且面積小於該晶片尺寸i 3 0之承座部 II 〇 ’ 一體成型於該承座部110外圍並且向下凹陷之階梯部 111/以及複數條將该階梯部111一體連接至導線架1 〇上之 支撐條112 ( Supporting Bar);其中，該承座部11〇與階 梯j 1 1 1間形成一大於封裝樹脂最大填料粒徑（約2密爾） 之高度差di。運用習知沖壓技術（Punch) 一體形成該承 座部110、階梯部111以及支撐條112，可藉由各支撐條112 撐設該承座部1 1 〇以及階梯部u丨共同分攤晶片重量。 惟連接該階梯部1 1 1之支撐條1丨2 ’係由彼此一體成型 並且各具有不同平面高度之第一連接段U2a及第二連接段 1 1 2 b所構成，如第5圖所示，該第一連接段n 2 a係用於連 接該階梯部Π 1以及第二連接段n 2 b，且各第一連接段Page 11 V. Description of the invention (4) The main purpose of the present invention is to provide a lead frame type that facilitates mold flow through, prevents the formation of air holes between the semiconductor wafer and the wafer holder, and reduces the rail stress effect of the wafer holder on the wafer. Semiconductor package. Another aspect of the present invention is to provide a leadframe-type semiconductor package that can prevent the adhesive to the wafer from overflowing to the back surface of the wafer holder, and reduce the grain stress effect of the wafer holder on the wafer. Another aspect of the present invention is to provide a leadframe semiconductor which can prevent the wafer holder from being displaced (Shi) ft or floating during the molding process, reduce the external path or break of the gold wire, and improve the yield of the chip package. Package 〇 Another aspect of the present invention is to provide a leadframe semiconductor package that prevents the delamination due to rubbing stress caused by the bonding interface between the chip holder and the packaging colloid. A lead frame type semiconductor package (Le) ad F'rame Based Semi l conductor Package having a chip holder portion smaller than a semiconductor wafer c 1 The lead frame type semiconductor package includes a lead frame having at least one wafer base and a plurality of conductors. At least one of the pins y is connected to a semiconductor chip placed on the lead frame, and an adhesive layer y is provided to bond the chip to the lead frame. Most of the pins are electrically connected to the chip. The gold wire j of the foot and the sealing gel covering the wafer and the gold wire. However, the present invention is characterized in that the wafer holder is composed of at least—a holder portion for receiving a wafer and having an area smaller than the size of the wafer, integrally formed on the periphery of the holder portion and a recessed step portion> and a plurality of steps It is integrated with the support bar on the lead frame (Suppor ting Bar 0 and its 17209 Shi Xipin. Ptd. 1236123 丨 V. Description of the invention (6) The number, type and layout of j | As shown in FIG. 1 'The present invention discloses a Lead Frame Based Seim conductor Package 1 having a socket smaller than a semiconductor wafer. The semiconductor package includes a lead frame 10 having At least one chip holder 丨 丨 and a plurality of guide pins (not shown); at least one semiconductor wafer 13 connected to the lead frame 10; one providing an adhesive layer 1 for bonding the chip 13 to the lead frame 10 4; most of the gold wires i 5 electrically connecting the semiconductor chip 13 to the lead pins (not shown); and the encapsulation glue covering the chip 3 and the gold wire I 5 16. As shown in FIG. 2 and FIG. 3, the lead frame 10 is made of copper and copper alloy g. Each lead frame 10 has at least one wafer holder u and is ring-shaped on the wafer holder 1 Most of the guide pins 1 around 2 and the wafer holder J i includes at least one seat portion II ′ 0 for receiving a wafer and having an area smaller than the wafer size i 3 0. It is integrally formed on the periphery of the seat portion 110 and toward The recessed step portion 111 / and a plurality of the step portion 111 are integrally connected to the support bar 112 (Supporting Bar) on the lead frame 10; wherein the seat portion 11 and the step j 1 1 1 form a greater than The height difference di of the maximum filler particle size (about 2 mils) of the sealing resin. The seat 110, the step 111, and the support bar 112 are integrally formed using a conventional punching technique, and can be supported by each support bar 112 The bearing portion 1 1 0 and the step portion u 丨 share the weight of the wafer. However, the support bars 1 丨 2 'connecting the step portion 1 1 1 are integrally formed with each other and each of the first connecting sections U2a and The second connecting section 1 1 2 b is formed, as shown in FIG. 5, the first connecting section N 2 a line segment for connecting the step portion and a second connection segment Π 1 n 2 b, and each first connecting segment
17209矽品.ptd 第13頁 1236123 五、發明說明（8) 片式模具17包含有一上模170( Upper Mold)及一相對之 下模171 ( Bottom Mold)，且該上、下模170, 171内各形 成有一可供導線架及其他元件容置之模穴172( Mold C a v 11 y);以本發明為例，當導線架置入下模1 7 1模穴1 7 2 後，該第二連接段1 1 2b背面與該第一連接段}丨2a底緣間形 成之間隔距離Η係略大於該下模1 7丨模穴1 7 2之高度h ;以如 第6圖所示，待上模1 7 〇及下模1 7丨夹合後，曲折型態之第 一連接段112a底緣可完全觸抵於下模ι71模穴ι72底面[， 而提供一彈性力（F 1 exi bi 1 i ty)固定承座部1 1 0位置，以 免该承座部1 L0受模流衝擊而出現移位（Sh i f t)、浮動1 (Floating)而造成金線外露（wire Exposed)或斷裂等 情形。 、 以上所述僅為本發明之較佳實施例而已，並非用以限 制本舍.明之声、貝技術内容範圍。本發明之實質技術内容苑 圍係廣義地定義於下述之申請專利範圍中。任何他人所完 成之技術實體或方法，若是與下述之申請專利範圍所定$ 者為完全相同，或是為一種等效之變更，均將被視為涵: 於此專利範圍之中。 117209 硅 品 .ptd Page 13 1236123 V. Description of the invention (8) The chip mold 17 includes an upper mold 170 (Upper Mold) and a lower mold 171 (Bottom Mold), and the upper and lower molds 170, 171 A mold cavity 172 (Mold C av 11 y) can be formed in each of them to accommodate the lead frame and other components. Taking the present invention as an example, when the lead frame is placed in the lower mold 17 1 mold cavity 1 7 2, the first The distance between the back surface of the two connection sections 1 1 2b and the bottom edge of the first connection section 2a 2a is slightly larger than the height h of the lower mold 17 7 mold cavity 1 7 2; as shown in FIG. 6, After the upper mold 170 and the lower mold 17 are clamped, the bottom edge of the zigzag first connecting section 112a can completely touch the bottom surface of the lower mold ι71 and the cavity 72, and provide an elastic force (F 1 exi bi 1 i ty) Fix the position of the socket 1 1 0 to prevent the socket 1 L0 from being shuffled or floating due to the impact of the mold flow, causing the wire to be exposed or broken. And so on. The above descriptions are merely preferred embodiments of the present invention, and are not intended to limit the scope of the technical content of the sound of this house. The essential technical content of the present invention is broadly defined in the scope of the following patent applications. Any technical entity or method completed by others, if it is exactly the same as the one set out in the following patent application scope, or an equivalent change, will be deemed to be within the scope of this patent. 1
1236123 I圖式簡單說明 【圖式fa纟單說明】 弟1圖係本發明之導線架式半導體封裝件之剖面不意 圖； 第2圖係本發明之導線架式半導體封裝件所採用之導 線架之上視不意圖， 第3圖係本發明之導線架式半導體封裝件上該導線架 實施佈膠時之立體示意圖； 第4圖係本發明之導線架式半導體封裝件實施上片作 業前後之剖面示意圖； 1 第5圖係本發明之導線架式半導體封裝件進行模壓製 程時之局部剖面示意圖； 第6圖係本發明之導線架式半導體封裝件於模壓合模 後，該導線架觸抵模穴前後之剖面示意圖； 第，7圖係美國專利第5，3 7 8，6 5 6號之半導體封裝件所採 用之導線架之上視示意圖； 第8圖係第7圖所示之半導體封裝件完成上片後之上視 透視圖， 第9圖係第7圖所示之半導體封裝件受到模流衝擊後之 晶片座剖面示意圖； 第1 0圖係美國專利第5，6 2 3，1 2 3號之半導體封裝件所 採用之導線架之局部立體示意圖；以及 第1 1圖係第1 0圖所示之半導體封裝件完成上片後之局 部剖面示意圖。1236123 I Schematic description [Schematic fa 纟 single note] Figure 1 is a cross-sectional view of the lead frame semiconductor package of the present invention is not intended; Figure 2 is a lead frame used in the lead frame semiconductor package of the present invention It is not intended to be viewed from above. FIG. 3 is a schematic perspective view of the lead frame semiconductor package of the present invention when the lead frame is glued. FIG. 4 is a view of the lead frame type semiconductor package of the present invention before and after the film loading operation is performed. Sectional schematic diagram; 1 FIG. 5 is a partial cross-sectional schematic diagram of the lead frame semiconductor package of the present invention during the molding process; FIG. 6 is a lead frame semiconductor package of the present invention after the mold is pressed, the lead frame touches A schematic cross-sectional view of the front and back of the mold cavity; Figure 7 is a top schematic view of a lead frame used in the semiconductor package of US Patent No. 5, 3 7 8, 6 5 6; Figure 8 is a semiconductor shown in Figure 7 Figure 9 is a top perspective view of the package after the wafer is loaded. Figure 9 is a schematic cross-sectional view of the wafer holder after the semiconductor package shown in Figure 7 is subjected to a mold flow impact. Figure 10 is US Patent No. 5, 6 2 3, 1 2 3 A partial perspective view of the lead frame used in the semiconductor package; FIG. 11, and the first line of FIG. 10 after the semiconductor package is completed topsheet partial cross-sectional view of FIG.
17209矽品.ptd . 第16頁 123612317209 Silicone.ptd. Page 16 1236123
17209 矽品.ptd 第17頁17209 Silicone.ptd Page 17
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW092109030A TWI236123B (en) | 2003-04-18 | 2003-04-18 | Semiconductor package with lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW092109030A TWI236123B (en) | 2003-04-18 | 2003-04-18 | Semiconductor package with lead frame |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200423362A TW200423362A (en) | 2004-11-01 |
| TWI236123B true TWI236123B (en) | 2005-07-11 |
Family
ID=36648965
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW092109030A TWI236123B (en) | 2003-04-18 | 2003-04-18 | Semiconductor package with lead frame |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI236123B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI490960B (en) * | 2012-01-17 | 2015-07-01 | Chipmos Technologies Inc | Semiconductor package structure and manufacturing method thereof |
-
2003
- 2003-04-18 TW TW092109030A patent/TWI236123B/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| TW200423362A (en) | 2004-11-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8836101B2 (en) | Multi-chip semiconductor packages and assembly thereof | |
| KR101031394B1 (en) | Optical sensor package | |
| JP3205235B2 (en) | Lead frame, resin-encapsulated semiconductor device, method of manufacturing the same, and mold for manufacturing semiconductor device used in the manufacturing method | |
| KR101665721B1 (en) | Resin-sealed semiconductor device and manufacturing method thereof | |
| JP5479247B2 (en) | Manufacturing method of semiconductor device | |
| JP2006516812A (en) | Partially patterned leadframe and method of making and using it in semiconductor packaging | |
| TW200416992A (en) | Semiconductor device and the manufacturing method of the same | |
| JP2014220439A (en) | Method of manufacturing semiconductor device and semiconductor device | |
| CN107017174A (en) | Semiconductor device and its manufacture method | |
| JP2001274316A (en) | Semiconductor device and its manufacturing method | |
| TWI716532B (en) | Resin-encapsulated semiconductor device | |
| US6590279B1 (en) | Dual-chip integrated circuit package and method of manufacturing the same | |
| US20060091516A1 (en) | Flexible leaded stacked semiconductor package | |
| JP2008117875A (en) | Semiconductor device and method of manufacturing the same | |
| TWI237363B (en) | Semiconductor package | |
| TWI236123B (en) | Semiconductor package with lead frame | |
| JP3226244B2 (en) | Resin-sealed semiconductor device | |
| JP4050199B2 (en) | Lead frame, resin-encapsulated semiconductor device using the same, and manufacturing method thereof | |
| US20080038872A1 (en) | Method of manufacturing semiconductor device | |
| JP2005311099A (en) | Semiconductor device and its manufacturing method | |
| JP2001177007A (en) | Semiconductor device and manufacturing method thereof | |
| US20240203834A1 (en) | Method of producing electronic components, corresponding electronic component | |
| TWI248184B (en) | High frequency semiconductor device, method for fabricating the same and lead frame thereof | |
| TWI255533B (en) | Semiconductor package with lead frame for preventing delamination and dissipating heat | |
| JPH08279575A (en) | Semiconductor package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |