TWI242860B - Semiconductor package with heat dissipating structure - Google Patents

Abstract

A semiconductor package with heat dissipating structure is provided, wherein the second surface of a chip is adhered to a chip carrier, and the first surface opposite the second surface of the chip is attached to a heat dissipating structure by a thermal adhesion, so as to allow the heat generated from the chip to transfer to the heat dissipating structure. The heat dissipating structure has a lower surface toward the chip, an upper surface opposite the lower surface and a connecting portion extended from the lower surface. A surface of the connecting portion toward the chip is formed with a couple of projecting portions to form a point-contact relationship between the heat dissipating structure and the chip. The projecting portions prevent the heat dissipating structure from being dislocated or tilted due to warpage of the chip carrier and the chip. Therefore, this allows the yield of the semiconductor package to improved.

Description

1242860 V. Description of the invention (1) 丨 [Technical field to which the invention belongs] I The present invention relates to a semiconductor package with a heat sink, and more specifically, it relates to a method in which a chip and a heat sink are adhered in a point contact manner. Connected Half | Conductor Package. < j [prior art]! As electronic component processing speeds become faster and smaller in size, the demand for heat dissipation is also increasing. Failure to provide an effective heat dissipation mechanism will affect the performance and reliability of the electronic component and even shorten its life. Therefore, how to effectively dissipate the heat generated by the semiconductor wafer in use to ensure the service life and quality of the semiconductor package covered with the semiconductor wafer has always been a major issue in the semiconductor packaging industry. In response, US Patent No. 5, 2 1 6, 2 78 proposes a semiconductor package as shown in FIG. I (A). The conventional semiconductor package 1 is a heat spreader n (Heat spreader 0, = the top surface of the heat sink 11) exposed on the semiconductor wafer 10, and a packaging gel for covering the wafer is exposed. 1 2. Since the chip 丨 〇 is directly bonded to the heat sink 丨 丨 and the top surface 1 1 0 of the heat sink 丨 is exposed to the packaging gel i 2 and directly in contact with the atmosphere, the heat generated by the chip j 〇 is placed directly Passed to the heat sink 丨 丨 to escape to the atmosphere, the basin heat dissipation path does not need to pass through the packaging gel 12, so that this kind of semiconductor package 1 has good heat dissipation efficiency. This kind of semiconductor package 1 is manufactured before one The wafer i is bonded to the wafer i at a predetermined position on the upper surface 1 30 of the substrate 3 with adhesive 4; then, a wire bonding process is performed to solder most of the gold wires 15 to the wafer 10 and On the upper surface of the substrate 13, the wafer is electrically connected.

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Page 7 1242860 V. Description of the invention (2) Connected to the substrate 13; After the wafer 10 is electrically connected to the substrate, the heat sink 11 is bonded to the wafer 10 with an adhesive 16 Then, a molding process is performed so that the heat dissipation member is completely covered with the encapsulating resin forming the encapsulating colloid, and then a grinding process is performed to grind the solidified packaging resin above the heat dissipation member, such as a grinding stone, until the heat dissipation. The upper surface Π 0 of the component 1 1 exposes the encapsulant 12. The disadvantage of this semiconductor package 1 in the manufacturing process is that under the temperature change during the molding operation and subsequent processes, the substrate 13 will be warped and the wafer 10 will be skewed, and the surface will be brought into contact with each other. The heat sink 11 adhered to the wafer 10 in a manner is also inclined, as shown in FIG. 1 (B). Therefore, in the subsequent grinding operation, the grinding wheel (Grinding Wheel) is removed to cover the heat sink. In addition to the encapsulation gel on 1 1 ', the part of the heat sink 1 Γ which is tilted up due to the oblique position will be worn away, which will easily damage the heat sink 11', as shown in Figure 1 (C); and because The heat dissipating member 1 1 ′ inclined at this position is inclined upward on one side of the wing portion 1 1 ′, so grinding the grinding wheel 1 1 1 ′ will reduce the contact area of the heat dissipating member 1 Γ with the atmosphere and affect the The heat dissipation efficiency of the heat sink 1 1 ′. Furthermore, during the polishing process of the above-mentioned semi-finished package with a substrate 1 3 'warm, the heat dissipation shape after polishing is changed due to the inclined heat sink 1 1', as shown in FIG. 1 (C). Affect the appearance quality of the product. [Summary of the Invention] In view of the shortcomings of the above-mentioned conventional technology, the main object of the present invention is to provide a semiconductor package with a heat sink, so that the heat sink and the wafer can be adhered in point contact to prevent the substrate from being deformed during the polishing process Heat sink

17130.ptd Page 8 1242860 V. Description of Invention (3) Affected. Another object of the present invention is to provide a semiconductor package with a heat sink, so that the adhesion between the heat sink and the wafer is not inclined, so as to facilitate subsequent operations. In order to achieve the disclosure and other purposes, the semiconductor package with a heat sink provided by the present invention includes: a wafer carrier; a wafer connected to the wafer carrier and electrically connected to the wafer carrier; A heat sink having a first surface facing the wafer, a second surface corresponding to the first surface, and a connection portion protruding from the first surface, wherein the connection portion corresponds to one of the wafer portions There are a plurality of convex portions on the surface; the convex portions are used to adhere to the wafer so that the heat sink is adhered to the wafer, and the heat sink is spaced from the wafer; and a cover is used to cover the wafer and The heat dissipating member encapsulates the gel, and the second surface of the heat dissipating member exposes the encapsulating gel. The heat sink is bonded to the chip by most of the convex parts of the connection part to provide a point contact bonding method, so as to avoid the heat sink being tilted on the wafer due to the skew of the substrate, so it will not be damaged during the grinding process The heat sink. [Embodiment] As shown in Figs. 2 (A) and 2 (B), the side view and the bottom view of the heat sink 21 of the semiconductor package of the present invention are respectively. Referring to Figures 2 (A) and 2 (B), the heat sink 21 of the semiconductor package of the present invention is made of metal materials such as copper, aluminum, copper alloy or aluminum alloy, and has a top surface 210, a The lower surface 2 1 1 is opposite to the upper surface 21 0 and a connecting portion 2 1 2 protruding from the lower surface 2 1 1; and a surface of the connecting portion 2 1 2 opposite to the chip (not shown) There is a majority on 2 1 3

Page 9 17130. ptd 1242860 V. Description of the invention (4) The convex portions 2 1 4 are bonded to the wafer by the convex portions 2 丨 4 to adhere to the wafer. Then, as shown in Figs. 3 (A) to 3 (F), it is a schematic flow chart of the method for manufacturing the semiconductor package I of the present invention. As shown in FIG. 3 (a), a wafer 20 is bonded with an adhesive 24 at a predetermined position on an upper surface 2 3 0 of one of the substrates 23, and a plurality of gold wires 25 are respectively soldered to the wafer 2 〇 and the upper surface 2 3 0 of the substrate 23, so that the chip 20 is electrically connected to the substrate 2 3 (this bonding wire manufacturing process is the same as the conventional one, so it will not be repeated here). Then 'as shown in FIG. 3 (B), after the chip 20 is electrically connected to the substrate 23, the heat sink 21 is connected to the chip 20 with a thermally conductive adhesive 26 (thermal grease) of an insulating material. Adhesive. As shown in FIG. 3 (C), the majority of the convex portions 214 formed on the surface 2 13 of the connecting portion 2 丨 2 of the heat sink 2 丨 will be bonded to the upper surface 200 of the chip 20. The convex portion 214 provides a bonding structure of the chip 20 and the heat sink 2], and the surface 213 of the connection portion 212 of the heat sink 21 on the surface of the chip 2 can be fully adhered through the adhesive 26, because The m 1 connection method overcomes the problem of placing the heat sink 2 1_ due to the tilting of the wafer 20, thereby facilitating subsequent processes. As shown in FIG. 3 (D), the semi-finished product with the heat sink 2 丨, the wafer 20, and the base = M is placed in the cavity (not shown) of the packaging mold to perform the second I operation. The encapsulating resin injected into the cavity forms an encapsulating gel 22 for encapsulating the heat sink 2, the wafer 20, and the substrate 23. As shown in FIG. 3 (E), the molding process is finished, grinding is performed so that the upper surface of the heat sink 21 is directly exposed from 210, and the surface is covered with ^

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1242860 V. Description of the invention (5) The surface of the wafer Γί = Γ2 further improves the heat dissipation efficiency. As shown in Figure (F), after the polishing process is completed, a plurality of solder balls 27 are planted on the lower surface 231 of the substrate, so as to form an electrical connection relationship between the two boundary devices of the chip. And the cutting tool is used to make two orders (Si ngul ah οη) to form a plurality of single semiconductors. The process of encapsulating and planting the balls is the same as that of the known person, so it is not redundant here. As shown in Figure 4, borrow The convex part 214 formed by the heat sink 1 connection part 2 12 surface 21 3 of the semiconductor package 4 will make the wafer 20 contact the convex part 214 of the loose part, and the connection part 212 of the heat sink 21 is not formed. The surface 21 3 of the convex part 2 and the adhesive 20 of the wafer 20, the upper surface 200, and the wafer 26 of the semiconductor package (2, 4) of the present invention (2〇 / '2〇 = the heat sink 21) Form a point contact bonding structure, instead of a conventional surface contact, so that the heat sink 21, which is bonded to the chip 20, is not placed due to the warpage of the chip 20 '. The above-mentioned embodiment is only used for The features and effects of the present invention are exemplified and used to limit the implementable scope of the present invention. For example, as shown in Figures 2 (A) and 2 (β), the heat sink 21 does not look upright. It is limited to a circular shape, which may also have a shape such as a square shape; moreover, the number and shape of the convex portions 21 4 formed on the surface 21 3 of the connecting portion are not limited by the drawings. In addition to the BGA (Ball Grid Array) substrate shown in the figure, today's US board 2 3 can be used on QFN (Quad Flat Non lead) leadframe wafer carriers or g-crystalline BGA, that is, It depends on the implementation form. Therefore, without departing from the spirit and technical features of the disclosure disclosed in this disclosure, any modification or change made using the disclosure disclosed in the present invention should still be the application disclosed in the present invention. ★ Youth Academy ^

17130. ptd Page 11 1242860 V. Description of Invention (6) The scope is covered. 17130. ptd Page 12 1242860 Brief description of drawings [Simplified description of drawings] Sections 1 (A) to 1 (C) are sectional views of conventional semiconductor packages with heat sinks; Sections 2 (A) and 2 (B) is a side view and a bottom view of the heat sink of the semiconductor package of the present invention; Figures 3 (A) to 3 (F) are schematic diagrams of the manufacturing process of the semiconductor package with the heat sink of the present invention And FIG. 4 is a schematic diagram of another embodiment of a semiconductor package with a heat sink according to the present invention. Bu 2, 4 Semiconductor packages 10, 10 ', 20, 20, η, 11' Heat sink 110 Top surface 111 '111' Wing 12 Packaging gel 13, 23 Substrate 130, 200 > 2 0 0, 210 '230 Upper surface m, 211, 231 Lower surface 16 Adhesive 21 Radiator 212 Connecting portion 213 Surface 214 Convex portion 215 Curved surface structure 24, 26, 2 6 'Adhesive 25 Gold wire 27 Fresh ball 3 Grinding wheel a piece

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Claims (1)

1242860 VI. Patent application scope 1. A semiconductor package with a heat sink, comprising: a wafer carrier; a wafer connected to and electrically connected to the wafer carrier; and a heat sink, It has a first surface facing the wafer, a second surface corresponding to the first surface, and a connecting portion protruding from the first surface, wherein the connecting portion corresponds to a surface of the wafer portion. A plurality of convex portions are provided; the convex portions are used for adhering to the wafer so that the heat sink is adhered to the wafer so that the heat sink is spaced from the wafer. 2. For example, a semiconductor package with a heat sink in the scope of the patent application, wherein the semiconductor package has a packaging gel for covering the chip and the heat sink and making the second surface of the heat sink The encapsulant is exposed. 3. For a semiconductor package with a heat sink, such as the one in the scope of the patent application, wherein the wafer carrier is a substrate. 4. For a semiconductor package with a heat sink as described in item 3 of the patent application, wherein the chip is electrically connected to the substrate with a bonding wire. 5. For example, a semiconductor package with a heat sink in the scope of patent application, wherein the heat sink is bonded to the chip by a thermally conductive adhesive. 6. For a semiconductor package with a heat sink as described in the first patent application, the chip carrier is a lead frame. 7. The semiconductor package with a heat sink according to item 6 of the patent application, wherein the chip is electrically connected to the lead frame with a bonding wire. 1 1 1 1 1 1 1 U 1 17130. ptd page 14