WO2021149637A1 - 電子装置および電子装置の製造方法 - Google Patents

電子装置および電子装置の製造方法 Download PDF

Info

Publication number
WO2021149637A1
WO2021149637A1 PCT/JP2021/001480 JP2021001480W WO2021149637A1 WO 2021149637 A1 WO2021149637 A1 WO 2021149637A1 JP 2021001480 W JP2021001480 W JP 2021001480W WO 2021149637 A1 WO2021149637 A1 WO 2021149637A1
Authority
WO
WIPO (PCT)
Prior art keywords
electronic device
electronic component
mounting
ridge
bonding material
Prior art date
Application number
PCT/JP2021/001480
Other languages
English (en)
French (fr)
Inventor
羊水 二村
正彦 中村
Original Assignee
ローム株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ローム株式会社 filed Critical ローム株式会社
Priority to US17/792,931 priority Critical patent/US20230094354A1/en
Priority to CN202180010467.2A priority patent/CN115023804A/zh
Priority to DE112021000726.2T priority patent/DE112021000726T5/de
Priority to JP2021572719A priority patent/JPWO2021149637A1/ja
Publication of WO2021149637A1 publication Critical patent/WO2021149637A1/ja

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29012—Shape in top view
    • H01L2224/29015—Shape in top view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29016—Shape in side view
    • H01L2224/29018—Shape in side view comprising protrusions or indentations
    • H01L2224/29019—Shape in side view comprising protrusions or indentations at the bonding interface of the layer connector, i.e. on the surface of the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29347—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/2939—Base material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32052—Shape in top view
    • H01L2224/32053—Shape in top view being non uniform along the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32052—Shape in top view
    • H01L2224/32056—Shape in top view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H01L2224/32058—Shape in side view being non uniform along the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H01L2224/32059—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73263—Layer and strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83194—Lateral distribution of the layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83439—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83455—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862—Heat curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/182—Disposition

Definitions

  • This disclosure relates to an electronic device and a method of manufacturing the electronic device.
  • Patent Document 1 discloses an example of a conventional electronic device.
  • the electronic device described in Patent Document 1 includes an electronic component, a lead frame, and a joining material.
  • the electronic component is a semiconductor element.
  • the lead frame includes a mounting portion for mounting electronic components.
  • the mounting part is a part called an island or a die pad.
  • the joining material joins the electronic component to the mounting portion. For example, silver paste is used as the bonding material.
  • the electronic component generates heat when the electronic component is energized. Due to this heat generation, thermal stress due to the difference in the coefficient of linear expansion between the electronic component and the mounting portion (lead frame) is applied to the joint material. As a result, the joining material may be peeled off from the mounting portion, or the joining material may be damaged (for example, cracks are generated). This peeling or damage causes a decrease in conductivity and a decrease in heat dissipation in the electronic device.
  • the present disclosure has been conceived in view of the above circumstances, and an object thereof is to provide an electronic device capable of suppressing peeling or damage of a bonding material. Another object of the present invention is to provide a method for manufacturing an electronic device capable of suppressing peeling or damage of a bonding material.
  • the electronic device provided by the first aspect of the present disclosure has an electronic component having an element main surface and an element back surface separated in the thickness direction, and a mounting surface facing the element back surface, and the electronic component is mounted.
  • a mounting portion and a joining material for joining the electronic component to the mounting portion are provided, and the joining material includes a base portion sandwiched between the electronic component and the mounting portion in the thickness direction.
  • the electronic component includes a fillet portion connected to the base portion and formed on the outside of the electronic component when viewed in the thickness direction, and each of the electronic components is connected to the main surface of the element and the back surface of the element.
  • a second element side surface, a ridge extending in the thickness direction at the intersection of the first element side surface and the second element side surface, and the fillet portion covers at least a part of the ridge. Includes ridge covering.
  • the method of manufacturing an electronic device provided by the second aspect of the present disclosure includes an electronic component having an element main surface and an element back surface separated in the thickness direction, and a mounting surface facing the element back surface, and the electron.
  • a method for manufacturing an electronic device including a mounting portion on which a component is mounted and a bonding material for joining the electronic component to the mounting portion, wherein a coating step of applying a paste-like bonding material to the mounting surface is used.
  • the mounting portion includes a mounting step of mounting the electronic component on the paste-like bonding material and a solidification step of solidifying the paste-like bonding material to form the bonding material, and the mounting portion includes the electronic component.
  • the joining region includes a joining region to be joined, the joining region includes a corner portion overlapping the corners of the electronic component when viewed in the thickness direction, and the paste-like bonding material includes the electron when viewed in the thickness direction. It is applied from the central portion of the component toward the corner portion to at least the corner portion.
  • peeling or damage of the bonding material can be suppressed.
  • the method for manufacturing an electronic device of the present disclosure for example, it is possible to manufacture an electronic device in which peeling or damage of a bonding material is suppressed.
  • FIG. 1 It is a top view which shows the electronic device which concerns on one Embodiment. It is a figure which showed the resin member 2 by an imaginary line in FIG. It is a bottom view which shows the electronic device which concerns on one Embodiment. It is a front view which shows the electronic device which concerns on one Embodiment. It is a side view (left side view) which shows the electronic device which concerns on one Embodiment. It is sectional drawing which follows the VI-VI line of FIG. It is sectional drawing which follows the line VII-VII of FIG. It is sectional drawing which follows the line VIII-VIII of FIG. It is a perspective view which shows the joining structure by a joining material. It is a top view which shows the joining structure by a joining material.
  • the electronic device A1 has a package structure called, for example, a QFN (Quad Flat Non-leaded package).
  • the electronic device A1 is mounted on a circuit board of an electronic device or the like.
  • the electronic device A1 has, for example, a rectangular shape in a plan view.
  • the electronic device A1 includes an electronic component 1, a resin member 2, a lead frame 3, a joining material 4, and a plurality of connecting members 5.
  • FIG. 1 is a plan view showing the electronic device A1.
  • FIG. 2 is a diagram showing the resin member 2 in FIG. 1 with an imaginary line.
  • FIG. 3 is a bottom view showing the electronic device A1.
  • FIG. 4 is a front view showing the electronic device A1.
  • FIG. 5 is a side view (left side view) showing the electronic device A1.
  • FIG. 6 is a cross-sectional view taken along the line VI-VI of FIG.
  • FIG. 7 is a cross-sectional view taken along the line VII-VII of FIG.
  • FIG. 8 is a cross-sectional view taken along the line VIII-VIII of FIG.
  • FIG. 9 is an enlarged perspective view of a main part showing a joining structure made of the joining material 4.
  • FIG. 9 is an enlarged perspective view of a main part showing a joining structure made of the joining material 4.
  • FIGS. 9 to 11 show the electronic component 1, a part of the lead frame 3 (first lead 31 described later), and the joining material 4.
  • the three directions orthogonal to each other are defined as the x direction, the y direction, and the z direction.
  • the z direction is the thickness direction of the electronic device A1.
  • the x direction is the left-right direction in the plan view (see FIG. 1) of the electronic device A1.
  • the y direction is the vertical direction in the plan view (see FIG. 1) of the electronic device A1.
  • One in the x direction is the x1 direction
  • the other in the x direction is the x2 direction.
  • one in the y direction is the y1 direction
  • the other in the y direction is the y2 direction
  • one in the z direction is the z1 direction
  • the other in the z direction is the z2 direction.
  • planar view means when viewed in the z direction.
  • the z direction is also referred to as a "thickness direction”.
  • the x direction is an example of the "first direction”
  • the y direction is an example of the "second direction”.
  • the electronic component 1 is an element that exerts an electrical function of the electronic device A1.
  • the electronic component 1 is, for example, an integrated circuit element, an active functional element, a passive functional element, or the like.
  • the electronic component 1 is, for example, a semiconductor element made of a semiconductor material. Examples of the semiconductor material include Si (silicon), SiC (silicon carbide), Ge (germanium), GaAs (gallium arsenide) and GaN (gallium nitride).
  • the electronic component 1 is made of silicon.
  • the electronic component 1 has, for example, a rectangular shape in a plan view.
  • the electronic component 1 has an element main surface 11, an element back surface 12, and a plurality of element side surfaces 131 to 134.
  • the element main surface 11 and the element back surface 12 are separated from each other in the z direction.
  • the element main surface 11 faces the z2 direction, and the element back surface 12 faces the z1 direction.
  • the back surface 12 of the element faces the lead frame 3.
  • a plurality of main surface electrodes 111 are formed on the element main surface 11. Each of the plurality of main surface electrodes 111 is exposed on the element main surface 11.
  • a back surface electrode 121 is formed on the back surface 12 of the element.
  • the back surface electrode 121 is exposed on the back surface 12 of the element.
  • the back surface electrode 121 is formed over substantially the entire surface of the back surface 12 of the element.
  • the number, arrangement, shape, and plan view dimensions of the main surface electrode 111 and the back surface electrode 121 are not limited to the examples shown in FIGS. 2 and 6 to 8, and are appropriately changed according to the electronic component 1 used.
  • NS Each of the plurality of element side surfaces 131 to 134 is sandwiched between the element main surface 11 and the element back surface 12 in the z direction, and is connected to both the element main surface 11 and the element back surface 12.
  • the side surfaces 131 to 134 of each element stand upright from the back surface 12 of the element, and in the present embodiment, they stand upright. As shown in FIGS.
  • the element side surfaces 131 and 133 are separated from each other in the x direction.
  • the element side surface 131 faces the x1 direction, and the element side surface 133 faces the x2 direction.
  • the element side surfaces 132 and 134 are separated from each other in the y direction.
  • the element side surface 132 faces the y1 direction, and the element side surface 134 faces the y2 direction.
  • the plurality of element side surfaces 131 to 134 are examples of "first element side surface", “second element side surface”, “third element side surface”, and "fourth element side surface", respectively.
  • the electronic component 1 has a plurality of ridges 141 to 144 as shown in FIGS. 2 and 8 to 11.
  • the ridge 141 is an intersection of the element side surface 131 and the element side surface 132.
  • the ridge 142 is an intersection of the element side surface 132 and the element side surface 133.
  • the ridge 143 is an intersection of the element side surface 133 and the element side surface 134.
  • the ridge 144 is an intersection of the element side surface 134 and the element side surface 131.
  • Each ridge 141 to 144 extends in the z direction.
  • the plurality of ridges 141 to 144 correspond to the four corners of the electronic component 1 in a plan view. Ridge 141 is an example of an "ridge”, and each ridge 142-144 is an example of an "additional ridge”.
  • the resin member 2 is a sealing material that protects the electronic component 1.
  • the resin member 2 is made of an insulating resin material. As the resin material, for example, a black epoxy resin is adopted.
  • the resin member 2 covers the electronic component 1, a part of the lead frame 3, and the plurality of connecting members 5.
  • the resin member 2 has a rectangular shape in a plan view.
  • the resin member 2 has a resin main surface 21, a resin back surface 22, and a plurality of resin side surfaces 231 to 234. As shown in FIGS. 4 to 8, the resin main surface 21 and the resin back surface 22 are separated from each other in the z direction.
  • the resin main surface 21 faces the z2 direction
  • the resin back surface 22 faces the z1 direction.
  • the plurality of resin side surfaces 231 to 234 are sandwiched between the resin main surface 21 and the resin back surface 22 in the z direction, respectively, and are connected to both the resin main surface 21 and the resin back surface 22.
  • Each of the resin side surfaces 231 to 234 stands upright from the resin back surface 22, and in the present embodiment, stands upright.
  • the resin side surfaces 231,233 are separated in the x direction.
  • the resin side surface 231 faces the x1 direction, and the resin side surface 233 faces the x2 direction. As shown in FIGS. 1 to 3 and 5, the resin side surfaces 232 and 234 are separated in the y direction. The resin side surface 232 faces the y1 direction, and the resin side surface 234 faces the y2 direction.
  • the lead frame 3 supports the electronic component 1 and conducts to the electronic component 1. A part of the lead frame 3 is exposed from the resin member 2, and the exposed portion is an external terminal in the electronic device A1.
  • the lead frame 3 is made of, for example, metal. As the metal, for example, Cu (copper), Cu alloy, nickel, nickel alloy, 42 alloy, or the like is adopted. In this embodiment, the lead frame 3 is made of Cu.
  • the lead frame 3 is formed by, for example, etching a metal plate.
  • the lead frame 3 may be formed by subjecting a metal plate to machining such as punching or bending instead of etching.
  • the lead frame 3 includes a first lead 31 and a plurality of second leads 32.
  • the first lead 31 is arranged at the center of the electronic device A1 in a plan view, and extends to both ends of the electronic device A1 in the x-direction and the y-direction. As shown in FIGS. 1 to 3 and 6 to 8, the first lead 31 includes a mounting portion 311, a plurality of terminal portions 312, and a connecting portion 313.
  • the mounting unit 311 is mounted with the electronic component 1.
  • the mounting portion 311 has, for example, a rectangular shape in a plan view as shown in FIGS. 2 and 10. Each side of the mounting portion 311 in a plan view is substantially parallel in the x direction or the y direction.
  • the mounting unit 311 has a mounting surface 311a and a back surface 311b.
  • the mounting surface 311a and the back surface 311b are separated from each other in the z direction.
  • the mounting surface 311a faces the z2 direction, and the back surface 311b faces the z1 direction.
  • the mounting surface 311a faces the electronic component 1 (element back surface 12).
  • the electronic component 1 is mounted on the mounting surface 311a.
  • the mounting surface 311a may be plated.
  • the plating material is appropriately selected according to the material of the bonding material 4.
  • the wettability of the solder can be improved by applying Ag plating or Ni plating to the mounting surface 311a.
  • the back surface 311b is exposed from the resin back surface 22 and serves as an external terminal in the electronic device A1. As shown in FIGS. 6 to 8, the back surface 311b is flush with the resin back surface 22.
  • the plurality of terminal portions 312 are arranged one by one at each of the four corners of the electronic device A1 in a plan view.
  • Each terminal portion 312 has, for example, a rectangular shape in a plan view.
  • each terminal portion 312 has a main surface 312a, a back surface 312b, and two end surfaces 312c.
  • the main surface 312a and the back surface 312b are separated in the z direction.
  • the main surface 312a faces the z2 direction
  • the back surface 312b faces the z1 direction.
  • the main surface 312a is flush with the mounting surface 311a.
  • the back surface 312b is exposed from the resin back surface 22 as shown in FIGS. 3 and 8.
  • the two end faces 312c are connected to the main surface 312a and the back surface 312b, respectively, and are orthogonal to the main surface 312a and the back surface 312b, respectively.
  • Each of the two end faces 312c is exposed from any of the plurality of resin side surfaces 231 to 2.34.
  • One of the two end faces 312c faces outward in the x direction, and the other of the two end faces 312c faces outward in the y direction.
  • the back surface 312b and the two end faces 312c are external terminals in the electronic device A1.
  • each connecting portion 313 extends radially from each of the four corners of the mounting portion 311 in a plan view, and is connected to each terminal portion 312.
  • the thickness of the connecting portion 313 is, for example, about half the thickness of the mounting portion 311.
  • the connecting portion 313 is formed by, for example, a half etching process.
  • each connecting portion 313 has a main surface 313a and a back surface 313b.
  • the main surface 313a and the back surface 313b are separated in the z direction.
  • the main surface 313a faces the z2 direction, and the back surface 313b faces the z1 direction.
  • the main surface 313a is flush with the mounting surface 311a and the main surface 312a.
  • the main surface 313a and the back surface 313b are covered with the resin member 2.
  • a plating layer (not shown) is formed on the portion exposed from the resin member 2.
  • the plating layer is formed on the back surface 311b, the back surface 312b, and each end surface 312c.
  • the plating layer is made of a material having a higher solder wettability than the base material of the first lead 31, for example, Au.
  • the plating layer is formed by, for example, replacement type electroless plating. The plating layer may not be formed.
  • each of the plurality of second leads 32 conducts to the main surface electrode 111 of the electronic component 1 via each connecting member 5.
  • the plurality of second leads 32 are arranged at both ends in the x direction and both ends in the y direction of the electronic device A1 in a plan view, and are separated from each other.
  • the plurality of second leads 32 are separated from the first lead 31.
  • the electronic device A1 is arranged along the resin side surface 231, the plurality of second leads 32 arranged along the resin side surface 231 and the plurality of second leads 32 arranged along the resin side surface 232, and the resin side surface 233 in a plan view.
  • each second lead 32 includes a terminal portion 321 and a connection portion 322.
  • each of the plurality of terminal portions 321 has a rectangular shape, for example, in a plan view. A part of each terminal portion 321 is exposed from the resin member 2.
  • each terminal portion 321 has a main surface 321a, a back surface 321b, and an end surface 321c.
  • the main surface 321a and the back surface 321b are separated in the z direction.
  • the main surface 321a faces the z2 direction
  • the back surface 321b faces the z1 direction.
  • the back surface 321b is exposed from the resin back surface 22.
  • the end surface 321c is connected to the main surface 321a and the back surface 321b.
  • the end face 321c is exposed from any of the plurality of resin side surfaces 231 to 234.
  • the back surface 321b and the end surface 321c are external terminals in the electronic device A1.
  • each of the plurality of connection portions 322 extends from the terminal portion 321 toward the mounting portion 311.
  • Each connecting member 5 is joined to each connecting portion 322.
  • the plurality of second leads 32 arranged parallel to the edge on both sides of the mounting portion 311 in the y direction are arranged on both end sides in the x direction, so that the connecting portion 322 is more inclined with respect to the y direction. Further, as for the plurality of second leads 32 arranged parallel to the edge on both sides of the mounting portion 311 in the x direction, the connecting portion 322 is more inclined with respect to the x direction as the second leads 32 are arranged on both ends in the y direction. There is.
  • each connecting portion 322 of the second lead 32 (adjacent to the connecting portion 313) arranged on both end sides extends substantially parallel to the extending direction of the adjacent connecting portion 313. It should be noted that each connecting portion 322 does not have to be inclined with respect to the x direction or the y direction.
  • each second lead 32 as shown in FIG. 6, the thickness (dimension in the z direction) of the connecting portion 322 is, for example, about half the thickness of the terminal portion 321.
  • the connecting portion 322 is formed by, for example, a half etching process.
  • Each connecting portion 322 has a main surface 322a and a back surface 322b.
  • the main surface 322a and the back surface 322b are separated in the z direction.
  • the main surface 322a faces the z2 direction, and the back surface 322b faces the z1 direction.
  • the main surface 322a is a surface to which the connecting member 5 is joined.
  • the main surface 321a and the main surface 322a are flush with each other.
  • the back surface 322b is covered with the resin member 2.
  • the thickness of the connection portion 322 may be the same as the thickness of the terminal portion 321. In this case, the back surface 321b and the back surface 322b are flush with each other, and the back surface 322b is exposed from the resin member 2 (resin back surface 22).
  • a plating layer (not shown) is formed on the portion exposed from the resin member 2.
  • the plating layer is formed on the back surface 321b and the end surface 321c.
  • the plating layer is similar to the plating layer of the first lead 31, and is made of, for example, Au, and is formed by substitution type electroless plating. The plating layer may not be formed.
  • the joining material 4 joins the electronic component 1 to the lead frame 3.
  • the bonding material 4 is, for example, sintered silver.
  • the bonding material 4 is not limited to sintered silver, and may be another sintered metal such as sintered copper, or another conductive bonding material such as solder or silver paste.
  • the joining material 4 is not limited to the conductive joining material, and may be an insulating joining material.
  • the bonding material 4 is an insulating bonding material, the back surface electrode 121 is not provided on the electronic component 1, or the bonding material 4 between the back surface electrode 121 of the electronic component 1 and the mounting portion 311 is used. Only when the conduction is unnecessary.
  • the joining material 4 is interposed between the electronic component 1 and the mounting portion 311 (first lead 31).
  • the joining material 4 is in contact with the back surface 12 of the element and the mounting surface 311a.
  • the back surface electrode 121 and the mounting portion 311 are electrically connected to each other via the joining material 4.
  • the joining material 4 includes a base 41 and a fillet 42.
  • the base portion 41 is sandwiched between the electronic component 1 and the mounting portion 311 in the z direction.
  • the base 41 completely overlaps the electronic component 1 in a plan view.
  • the base 41 is in contact with the entire surface of the back surface 12 of the element.
  • the base 41 has, for example, a rectangular shape in a plan view.
  • the base portion 41 has a substantially uniform thickness (dimension in the z direction).
  • the fillet portion 42 is connected to the base portion 41 and is formed on the outside of the electronic component 1 in a plan view. As shown in FIG. 10, the fillet portion 42 is formed over the entire circumference of the electronic component 1 in a plan view. As shown in FIGS. 9 and 11, the fillet portion 42 projects upward from the base portion 41 along the side surfaces 131 to 134 of each element in the z direction.
  • the fillet portion 42 includes a plurality of side covering portions 431 to 434 and a plurality of ridge covering portions 441 to 444.
  • the ridge covering portion 441 is an example of the "ridge covering portion”
  • each ridge covering portion 442 to 444 is an example of the "additional ridge covering portion”.
  • the side covering portion 431 is an example of the "first covering portion”
  • the side covering portion 432 is an example of the "second covering portion”.
  • the ridge covering portion 441 covers at least a part of the ridge 141 as shown in FIGS. 8 to 11. In the present embodiment, the ridge covering portion 441 covers the lower end of the ridge 141 in the z direction and does not cover the upper end of the ridge 141 in the z direction. As shown in FIG. 10, the ridge covering portion 441 connects the side covering portion 431 and the side covering portion 432.
  • the ridge covering portion 442 covers at least a part of the ridge 142 as shown in FIGS. 9 and 10. In the present embodiment, the ridge covering portion 442 covers the lower end of the ridge 142 in the z direction and does not cover the upper end of the ridge 142 in the z direction. As shown in FIG. 10, the ridge covering portion 442 connects the side covering portion 432 and the side covering portion 433.
  • the ridge covering portion 443 covers at least a part of the ridge 143.
  • the ridge covering portion 443 covers the lower end of the ridge 143 in the z direction and does not cover the upper end of the ridge 143 in the z direction.
  • the ridge covering portion 443 connects the side covering portion 433 and the side covering portion 434.
  • the ridge covering portion 444 covers at least a part of the ridge 144 as shown in FIGS. 9 and 10. In the present embodiment, the ridge covering portion 444 covers the lower end of the ridge 144 in the z direction and does not cover the upper end of the ridge 144 in the z direction. As shown in FIG. 10, the ridge covering portion 444 connects the side covering portion 434 and the side covering portion 431.
  • the side covering portion 431 covers at least a part of the element side surface 131.
  • the edge on the z2 direction side that is, the edge on the element main surface 11 side is exposed from the side covering portion 431 when viewed in the x direction
  • the edge on the z1 direction side that is, The edge on the back surface 12 side of the element is covered with the side covering portion 431 when viewed in the x direction.
  • the side covering portion 431 is sandwiched between the ridge covering portion 444 and the ridge covering portion 441 and is connected to the ridge covering portion 441.
  • the side covering portion 431 is aligned with the ridge covering portion 444 and the ridge covering portion 441 in the y direction.
  • the side covering portion 432 covers at least a part of the element side surface 132 as shown in FIGS. 9 and 10.
  • the edge on the z2 direction side that is, the edge on the element main surface 11 side is exposed from the side covering portion 432 when viewed in the y direction
  • the edge on the z1 direction side that is, The edge on the back surface 12 side of the element is covered with the side covering portion 432 when viewed in the y direction.
  • the side covering portion 432 is sandwiched between the ridge covering portion 441 and the ridge covering portion 442 and is connected to the ridge covering portion 441.
  • the side covering portion 432 is aligned with the ridge covering portion 441 and the ridge covering portion 442 in the x direction.
  • the side covering portion 433 covers at least a part of the element side surface 133.
  • the edge on the z2 direction side that is, the edge on the element main surface 11 side is exposed from the side covering portion 433 when viewed in the x direction
  • the edge on the z1 direction side that is, The edge on the back surface 12 side of the element is covered with the side covering portion 433 when viewed in the x direction.
  • the side covering portion 433 is sandwiched between the ridge covering portion 442 and the ridge covering portion 443 and is connected to the ridge covering portion 442 and the ridge covering portion 443.
  • the side covering portion 433 is aligned with the ridge covering portion 442 and the ridge covering portion 443 in the y direction.
  • the side covering portion 434 covers at least a part of the element side surface 134.
  • the edge on the z2 direction side that is, the edge on the element main surface 11 side is exposed from the side covering portion 434 when viewed in the y direction
  • the edge on the z1 direction side that is, The edge on the back surface 12 side of the element is covered with the side covering portion 434 when viewed in the y direction.
  • the side covering portion 434 is sandwiched between the ridge covering portion 443 and the ridge covering portion 444 and is connected to the ridge covering portion 443.
  • the side covering portion 434 is aligned with the ridge covering portion 443 and the ridge covering portion 444 in the x direction.
  • each of the side covering portions 431 to 434 has a central portion in each longitudinal direction recessed in the z1 direction from both end edges in each longitudinal direction. Therefore, in each of the lateral covering portions 431 to 434, the dimension d11 of the central portion in each longitudinal direction in the z direction is smaller than the dimension d12 of each end edge portion in each longitudinal direction in the z direction.
  • FIG. 11 shows the dimensions d11 and d12 of the side covering portion 431.
  • a raised portion 439 is formed between the central portion in each longitudinal direction and each edge portion in each longitudinal direction. The raised portion 439 is raised in the z2 direction, that is, toward the element main surface 11 side.
  • the raised portion 439 has the largest dimension in the z direction among the side covering portions 431 to 434 in the side covering portions 431 to 434.
  • FIG. 11 shows a raised portion 439 in the lateral covering portion 431.
  • the longitudinal direction of each side covering portion 431, 433 is the y direction
  • the longitudinal direction of each side covering portion 432, 434 is the x direction.
  • the dimensions d11 and d12 of the side covering portions 431 to 434 may be the same or different in the plurality of side covering portions 431 to 434, respectively.
  • the central portion in each longitudinal direction is recessed toward each element side surface 131 to 134 side with respect to both end edges in each longitudinal direction in a plan view. ..
  • the inclination degree ⁇ 11 is larger than the inclination degree ⁇ 12 (see FIG. 6).
  • the inclination degree ⁇ 11 is an angle formed by the mounting surface 311a and each end edge portion in each longitudinal direction of each side covering portion 431 to 434, and the inclination degree ⁇ 11 is the angle formed by the end edge portion with respect to the mounting surface 311a.
  • the degree of surface inclination As shown in FIG. 7, the inclination degree ⁇ 11 is an angle formed by the mounting surface 311a and each end edge portion in each longitudinal direction of each side covering portion 431 to 434, and the inclination degree ⁇ 11 is the angle formed by the end edge portion with respect to the mounting surface 311a. The degree of surface inclination. As shown in FIG.
  • the inclination degree ⁇ 12 is an angle formed by the mounting surface 311a and the central portion of each of the lateral covering portions 431 to 434 in the longitudinal direction, and the inclination of the surface of the central portion with respect to the mounting surface 311a. Degree.
  • Each of the side covering portions 431 to 434 gradually changes from the inclination degree ⁇ 12 to the inclination degree ⁇ 11 from the central portion toward each end edge portion in each longitudinal direction.
  • the inclination degree ⁇ 11 may be the same as the inclination degree ⁇ 12 or may be smaller than the inclination degree ⁇ 12.
  • the surfaces of the lateral covering portions 431 and 433 are curved in a convex shape when viewed in the y direction, but the surface thereof is not limited to this and is a flat surface. It may be curved in a concave shape. Alternatively, two or more of a convexly curved portion, a concavely curved portion and a flat portion may be mixed. Similarly, the surfaces of the lateral covering portions 432 and 434 are curved in a convex shape when viewed in the x direction, but the surface thereof is not limited to this, and may be a flat surface or a concave shape. You may be doing it. Alternatively, two or more of a convexly curved portion, a concavely curved portion and a flat portion may be mixed.
  • the plurality of connecting members 5 conduct conduction between two parts separated from each other.
  • Each connecting member 5 is, for example, a bonding wire.
  • Each connecting member 5 may be a bonding ribbon, a plate-shaped lead member, or the like instead of the bonding wire.
  • Each constituent material of the plurality of connecting members 5 may be, for example, any of a metal containing Au, a metal containing Al, a metal containing Cu, and the like.
  • Each connecting member 5 is formed by, for example, a well-known wire bonder. As shown in FIG. 2, each connecting member 5 is joined to the main surface electrode 111 of the electronic component 1 and the connecting portion 322 (main surface 322a) of each second lead 32, respectively, and the main surface electrode 111 and the second lead are joined to each other. It is made conductive with 32.
  • FIGS. 12 to 15. are enlarged plan views of a main part showing one step of the manufacturing method of the electronic device A1.
  • 13 and 15 are enlarged side views of a main part showing one step of the manufacturing method of the electronic device A1.
  • each lead frame 3 includes a first lead 31 and a plurality of second leads 32.
  • the first lead 31 includes a mounting portion 311, a plurality of terminal portions 312, and a plurality of connecting portions 313.
  • the mounting portion 311 has a mounting surface 311a facing in the z2 direction.
  • Each second lead 32 includes a terminal portion 321 and a connection portion 322. In the step of preparing the lead frame 3 (preparation step), the plurality of formed lead frames 3 are continuous with each other.
  • the paste-like bonding material 49 is applied to the mounting surface 311a of the mounting portion 311.
  • the paste-like bonding material 49 is, for example, a sintered metal paste (silver paste, copper paste, or the like).
  • a dispenser is used in the step of applying the paste-like bonding material 49 (coating step).
  • the mounting surface 311a includes a joining region 391 to which the electronic component 1 is joined.
  • the joining region 391 is a region of the mounting surface 311a that overlaps all of the electronic components 1 in a plan view when the electronic components 1 are joined.
  • the joint region 391 has substantially the same shape as the electronic component 1 (rectangular shape in the present embodiment) and has the same size as the electronic component 1.
  • the joint region 391 includes four corners 392.
  • the four corner portions 392 are portions that overlap the four corners of the electronic component 1 in a plan view in a state where the electronic component 1 is joined.
  • the paste-like bonding material 49 is linearly applied along the tracks L1 and L2 shown in FIG.
  • the tracks L1 and L2 are the application tracks of the paste-like bonding material 49 by the dispenser, respectively.
  • Each of the orbits L1 and L2 is a straight line passing through the center 393 from one of the pair of corner portions 392 located on the diagonal line of the joint region 391 to the other.
  • the start points and end points of the orbits L1 and L2 overlap each corner portion 392, but may be set outside the plan view of the joint region 391 than each corner portion 392.
  • the coating trajectory of the paste-like bonding material 49 is not limited to this.
  • the paste-like bonding material 49 may be applied radially from the center 393 of the bonding region 391 to each of the four corner portions 392.
  • the applied paste-like bonding material 49 completely covers all four corner portions 392 and is formed in an X shape in a plan view.
  • the tracks L1 and L2 to which the paste-like joining material 49 is applied have the corner portion 392 as the starting point and the ending point, the applied paste-like joining material 49 is outside the joining region 391 with respect to the corner portion 392. Is formed up to.
  • the paste-like joining material 49 is formed with a protruding portion 491 when viewed from the side (x direction or y direction).
  • the protruding portion 491 is a portion of the paste-like joining material 49 that rises in the z2 direction and is formed on the center 393 of the joining region 391.
  • the protrusion 491 is formed because the two tracks L1 and L2 intersect when the paste-like joining material 49 is applied along the tracks L1 and L2.
  • the applied paste-like bonding material 49 has a line width W1 (see FIG. 12) of, for example, 200 ⁇ m or more and 300 ⁇ m or less, and a thickness (dimension in the z direction) of, for example, 100 ⁇ m or more and 150 ⁇ m or less (excluding the protruding portion 491). ..
  • the paste-like joining material 49 is curved in a semicircular shape when viewed in the traveling direction of each of the orbits L1 and L2, and the thickness thereof is the size of the maximum portion (excluding the protruding portion 491).
  • the electronic component 1 is placed on the paste-like joining material 49.
  • a well-known die bonder is used in the step of mounting the electronic component 1 (mounting step).
  • the paste-like bonding material 49 is expanded by the weight of the electronic component 1.
  • the paste-like bonding material 49 may be expanded not only by the weight of the electronic component 1 but also by the pressing force when the electronic component 1 is pressed by the die bonder.
  • the expanded paste-like joint material 49 covers the entire region of the joint region 391 and has a shape protruding outward over the entire circumference of the joint region 391. At this time, the paste-like joining material 49 has substantially the same shape as the joining material 4.
  • the paste-like joining material 49 is solidified to form the joining material 4.
  • the paste-like bonding material 49 is solidified by sintering. ..
  • the solvent in the paste-like bonding material 49 is volatilized and disappears, and the metal particles (silver particles, copper particles, etc.) in the paste-like bonding material 49 are bonded to each other, so that the paste-like bonding material 49 is formed. It solidifies and the bonding material 4 is formed.
  • the solidification step is appropriately changed depending on the material of the paste-like bonding material 49.
  • the paste-like bonding material 49 is a thermosetting metal paste
  • the paste-like bonding material 49 is heated in the solidification step. By this heating, the resin material in the metal paste is cured, so that the paste-like bonding material 49 is solidified and the bonding material 4 is formed.
  • the "metal paste” refers to, for example, a conductive material composed of fine particles of metal, fine particles (binder) such as epoxy resin, and a solvent.
  • Each of the plurality of connecting members 5 is formed by, for example, a well-known wire bonder.
  • One end of each connecting member 5 is joined to the main surface electrode 111 of the electronic component 1, and the other end is joined to the connecting portion 322 (main surface 322a) of each second lead 32.
  • the resin member 2 is formed.
  • a well-known transfer molding machine or compression molding machine is used as the resin member 2.
  • the resin member 2 for example, an insulating epoxy resin is used.
  • the lead frame 3 is partially exposed from the formed resin member 2.
  • the resin member 2 and the lead frame 3 are cut for each electronic component 1 and separated into individual pieces.
  • the electronic device A1 is formed.
  • the above-mentioned manufacturing method is an example, and the present invention is not limited to this.
  • the joining material 4 for joining the electronic component 1 to the lead frame 3 includes a fillet portion 42.
  • the fillet portion 42 includes a ridge covering portion 441 that covers at least a part of the ridge 141.
  • the ridge 141 is an intersection of the element side surface 131 and the element side surface 132, and corresponds to one of the four corners of the electronic component 1 in a plan view. According to this configuration, the ridge 141 (lower corner portion of the electronic component 1) of the electronic component 1 is protected by the joining material 4 (ridge covering portion 441 of the fillet portion 42).
  • the fillet portion 42 of the joining material 4 includes a plurality of ridge covering portions 441 to 444.
  • Each of the plurality of ridge covering portions 441 to 444 covers each of the lower end portions of the plurality of ridges 141 to 144 of the electronic component 1. That is, the lower four corners of the electronic component 1 are covered with the fillet portions 42. According to this configuration, it is possible to improve the resistance to peeling or damage of the bonding material 4 in the vicinity of the lower four corners of the electronic component 1. Therefore, according to the electronic device A1, peeling or damage of the bonding material 4 can be suppressed.
  • the joining material 4 includes the base 41.
  • the base 41 is sandwiched between the electronic component 1 and the mounting portion 311 and completely overlaps with the electronic component 1.
  • the base 41 is in contact with the entire surface of the back surface 12 of the element.
  • the back surface 12 of the element is protected by the bonding material 4 (base 41). Therefore, according to the electronic device A1, even if the back surface 12 of the element of the electronic component 1 is slightly scratched, the progress of destruction of the electronic component 1 starting from the scratch can be suppressed.
  • the bonding material 4 is made of, for example, sintered silver.
  • Sintered silver has lower ductility than solder. Therefore, when the bonding material 4 is made of sintered silver, the thermal stress applied to the bonding material 4 is larger than when the bonding material 4 is made of solder. This is because solder can relax thermal stresses more than sintered silver due to its ductility. That is, when the bonding material 4 is made of sintered silver, the bonding material 4 is more likely to be peeled off or broken due to thermal stress than when the bonding material 4 is made of solder.
  • the electronic component 1 is a semiconductor element made of, for example, silicon, and the lead frame 3 is made of, for example, Cu.
  • the thermal stress applied to the bonding material 4 becomes large. That is, the bonding material 4 is likely to be peeled off or damaged due to thermal stress. Therefore, when the electronic component 1 made of silicon is joined to the mounting portion 311 (lead frame 3) made of Cu by using the joining material 4, the fillet portion 42 (ridge covering portion 441) protects the ridge 141 as described above. This is effective in suppressing peeling and breakage of the bonding material 4.
  • the paste-like bonding material 49 is applied to each corner portion 392 of the bonding region 391, so that the four corners of the bonding region 391 are covered with the paste-like bonding material 49.
  • the paste-like bonding material 49 spreads so as to cover at least a part of each of the ridges 141 to 144 of the electronic component 1. That is, a fillet portion 42 including a ridge covering portion 441 is formed on the joining material 4. Therefore, according to the manufacturing method of the present disclosure, it is possible to manufacture the electronic device A1 in which the peeling and breaking of the bonding material 4 are suppressed.
  • the paste-like bonding material 49 is applied in an X shape in a plan view in the coating process.
  • the fillet portion 42 including the ridge covering portions 441 to 444 is formed by applying the paste-like bonding material 49 over the entire surface or a wider range than the entire surface of the bonding region 391. Be done.
  • the paste-like bonding material 49 may greatly spread to the outside of the electronic component 1 in a plan view. In this case, the paste-like bonding material 49 flows out to an unintended place, and there is a concern that an unintended short circuit may occur, for example.
  • the unintended short circuit includes a short circuit between the main surface electrodes 111 of the electronic component 1.
  • the cost will increase due to the material cost of the part that has spread unnecessarily. Therefore, in the manufacturing method of the present disclosure, by applying the paste-like bonding material 49 in an X shape, the fillet portion 42 including the ridge covering portions 441 to 444 is formed, and the above-mentioned unintended short circuit occurs. It is possible to suppress the cost increase.
  • the paste-like bonding material 49 is applied linearly along the tracks L1 and L2 is shown, but the present invention is not limited to this.
  • a plurality of dot-shaped paste-like joining materials 49 may be applied in an X-shape.
  • the paste-like joining material 49 in FIG. 16, is shown by an imaginary line.
  • Each paste-like joining material 49 is, for example, hemispherical. Also in this case, the same joining material 4 as in FIGS. 9 to 11 is formed.
  • the paste-like bonding material 49 is, firstly, the "* (asterisk)" character used in the electronic component 1 having a large rectangular planar shape (typically a large square). There are shapes such as “* (rice stamp)". The "*" shape is arranged between four line segments arranged in an "X” shape and two line segments adjacent to each other in the x direction or the y direction in these four line segments. It is a shape formed by four " ⁇ (dots)”. Secondly, there is an aspect of a shape used in a horizontally long rectangular electronic component 1 in which ">", "-", and " ⁇ " are arranged in contact with or close to each other along the longitudinal direction.
  • the shapes of the side covering portions 431 to 434 are not limited to those described above.
  • the raised portions 439 may not be formed on the side covering portions 431 to 434.
  • each of the lateral covering portions 431 to 434 has a dimension in which the central portion in each longitudinal direction is not recessed in the z1 direction as compared with the both end edges in each longitudinal direction.
  • the d11 and the dimension d12 may be substantially the same. Further, as shown in FIG.
  • each of the side covering portions 431 to 434 is closer to the side surface 131 to 134 of each element than the edge portions at both ends in each longitudinal direction. It does not have to be dented.
  • the central portion in each longitudinal direction may protrude from both end edges in each longitudinal direction to the side opposite to the side surfaces 131 to 134 of each element.
  • Each of the side covering portions 431 to 434 according to these modified examples includes the coating amount of the paste-like bonding material 49 in the coating process, the coating track, the line width W1, and how the paste-like bonding material 49 spreads in the mounting process.
  • the paste-like bonding material 49 is formed by appropriately adjusting the wettability with respect to the mounting portion 311 (lead frame 3).
  • the electronic device A1 has a QFN type package structure
  • the present invention is not limited to this.
  • other package structures such as TO (Transistor Outline) package type, SOP (Small Outline Package) type, QFP (Quad Flat Package) type, and BGA (Ball Grid Array) type may be used.
  • TO Transistor Outline
  • SOP Small Outline Package
  • QFP Quad Flat Package
  • BGA Ball Grid Array
  • the electronic device A1 is a lead frame type
  • the present invention is not limited to this.
  • the electronic component 1 may have a structure in which the electronic component 1 is bonded to, for example, a silicon substrate, a ceramic substrate, a glass substrate, or the like instead of the lead frame 3.
  • the configuration of the present disclosure can be applied to a structure in which the electronic component 1 is joined to a certain support member (mounting portion) via the joining material 4.
  • the electronic device and the method for manufacturing the electronic device according to the present disclosure are not limited to the above-described embodiment.
  • the specific configuration of each part of the electronic device of the present disclosure and the specific processing of each step of the manufacturing method of the electronic device of the present disclosure can be variously redesigned.
  • the electronic device and the method for manufacturing the electronic device according to the present disclosure include embodiments relating to the following appendices.
  • Including and The electronic component is an intersection of the side surface of the first element and the side surface of the second element connected to the main surface of the element and the back surface of the element, and the side surface of the first element and the side surface of the second element, respectively, in the thickness direction.
  • the fillet portion is an electronic device including a ridge covering portion that covers at least a part of the ridge.
  • the fillet portion further includes a first covering portion that covers at least a part of the side surface of the first element, and a second covering portion that covers at least a part of the side surface of the second element.
  • the electronic device according to Appendix 1 wherein the first coating portion and the second coating portion are connected to the ridge coating portion, respectively.
  • Appendix 3 On the side surface of the first element, the edge connected to the main surface of the element is exposed from the first covering portion when viewed in the first direction orthogonal to the side surface of the first element.
  • the electronic device wherein on the side surface of the second element, an edge connected to the main surface of the element is exposed from the second covering portion when viewed in a second direction orthogonal to the side surface of the second element.
  • the electronic component has a rectangular shape when viewed in the thickness direction.
  • the electronic component further includes a third element side surface, a fourth element side surface, and a plurality of additional ridges.
  • the side surface of the third element is connected to the main surface of the element and the back surface of the element, and is separated from the side surface of the first element in the first direction.
  • the side surface of the fourth element is connected to the main surface of the element and the back surface of the element, and is separated from the side surface of the second element in the second direction.
  • the plurality of additional ridges are formed at the intersection of the side surface of the first element and the side surface of the fourth element, the intersection of the side surface of the second element and the side surface of the third element, and the side surface of the third element. It occurs at the intersection with the side surface of the fourth element, and each extends in the thickness direction.
  • the electronic device according to Appendix 4, wherein the fillet portion further includes a plurality of additional ridge covering portions covering the plurality of additional ridges.
  • the dimension of the central portion in the second direction in the thickness direction is smaller than the dimension of the edge portion connected to the ridge covering portion in the thickness direction, according to Appendix 4 or Appendix 5.
  • the first covering portion has a raised portion raised on the element main surface side between the central portion in the second direction and the edge portion connected to the ridge covering portion, whichever of Appendix 4 to Appendix 6.
  • [Appendix 8] The electronic device according to any one of Supplementary note 4 to Supplementary note 7, wherein in the first covering portion, the central portion in the second direction is recessed on the side surface side of the first element when viewed in the thickness direction. ..
  • the electronic device according to one.
  • [Appendix 12] The electronic device according to any one of Supplementary note 4 to Supplementary note 11, wherein in the second covering portion, the central portion in the first direction is recessed on the side surface side of the second element when viewed in the thickness direction.
  • the second covering portion has any of Appendix 4 to Appendix 12, wherein the inclination of the edge portion connected to the ridge coating portion with respect to the mounting surface is larger than the inclination of the central portion with respect to the mounting surface in the first direction.
  • [Appendix 14] The electronic device according to any one of Supplementary note 1 to Supplementary note 13, wherein the fillet portion is formed over the entire circumference of the electronic component when viewed in the thickness direction.
  • [Appendix 15] The electronic device according to any one of Supplementary note 1 to Supplementary note 14, wherein the electronic component is made of a semiconductor material.
  • the electronic component has a main surface electrode formed on the main surface of the element.
  • the mounting portion is a part of the lead frame and
  • the electronic device according to any one of Supplementary note 1 to Supplementary note 15, wherein the lead frame further includes a terminal portion that conducts to the main surface electrode and is separated from the mounting portion.
  • [Appendix 17] The electronic device according to Appendix 16, wherein the lead frame is a metal containing Cu as a constituent material.
  • the electronic component has a back electrode formed on the back surface of the element.
  • An electronic component having an element main surface and an element back surface that are separated in the thickness direction, A mounting portion having a mounting surface facing the back surface of the element and on which the electronic component is mounted, A bonding material for joining the electronic component to the mounting portion, It is a manufacturing method of an electronic device equipped with The coating process of applying the paste-like bonding material to the mounting surface and A mounting step of mounting the electronic component on the paste-like bonding material, and A solidification step of solidifying the paste-like bonding material to form the bonding material, and Including
  • the mounting portion includes a joining region to which the electronic component is joined.
  • the joint region includes a corner portion that overlaps the corner of the electronic component when viewed in the thickness direction.
  • a method for manufacturing an electronic device wherein the paste-like bonding material is applied from the central portion of the electronic component toward the corner portion at least to the corner portion when viewed in the thickness direction.

Abstract

接合材の剥離や損壊を抑制しうる電子装置が提供される。当該電子装置は、電子部品と、搭載部と、接合材とを備える。前記電子部品は、ｚ方向において離間する素子主面および素子裏面を有する。前記搭載部は、前記素子裏面に対向する搭載面を有し、前記電子部品が搭載されている。前記接合材は、前記電子部品を前記搭載部に接合する。前記接合材は、基部とフィレット部とを含む。前記基部は、ｚ方向において前記電子部品と前記搭載部とに挟まれている。前記フィレット部は、前記基部に繋がり、かつ、ｚ方向に見て前記電子部品の外側に形成されている。前記電子部品は、２つの素子側面と、稜とを含む。前記稜は、前記２つの素子側面の交差部分であって、ｚ方向に延びる。前記フィレット部は、前記稜の少なくとも一部を覆う稜被覆部を含む。

Description

電子装置および電子装置の製造方法
　本開示は、電子装置と、電子装置の製造方法とに関する。
　特許文献１には、従来の電子装置の一例が開示されている。特許文献１に記載の電子装置は、電子部品、リードフレーム、および、接合材を備えている。当該電子装置において、電子部品は、半導体素子である。リードフレームは、電子部品を搭載する搭載部を含んでいる。搭載部は、アイランドやダイパッドと呼ばれる部位である。接合材は、電子部品を搭載部に接合する。接合材は、たとえば銀ペーストが採用されている。
特開２０００－２７７６７９号公報
　上記電子装置において、電子部品への通電により、電子部品が発熱する。この発熱によって、電子部品と搭載部（リードフレーム）との線膨張係数の差に起因する熱応力が接合材に加わる。その結果、接合材が搭載部から剥離したり、接合材が損壊（たとえば亀裂の発生など）したりすることがあった。この剥離や損壊は、電子装置における導通性の低下および放熱性の低下を招く。
　本開示は、上記事情に鑑みて考え出されたものであり、その目的は、接合材の剥離や損壊を抑制することができる電子装置を提供することにある。また、接合材の剥離や損壊を抑制可能な電子装置の製造方法を提供することにある。
　本開示の第１の側面によって提供される電子装置は、厚さ方向において離間する素子主面および素子裏面を有する電子部品と、前記素子裏面に対向する搭載面を有し、前記電子部品が搭載された搭載部と、前記電子部品を前記搭載部に接合する接合材と、を備えており、前記接合材は、前記厚さ方向において前記電子部品と前記搭載部とに挟まれた基部と、前記基部に繋がり、かつ、前記厚さ方向に見て前記電子部品の外側に形成されたフィレット部とを含み、前記電子部品は、各々が前記素子主面および前記素子裏面に繋がる第１素子側面および第２素子側面と、前記第１素子側面と前記第２素子側面との交差部分であって前記厚さ方向に延びる稜と、を含み、前記フィレット部は、前記稜の少なくとも一部を覆う稜被覆部を含む。
　本開示の第２の側面によって提供される電子装置の製造方法は、厚さ方向において離間する素子主面および素子裏面を有する電子部品と、前記素子裏面に対向する搭載面を有し、前記電子部品が搭載された搭載部と、前記電子部品を前記搭載部に接合する接合材と、を備えた電子装置の製造方法であって、前記搭載面にペースト状接合材を塗布する塗布工程と、前記ペースト状接合材上に前記電子部品を載置する載置工程と、前記ペースト状接合材を固化し、前記接合材を形成する固化工程と、を含み、前記搭載部は、前記電子部品が接合される接合領域を含み、前記接合領域は、前記厚さ方向に見て、前記電子部品の角に重なるコーナー部を含み、前記ペースト状接合材は、前記厚さ方向に見て、前記電子部品の中央部から前記コーナー部に向かって少なくとも前記コーナー部まで塗布される。
　本開示の電子装置によれば、たとえば、接合材の剥離や損壊を抑制することができる。また、本開示の電子装置の製造方法によれば、たとえば、接合材の剥離や損壊が抑制された電子装置を製造することができる。
一実施形態にかかる電子装置を示す平面図である。 図１において樹脂部材２を想像線で示した図である。 一実施形態にかかる電子装置を示す底面図である。 一実施形態にかかる電子装置を示す正面図である。 一実施形態にかかる電子装置を示す側面図（左側面図）である。 図２のＶＩ－ＶＩ線に沿う断面図である。 図２のＶＩＩ－ＶＩＩ線に沿う断面図である。 図２のＶＩＩＩ－ＶＩＩＩ線に沿う断面図である。 接合材による接合構造を示す斜視図である。 接合材による接合構造を示す平面図である。 接合材による接合構造を示す側方図である。 電子装置の製造方法の一工程（塗布工程）を示す平面図である。 電子装置の製造方法の一工程（塗布工程）を示す側方図である。 電子装置の製造方法の一工程（載置工程）を示す平面図である。 電子装置の製造方法の一工程（載置工程）を示す側方図である。 変形例にかかる塗布工程を示す平面図である。 変形例にかかる側方被覆部（フィレット部）を示す斜視図である。 図１７の側方被覆部（フィレット部）を示す側方図である。 変形例にかかる側方被覆部（フィレット部）を示す斜視図である。 図１９の側方被覆部（フィレット部）を示す側方図である。 変形例にかかる側方被覆部（フィレット部）を示す平面図である。
　本開示の電子装置および電子装置の製造方法の好ましい実施の形態について、図面を参照して、以下に説明する。
　図１～図１１は、一実施形態にかかる電子装置Ａ１を示している。電子装置Ａ１は、たとえばＱＦＮ（Quad Flat Non-leaded package）と呼ばれるパッケージ構造である。電子装置Ａ１は、電子機器などの回路基板に実装される。電子装置Ａ１は、たとえば平面視矩形状である。電子装置Ａ１は、電子部品１、樹脂部材２、リードフレーム３、接合材４、および、複数の接続部材５を備えている。
　図１は、電子装置Ａ１を示す平面図である。図２は、図１において樹脂部材２を想像線で示した図である。図３は、電子装置Ａ１を示す底面図である。図４は、電子装置Ａ１を示す正面図である。図５は、電子装置Ａ１を示す側面図（左側面図）である。図６は、図２のＶＩ－ＶＩ線に沿う断面図である。図７は、図２のＶＩＩ－ＶＩＩ線に沿う断面図である。図８は、図２のＶＩＩＩ－ＶＩＩＩ線に沿う断面図である。図９は、接合材４による接合構造を示す要部拡大斜視図である。図１０は、接合材４による接合構造を示す要部拡大平面図である。図１１は、接合材４による接合構造を示す要部拡大側方図である。理解の便宜上、図９～図１１においては、電子部品１、リードフレーム３の一部（後述の第１リード３１）および、接合材４を図示している。
　説明の便宜上、互いに直交する３つの方向を、ｘ方向、ｙ方向、ｚ方向と定義する。ｚ 方向は、電子装置Ａ１の厚さ方向である。ｘ方向は、電子装置Ａ１の平面図（図１参照）における左右方向である。ｙ方向は、電子装置Ａ１の平面図（図１参照）における上下方向である。ｘ方向の一方をｘ１方向、ｘ方向の他方をｘ２方向とする。同様に、ｙ方向の一方をｙ１方向、ｙ方向の他方をｙ２方向とし、ｚ方向の一方をｚ１方向、ｚ方向の他方をｚ２方向とする。以下の説明において、「平面視」とは、ｚ方向に見たときをいう。ｚ方向は、「厚さ方向」とも称する。また、ｘ方向は、「第１方向」の一例であり、ｙ方向は、「第２方向」の一例である。
　電子部品１は、電子装置Ａ１の電気的機能を発揮する要素である。電子部品１は、たとえば、集積回路素子、能動機能素子、あるいは、受動機能素子などである。電子部品１は、たとえば半導体材料からなる半導体素子である。半導体材料としては、Ｓｉ（シリコン）、ＳｉＣ（炭化ケイ素）、Ｇｅ（ゲルマニウム）、ＧａＡｓ（ヒ化ガリウム）およびＧａＮ（窒化ガリウム）などがある。本実施形態では、電子部品１は、シリコンからなる。電子部品１は、平面視において、たとえば矩形状である。
　電子部品１は、図２および図６～図１１に示すように、素子主面１１、素子裏面１２および複数の素子側面１３１～１３４を有する。素子主面１１および素子裏面１２は、ｚ方向において離間している。素子主面１１はｚ２方向を向き、素子裏面１２はｚ１方向を向く。素子裏面１２は、リードフレーム３に対向する。素子主面１１には複数の主面電極１１１が形成されている。複数の主面電極１１１はそれぞれ、素子主面１１において露出している。素子裏面１２には裏面電極１２１が形成されている。裏面電極１２１は素子裏面１２において露出している。裏面電極１２１は、素子裏面１２の略全面にわたって形成されている。主面電極１１１および裏面電極１２１のそれぞれの数、配置、形状および平面視寸法は、図２および図６～図８に示す例に限定されず、用いられる電子部品１に応じて、適宜変更される。複数の素子側面１３１～１３４はそれぞれ、ｚ方向において素子主面１１と素子裏面１２とに挟まれており、かつ、素子主面１１および素子裏面１２の双方に繋がる。各素子側面１３１～１３４は、素子裏面１２から起立しており、本実施形態では、直立している。図６、図７および図９などに示すように、素子側面１３１，１３３は、ｘ方向において、離間する。素子側面１３１はｘ１方向を向き、素子側面１３３はｘ２方向を向く。素子側面１３２，１３４は、ｙ方向において離間する。素子側面１３２はｙ１方向を向き、素子側面１３４はｙ２方向を向く。複数の素子側面１３１～１３４がそれぞれ、「第１素子側面」、「第２素子側面」、「第３素子側面」、および「第４素子側面」の一例である。
　電子部品１は、図２および図８～図１１に示すように、複数の稜１４１～１４４を有する。稜１４１は、素子側面１３１と素子側面１３２との交差部分である。稜１４２は、素子側面１３２と素子側面１３３との交差部分である。稜１４３は、素子側面１３３と素子側面１３４との交差部分である。稜１４４は、素子側面１３４と素子側面１３１との交差部分である。各稜１４１～１４４は、ｚ方向に延びている。複数の稜１４１～１４４は、平面視における電子部品１の四隅に対応する。稜１４１が、「稜」の一例であり、各稜１４２～１４４が、「追加の稜」の一例である。
　樹脂部材２は、電子部品１を保護する封止材である。樹脂部材２は、絶縁性の樹脂材料からなる。当該樹脂材料としては、たとえば黒色のエポキシ樹脂が採用される。樹脂部材２は、電子部品１、リードフレーム３の一部および複数の接続部材５を覆っている。樹脂部材２は、平面視において矩形状である。
　樹脂部材２は、樹脂主面２１、樹脂裏面２２および複数の樹脂側面２３１～２３４を有する。樹脂主面２１および樹脂裏面２２は、図４～図８に示すように、ｚ方向に離間する 。樹脂主面２１はｚ２方向を向き、樹脂裏面２２はｚ１方向を向く。複数の樹脂側面２３１～２３４はそれぞれ、ｚ方向において樹脂主面２１および樹脂裏面２２に挟まれており、かつ、樹脂主面２１および樹脂裏面２２の双方に繋がっている。各樹脂側面２３１～２３４は、樹脂裏面２２から起立しており、本実施形態では、直立している。図１～図４に示すように、樹脂側面２３１，２３３は、ｘ方向に離間している。樹脂側面２３１はｘ１方向を向き、樹脂側面２３３はｘ２方向を向く。図１～図３および図５に示すように、樹脂側面２３２，２３４は、ｙ方向に離間している。樹脂側面２３２はｙ１方向を向き、樹脂側面２３４はｙ２方向を向く。
　リードフレーム３は、電子部品１を支持するとともに、電子部品１に導通する。リードフレーム３は、一部が樹脂部材２から露出しており、この露出した部分が電子装置Ａ１における外部端子である。リードフレーム３は、たとえば金属からなる。この金属としては、たとえば、Ｃｕ（銅）、Ｃｕ合金、ニッケル、ニッケル合金、あるいは、４２アロイなどが採用される。本実施形態では、リードフレーム３は、Ｃｕからなる。リードフレーム３は、たとえば金属板にエッチング加工を施すことで形成される。リードフレーム３は、エッチング加工ではなく、金属板に打ち抜き加工や折り曲げ加工などの機械加工を施すことにより形成されてもよい。リードフレーム３は、第１リード３１および複数の第２リード３２を含んでいる。
　第１リード３１は、図１～図３に示すように、平面視において、電子装置Ａ１の中央に配置され、電子装置Ａ１のｘ方向およびｙ方向の両端部まで広がっている。第１リード３１は、図１～図３および図６～図８に示すように、搭載部３１１、複数の端子部３１２および連結部３１３を含んでいる。
　搭載部３１１は、図２、図６～図８および図９に示すように、電子部品１が搭載される。搭載部３１１は、図２および図１０に示すように平面視において、たとえば矩形状である。平面視における搭載部３１１の各辺は、ｘ方向あるいはｙ方向に略平行である。
　搭載部３１１は、図６～図８などに示すように、搭載面３１１ａおよび裏面３１１ｂを有する。搭載面３１１ａおよび裏面３１１ｂは、ｚ方向において離間している。搭載面３１１ａはｚ２方向を向き、裏面３１１ｂはｚ１方向を向く。搭載面３１１ａは、電子部品１（素子裏面１２）に対向する。電子部品１は、搭載面３１１ａ上に搭載されている。搭載面３１１ａにはめっきが施されていてもよい。このめっきの材料は、接合材４の材料に応じて適宜選定される。たとえば、リードフレーム３がＣｕであり、接合材４がはんだである場合、ＡｇめっきあるいはＮｉめっきを搭載面３１１ａに施すことで、はんだ（接合材４）の濡れ性を向上できる。図２および図６～図８に示すように、裏面３１１ｂは、樹脂裏面２２から露出しており、電子装置Ａ１における外部端子になる。図６～図８に示すように裏面３１１ｂは、樹脂裏面２２と面一である。
　複数の端子部３１２は、図１および図２に示すように、平面視において、電子装置Ａ１の４つの角にそれぞれ１つずつ配置されている。各端子部３１２は、平面視において、たとえば矩形状である。
　各端子部３１２は、図３～図５および図８に示すように、主面３１２ａ、裏面３１２ｂおよび２つの端面３１２ｃを有している。各端子部３１２において、主面３１２ａおよび裏面３１２ｂは、ｚ方向に離間している。主面３１２ａは、ｚ２方向を向き、裏面３１２ｂは、ｚ１方向を向く。主面３１２ａは、図８に示すように、搭載面３１１ａと面一である。裏面３１２ｂは、図３および図８に示すように、樹脂裏面２２から露出する。２つの端面３１２ｃはそれぞれ、主面３１２ａおよび裏面３１２ｂに繋がり、主面３１２ａおよび裏面３１２ｂに直交する。２つの端面３１２ｃはそれぞれ、複数の樹脂側面２３１～２ ３４のいずれかから露出する。２つの端面３１２ｃの一方は、ｘ方向外側を向いており、２つの端面３１２ｃの他方は、ｙ方向外側を向いている。裏面３１２ｂおよび２つの端面３１２ｃは、電子装置Ａ１における外部端子である。
　複数の連結部３１３はそれぞれ、図１、図２および図８に示すように、搭載部３１１と各端子部３１２とに繋がっている。各連結部３１３は、図１および図２に示すように、平面視において、搭載部３１１の４つの角からそれぞれ放射状に延びており、各端子部３１２に繋がっている。連結部３１３の厚さ（ｚ方向の寸法）は、たとえば搭載部３１１の厚さの半分程度である。連結部３１３は、たとえばハーフエッチング処理により形成される。
　各連結部３１３は、図８に示すように、主面３１３ａおよび裏面３１３ｂを有する。各連結部３１３において、主面３１３ａおよび裏面３１３ｂは、ｚ方向に離間している。主面３１３ａは、ｚ２方向を向き、裏面３１３ｂは、ｚ１方向を向く。主面３１３ａは、図８に示すように、搭載面３１１ａおよび主面３１２ａと面一である。主面３１３ａおよび裏面３１３ｂは、樹脂部材２に覆われている。
　第１リード３１において、樹脂部材２から露出した部分には、図示しないめっき層が形成されている。電子装置Ａ１においては、当該めっき層は、裏面３１１ｂ、裏面３１２ｂおよび各端面３１２ｃに形成されている。当該めっき層は、第１リード３１の母材よりもはんだ濡れ性が高い材料からなり、たとえばＡｕからなる。当該めっき層は、たとえば置換型の無電解めっきによって形成される。なお、当該めっき層は、形成されていなくてもよい。
　複数の第２リード３２はそれぞれ、図２に示すように、各接続部材５を介して、電子部品１の主面電極１１１に導通する。複数の第２リード３２は、図１～図３に示すように、平面視において、電子装置Ａ１のｘ方向の両端部およびｙ方向の両端部にそれぞれ配置され、互いに離間している。複数の第２リード３２は、第１リード３１から離間している。電子装置Ａ１は、平面視において、樹脂側面２３１に沿って配置された複数の第２リード３２と、樹脂側面２３２に沿って配置された複数の第２リード３２と、樹脂側面２３３に沿って配置された複数の第２リード３２と樹脂側面２３４に沿って配置された複数の第２リード３２とを備えている。樹脂側面２３１に沿って配置された複数の第２リード３２と、樹脂側面２３３に沿って配置された複数の第２リード３２とはそれぞれ、ｙ方向に隣り合う２つの端子部３１２の間に配置されている。樹脂側面２３２に沿って配置された複数の第２リード３２と、樹脂側面２３４に沿って配置された複数の第２リード３２とはそれぞれ、ｘ方向に隣り合う２つの端子部３１２の間に配置されている。各第２リード３２は、端子部３２１および接続部３２２を含む。
　複数の端子部３２１はそれぞれ、図２に示すように、平面視において、たとえば矩形状である。各端子部３２１の一部は、樹脂部材２から露出している。
　各端子部３２１は、図２～図６に示すように、主面３２１ａ、裏面３２１ｂおよび端面３２１ｃを有する。各端子部３２１において、主面３２１ａおよび裏面３２１ｂは、ｚ方向において離間している。主面３２１ａは、ｚ２方向を向き、裏面３２１ｂは、ｚ１方向を向く。裏面３２１ｂは、樹脂裏面２２から露出する。端面３２１ｃは、主面３２１ａおよび裏面３２１ｂに繋がる。端面３２１ｃは、複数の樹脂側面２３１～２３４のいずれかから露出する。裏面３２１ｂと端面３２１ｃとは、電子装置Ａ１における外部端子である。
　複数の接続部３２２はそれぞれ、図２に示すように、端子部３２１から搭載部３１１に 向かって延びている。各接続部３２２には、各接続部材５がそれぞれ接合されている。搭載部３１１のｙ方向の両側の端縁に平行に並ぶ複数の第２リード３２は、ｘ方向の両端側に配置されたものほど、接続部３２２がｙ方向に対してより傾斜している。また、搭載部３１１のｘ方向の両側の端縁に平行に並ぶ複数の第２リード３２は、ｙ方向の両端側に配置されたものほど、接続部３２２がｘ方向に対してより傾斜している。これは、電子部品１の各主面電極１１１と、各第２リード３２の端子部３２１とを接続部材５で接続し易くするためである。ｘ方向およびｙ方向のそれぞれにおいて、最も両端側に配置された（連結部３１３に隣接した）第２リード３２の接続部３２２は、隣接する連結部３１３の延びる方向に略平行に延びている。なお、各接続部３２２は、ｘ方向またはｙ方向に対して傾斜していなくてもよい。
　各第２リード３２において、図６に示すように、接続部３２２の厚さ（ｚ方向の寸法）は、たとえば端子部３２１の厚さの半分程度である。接続部３２２は、たとえばハーフエッチング処理により形成される。各接続部３２２は、主面３２２ａおよび裏面３２２ｂを有する。主面３２２ａおよび裏面３２２ｂは、ｚ方向において離間している。主面３２２ａは、ｚ２方向を向き、裏面３２２ｂは、ｚ１方向を向く。主面３２２ａは、接続部材５が接合される面である。主面３２１ａと主面３２２ａとは、互いに面一となっている。裏面３２２ｂは、樹脂部材２に覆われている。なお、接続部３２２の厚さが、端子部３２１の厚さと同じであってもよい。この場合、裏面３２１ｂと裏面３２２ｂとが互いに面一となり、裏面３２２ｂは、樹脂部材２（樹脂裏面２２）から露出する。
　各第２リード３２において、樹脂部材２から露出した部分には、図示しないめっき層が形成されている。電子装置Ａ１においては、当該めっき層は、裏面３２１ｂおよび端面３２１ｃに形成される。当該めっき層は、第１リード３１のめっき層と同様であって、たとえばＡｕからなり、置換型の無電解めっきによって形成される。なお、当該めっき層は、形成されていなくてもよい。
　接合材４は、電子部品１をリードフレーム３に接合する。接合材４は、たとえば焼結銀である。接合材４は、焼結銀に限らず、焼結銅などの他の焼結金属であってもよいし、はんだあるいは銀ペーストなど他の導電性接合材であってもよい。また、接合材４は、導電性接合材に限らず、絶縁性接合材であってもよい。ただし、接合材４が絶縁性接合材である場合は、電子部品１に裏面電極１２１が設けられていない場合か、あるいは、電子部品１の裏面電極１２１と搭載部３１１との接合材４を介した導通が不要な場合に限られる。接合材４は、電子部品１と搭載部３１１（第１リード３１）との間に介在する。接合材４は、素子裏面１２および搭載面３１１ａに接している。接合材４を介して、裏面電極１２１と搭載部３１１とが導通する。接合材４は、基部４１およびフィレット部４２を含んでいる。
　基部４１は、図９に示すように、ｚ方向において、電子部品１と搭載部３１１とに挟まれている。基部４１は、平面視において、電子部品１と完全に重なる。基部４１は、素子裏面１２の全面に接している。基部４１は、平面視において、たとえば矩形状である。基部４１は、略均等な厚さ（ｚ方向の寸法）となっている。
　フィレット部４２は、図９および図１１に示すように、基部４１に繋がり、かつ、平面視において電子部品１の外側に形成されている。フィレット部４２は、図１０に示すように、平面視において、電子部品１の全周にわたって形成されている。フィレット部４２は、図９および図１１に示すように、基部４１から各素子側面１３１～１３４に沿ってｚ方向上方に突き出ている。フィレット部４２は、複数の側方被覆部４３１～４３４および複数の稜被覆部４４１～４４４を含んでいる。本実施形態では、稜被覆部４４１が、「稜被覆部」の一例であり、各稜被覆部４４２～４４４が、「追加の稜被覆部」の一例である。また、側方被覆部４３１が、「第１被覆部」の一例であり、側方被覆部４３２が、「第２被覆部」の一例である。
　稜被覆部４４１は、図８～図１１に示すように、稜１４１の少なくとも一部を覆う。本実施形態では、稜被覆部４４１は、稜１４１のｚ方向下方側の端部を覆い、稜１４１のｚ方向上方側の端部を覆っていない。稜被覆部４４１は、図１０に示すように、側方被覆部４３１と側方被覆部４３２とを繋ぐ。
　稜被覆部４４２は、図９および図１０に示すように、稜１４２の少なくとも一部を覆う。本実施形態では、稜被覆部４４２は、稜１４２のｚ方向下方側の端部を覆い、稜１４２のｚ方向上方側の端部を覆っていない。稜被覆部４４２は、図１０に示すように、側方被覆部４３２と側方被覆部４３３とを繋ぐ。
　稜被覆部４４３は、図１０に示すように、稜１４３の少なくとも一部を覆う。本実施形態では、稜被覆部４４３は、稜１４３のｚ方向下方側の端部を覆い、稜１４３のｚ方向上方側の端部を覆っていない。稜被覆部４４３は、図１０に示すように、側方被覆部４３３と側方被覆部４３４とを繋ぐ。
　稜被覆部４４４は、図９および図１０に示すように、稜１４４の少なくとも一部を覆う。本実施形態では、稜被覆部４４４は、稜１４４のｚ方向下方側の端部を覆い、稜１４４のｚ方向上方側の端部を覆っていない。稜被覆部４４４は、図１０に示すように、側方被覆部４３４と側方被覆部４３１とを繋ぐ。
　側方被覆部４３１は、図９～図１１に示すように、素子側面１３１の少なくとも一部を覆う。素子側面１３１において、ｚ２方向側の端縁、つまり、素子主面１１側の端縁は、ｘ方向に見て、側方被覆部４３１から露出しており、ｚ１方向側の端縁、つまり、素子裏面１２側の端縁は、ｘ方向に見て、側方被覆部４３１に覆われている。側方被覆部４３１は、図１０に示すように、稜被覆部４４４および稜被覆部４４１に挟まれ、これらに繋がっている。側方被覆部４３１は、図１０に示すように、稜被覆部４４４および稜被覆部４４１とｙ方向に並んでいる。
　側方被覆部４３２は、図９および図１０に示すように、素子側面１３２の少なくとも一部を覆う。素子側面１３２において、ｚ２方向側の端縁、つまり、素子主面１１側の端縁は、ｙ方向に見て、側方被覆部４３２から露出しており、ｚ１方向側の端縁、つまり、素子裏面１２側の端縁は、ｙ方向に見て、側方被覆部４３２に覆われている。側方被覆部４３２は、図１０に示すように、稜被覆部４４１および稜被覆部４４２に挟まれ、これらに繋がっている。側方被覆部４３２は、図１０に示すように、稜被覆部４４１および稜被覆部４４２とｘ方向に並んでいる。
　側方被覆部４３３は、図１０に示すように、素子側面１３３の少なくとも一部を覆う。素子側面１３３において、ｚ２方向側の端縁、つまり、素子主面１１側の端縁は、ｘ方向に見て、側方被覆部４３３から露出しており、ｚ１方向側の端縁、つまり、素子裏面１２側の端縁は、ｘ方向に見て、側方被覆部４３３に覆われている。側方被覆部４３３は、図１０に示すように、稜被覆部４４２および稜被覆部４４３に挟まれ、これらに繋がっている。側方被覆部４３３は、図１０に示すように、稜被覆部４４２および稜被覆部４４３とｙ方向に並んでいる。
　側方被覆部４３４は、図１０に示すように、素子側面１３４の少なくとも一部を覆う。素子側面１３４において、ｚ２方向側の端縁、つまり、素子主面１１側の端縁は、ｙ方向 に見て、側方被覆部４３４から露出しており、ｚ１方向側の端縁、つまり、素子裏面１２側の端縁は、ｙ方向に見て、側方被覆部４３４に覆われている。側方被覆部４３４は、図１０に示すように、稜被覆部４４３および稜被覆部４４４に挟まれ、これらに繋がっている。側方被覆部４３４は、図１０に示すように、稜被覆部４４３および稜被覆部４４４とｘ方向に並んでいる。
　図９および図１１に示すように、各側方被覆部４３１～４３４は、各長手方向における中央部が、各長手方向における両端縁部よりも、ｚ１方向に窪んでいる。このため、各側方被覆部４３１～４３４において、各長手方向における中央部のｚ方向の寸法ｄ１１は、各長手方向における各端縁部のｚ方向の寸法ｄ１２よりも小さい。図１１には、側方被覆部４３１における各寸法ｄ１１，ｄ１２が示されている。また、各側方被覆部４３１～４３４は、各長手方向における中央部と、各長手方向における各端縁部との間にそれぞれ隆起部４３９が形成されている。隆起部４３９は、ｚ２方向に、つまり、素子主面１１側に隆起している。隆起部４３９は、各側方被覆部４３１～４３４において、各側方被覆部４３１～４３４のうち最もｚ方向の寸法が大きい。図１１には、側方被覆部４３１における隆起部４３９が示されている。各側方被覆部４３１，４３３における長手方向は、ｙ方向であり、各側方被覆部４３２，４３４における長手方向は、ｘ方向である。なお、各側方被覆部４３１～４３４における各寸法ｄ１１，ｄ１２は、複数の側方被覆部４３１～４３４でそれぞれ同じであってもよいし、差があってもよい。
　図１０に示すように、各側方被覆部４３１～４３４は、平面視において、各長手方向における中央部が、各長手方向における両端縁部よりも、各素子側面１３１～１３４側に窪んでいる。
　図６および図７に示すように、各側方被覆部４３１～４３４においては、傾斜度α１１（図７参照）は、傾斜度α１２（図６参照）よりも大きい。傾斜度α１１は、図７に示すように、搭載面３１１ａと、各側方被覆部４３１～４３４の各長手方向における各端縁部とがなす角度であり、搭載面３１１ａに対する当該端縁部の表面の傾斜度合いである。傾斜度α１２は、図６に示すように、搭載面３１１ａと、各側方被覆部４３１～４３４の各長手方向における中央部とがなす角度であり、搭載面３１１ａに対する当該中央部の表面の傾斜度合いである。各側方被覆部４３１～４３４は、各長手方向において、中央部から各端縁部に向かうほど、傾斜度α１２から傾斜度α１１に徐々に変化する。なお、傾斜度α１１は、傾斜度α１２と同じであってもよいし、傾斜度α１２よりも小さくてもよい。
　各側方被覆部４３１，４３３は、図６および図７に示す例では、ｙ方向に見て、その表面が凸状に湾曲しているが、これに限定されず、平坦な面であってもよいし、凹状に湾曲していてもよい。あるいは、凸状に湾曲する部分、凹状に湾曲する部分および平坦な部分の２つ以上が混在していてもよい。同様に、各側方被覆部４３２，４３４は、ｘ方向に見て、その表面が凸状に湾曲しているが、これに限定されず、平坦な面であってもよいし、凹状に湾曲していてもよい。あるいは、凸状に湾曲する部分、凹状に湾曲する部分および平坦な部分の２つ以上が混在していてもよい。
　複数の接続部材５は、互いに離間した２つの部位間を導通させる。各接続部材５は、たとえばボンディングワイヤである。各接続部材５は、ボンディングワイヤではなく、ボンディングリボンや板状のリード部材などであってもよい。複数の接続部材５の各構成材料は、たとえばＡｕを含み金属、Ａｌを含む金属あるいはＣｕを含む金属などのいずれであってもよい。各接続部材５は、たとえば周知のワイヤボンダによって形成される。各接続部材５は、図２に示すように、電子部品１の主面電極１１１と各第２リード３２の接続部３２２（主面３２２ａ）とにそれぞれ接合され、主面電極１１１と第２リード３２とを導通させる。
　次に、電子装置Ａ１の製造方法について、図１２～図１５を参照して説明する。図１２および図１４は、電子装置Ａ１の製造方法の一工程を示す要部拡大平面図である。図１３および図１５は、電子装置Ａ１の製造方法の一工程を示す要部拡大側方図である。
　まず、リードフレーム３を準備する。具体的には、Ｃｕを含む金属板にエッチング加工を施し、複数のリードフレーム３を形成する。各リードフレーム３は、第１リード３１および複数の第２リード３２を備えている。第１リード３１は、搭載部３１１、複数の端子部３１２および複数の連結部３１３を含んでいる。搭載部３１１は、ｚ２方向を向く搭載面３１１ａを有する。各第２リード３２は、端子部３２１および接続部３２２を含んでいる。リードフレーム３を準備する工程（準備工程）においては、形成された複数のリードフレーム３は、互いに連続している。
　次に、図１２および図１３に示すように、搭載部３１１の搭載面３１１ａに、ペースト状接合材４９を塗布する。ペースト状接合材４９は、たとえば焼結型の金属ペースト（銀ペーストあるいは銅ペーストなど）である。ペースト状接合材４９を塗布する工程（塗布工程）では、たとえばディスペンサーを用いる。搭載面３１１ａは、図１２および図１３に示すように、電子部品１が接合される接合領域３９１を含む。接合領域３９１は、搭載面３１１ａのうち、電子部品１が接合された状態において、平面視で電子部品１のすべてに重なる領域である。よって、平面視において、接合領域３９１は、電子部品１と略同形（本実施形態では矩形状）であり、かつ、電子部品１と同じ大きさである。接合領域３９１は、４つのコーナー部３９２を含んでいる。４つのコーナー部３９２は、電子部品１が接合された状態において、平面視で電子部品１の四隅に重なる部分である。塗布工程では、たとえば、図１２に示す軌道Ｌ１，Ｌ２に沿って、直線状にペースト状接合材４９を塗布する。軌道Ｌ１，Ｌ２はそれぞれ、ディスペンサーによるペースト状接合材４９の塗布軌道である。軌道Ｌ１，Ｌ２はそれぞれ、接合領域３９１の対角線上に位置する一対のコーナー部３９２の一方から他方まで中心３９３を通る直線状である。図１２に示す例では、各軌道Ｌ１，Ｌ２の起点および終点は、各コーナー部３９２に重なるが、各コーナー部３９２よりも接合領域３９１の平面視外側に設定してもよい。ペースト状接合材４９の塗布軌道は、これに限定されない。たとえば、平面視において、接合領域３９１の中心３９３から４つのコーナー部３９２のそれぞれまで放射状にペースト状接合材４９を塗布してもよい。
　塗布されたペースト状接合材４９は、図１２および図１３に示すように、４つのコーナー部３９２のすべてを完全に覆っており、かつ、平面視において、Ｘ字状に形成されている。本実施形態では、ペースト状接合材４９を塗布する軌道Ｌ１，Ｌ２は、コーナー部３９２を起点および終点としていため、塗布されたペースト状接合材４９は、このコーナー部３９２よりも接合領域３９１の外側まで形成されている。また、ペースト状接合材４９には、図１３に示すように、側方（ｘ方向あるいはｙ方向）から見て、突出部４９１が形成されている。突出部４９１は、ペースト状接合材４９のうち、ｚ２方向に盛り上がった部分であり、接合領域３９１の中心３９３上に形成されている。突出部４９１は、ペースト状接合材４９を軌道Ｌ１，Ｌ２に沿って塗布した際、２つの軌道Ｌ１，Ｌ２が交差していることから、形成される。塗布されたペースト状接合材４９は、線幅Ｗ１（図１２参照）がたとえば２００μｍ以上３００μｍ以下であり、厚さ（ｚ方向の寸法）がたとえば１００μｍ以上１５０μｍ以下（突出部４９１を除く）である。なお、ペースト状接合材４９は、各軌道Ｌ１，Ｌ２の進行方向に見て、半円状に湾曲しており、上記厚さは最大部分（突出部４９１を除く）の大きさである。
　次に、図１４および図１５に示すように、ペースト状接合材４９上に電子部品１を載置する。電子部品１を載置する工程（載置工程）では、たとえば周知のダイボンダが用いら れる。載置工程により、電子部品１がペースト状接合材４９上に載置されると、電子部品１の重さによって、ペースト状接合材４９が押し広げられる。なお、ペースト状接合材４９は、電子部品１の重さだけでなく、ダイボンダによって電子部品１を押し付けた際の押圧力によって押し広げられてもよい。押し広げられたペースト状接合材４９は、図１４および図１５に示すように、接合領域３９１の全領域を覆い、かつ、接合領域３９１の全周にわたって外方に突き出た形状になる。このとき、ペースト状接合材４９は、上記接合材４と略同じ形状になる。
　次に、ペースト状接合材４９を固化し、接合材４を形成する。本実施形態では、ペースト状接合材４９として焼結型の金属ペーストを用いていることから、ペースト状接合材４９を固化する工程（固化工程）では、ペースト状接合材４９を焼結により固化する。この焼結により、ペースト状接合材４９中の溶媒が揮発・消失しつつ、ペースト状接合材４９中の金属粒子（銀粒子あるいは銅粒子など）同士が結合することで、ペースト状接合材４９が固化し、接合材４が形成される。固化工程は、ペースト状接合材４９の素材に応じて、適宜変更される。たとえばペースト状接合材４９が熱硬化型の金属ペーストの場合、固化工程では、ペースト状接合材４９を加熱する。この加熱により、金属ペースト中の樹脂材料が硬化することで、ペースト状接合材４９が固化し、接合材４が形成される。本開示において、「金属ペースト」とは、たとえば、金属の微粒子とエポキシ樹脂などの微粒子（バインダー）と溶剤とから構成される導電材料をいう。
　次に、複数の接続部材５を形成する。複数の接続部材５はそれぞれ、たとえば周知のワイヤボンダによって、形成される。各接続部材５は、一端が電子部品１の主面電極１１１に接合され、他端が各第２リード３２の接続部３２２（主面３２２ａ）に接合される。
　次に、樹脂部材２を形成する。樹脂部材２を形成する工程（樹脂形成工程）では、たとえば周知のトランスファー成形機または圧縮成形機を用いる。樹脂部材２としては、たとえば絶縁性のエポキシ樹脂を用いる。形成された樹脂部材２から、リードフレーム３が部分的に露出している。
　その後、電子部品１毎に樹脂部材２およびリードフレーム３を切断し、個片化する。以上の工程を経ることで、電子装置Ａ１が形成される。なお、上述の製造方法は、一例であって、これに限定されない。
　電子装置Ａ１および電子装置Ａ１の製造方法の作用および効果は、次の通りである。
　電子装置Ａ１では、電子部品１をリードフレーム３に接合する接合材４は、フィレット部４２を含んでいる。フィレット部４２は、稜１４１の少なくとも一部を覆う稜被覆部４４１を含んでいる。稜１４１は、素子側面１３１と素子側面１３２との交差部分であり、平面視における電子部品１の四隅の一つに相当する。この構成によると、電子部品１の稜１４１（電子部品１の下方角部）が接合材４（フィレット部４２の稜被覆部４４１）で保護される。電子部品１への通電時に発生する熱により、電子部品１とリードフレーム３との線膨張係数の差に起因する熱応力が接合材４に加わる。この接合材４にかかる熱応力は、電子部品１の下方側四隅付近が最も大きいので、接合材４の剥離や損壊などは、電子部品１の稜１４１付近から進行し易い。特に、従来の電子装置においては、稜１４１が接合材４から露出しており、電子部品１の下方側四隅付近での接合材４の剥離や損壊などが顕著であった。そこで、電子装置Ａ１では、稜被覆部４４１によって稜１４１を保護することで、稜１４１付近における接合材４の剥離や損壊などに対する耐性を向上させることができる。したがって、電子装置Ａ１によれば、接合材４の剥離や損壊などを抑制することができる。よって、電子装置Ａ１の信頼性を向上させることができる。
　電子装置Ａ１では、接合材４のフィレット部４２は、複数の稜被覆部４４１～４４４を含んでいる。複数の稜被覆部４４１～４４４はそれぞれ、電子部品１の複数の稜１４１～１４４の下方側の各端縁部分をそれぞれ覆っている。つまり、電子部品１の下方側四隅がフィレット部４２で覆われている。この構成によると、電子部品１の下方側四隅の付近における接合材４の剥離や損壊などに対する耐性を向上させることができる。したがって、電子装置Ａ１によれば、接合材４の剥離や損壊などを抑制することができる。
　電子装置Ａ１では、接合材４は、基部４１を含んでいる。基部４１は、電子部品１と搭載部３１１とに挟まれており、電子部品１と完全に重なっている。基部４１は、素子裏面１２の全面に接している。従来の電子装置では、電子部品１と搭載部３１１との間において、接合材４が充填されない部分があった。つまり、電子部品１の素子裏面１２には、接合材４に接していない領域があった。この領域において、電子部品１に微小な傷（例えば、素子裏面１２の端縁に存在するチッピングなど）がついている場合、この傷を起点に、電子部品１の破壊（亀裂など）が電子部品１の内部に進行することがあった。一方、電子装置Ａ１では、素子裏面１２の全面が接合材４（基部４１）に接しているため、素子裏面１２は接合材４（基部４１）によって保護される。したがって、電子装置Ａ１によれば、電子部品１の素子裏面１２に微小な傷がついていても、この傷を起点とする電子部品１の破壊の進行を抑制することができる。
　電子装置Ａ１では、接合材４は、たとえば焼結銀からなる。焼結銀は、はんだと比べて延性が低い。そのため、接合材４が焼結銀からなる場合、接合材４がはんだからなる場合よりも、接合材４に加わる熱応力が大きくなる。これは、はんだが、その延性により、焼結銀よりも熱応力を緩和させることができるからである。つまり、接合材４が焼結銀からなる場合、接合材４がはんだからなる場合よりも、熱応力による、接合材４の剥離や破壊が生じ易い。したがって、接合材４が焼結銀からなる場合、上記のようにフィレット部４２（稜被覆部４４１）で稜１４１を保護することは、接合材４がはんだからなる場合よりも、接合材４の剥離や破壊を抑制する上で、有効である。
　電子装置Ａ１では、電子部品１はたとえばシリコンからなる半導体素子であり、リードフレーム３はたとえばＣｕからなる。この場合、シリコンとＣｕとの線膨張係数の差が大きいため、接合材４に加わる熱応力が大きくなる。つまり、熱応力による、接合材４の剥離や損壊が生じ易くなる。したがって、接合材４を用いてシリコンからなる電子部品１をＣｕからなる搭載部３１１（リードフレーム３）に接合する場合、上記のようにフィレット部４２（稜被覆部４４１）で稜１４１を保護することは、接合材４の剥離や破壊を抑制する上で、有効である。
　電子装置Ａ１の製造方法では、塗布工程において、ペースト状接合材４９を、接合領域３９１の各コーナー部３９２まで塗布することで、接合領域３９１の四隅をペースト状接合材４９で覆わせている。これにより、載置工程によって電子部品１をペースト状接合材４９に載置した際、ペースト状接合材４９は、電子部品１の各稜１４１～１４４のそれぞれ少なくとも一部ずつを覆うように広がる。つまり、接合材４には、稜被覆部４４１を含むフィレット部４２が形成される。したがって、本開示の製造方法によれば、接合材４の剥離や破壊が抑制された電子装置Ａ１を製造できる。
　電子装置Ａ１の製造方法では、塗布工程において、ペースト状接合材４９が平面視においてＸ字状に塗布されている。本実施形態と異なる塗布工程において、接合領域３９１の全面あるいは全面よりも広範囲に、ペースト状接合材４９を塗布することで、各稜被覆部４４１～４４４を含むフィレット部４２を形成することが考えられる。しかしながら、この場合、ペースト状接合材４９は、載置工程によって電子部品１が載置されると、平面視において、電子部品１の外側に大きく広がる可能性がある。この場合、ペースト状接合材 ４９が意図せぬ場所に流出してしまい、たとえば意図せぬ短絡の発生が懸念される。意図せぬ短絡には、電子部品１の主面電極１１１同士の短絡が含まれる。また、無駄に広がった部分の材料費によってコスト増大が懸念される。そこで、本開示の製造方法では、ペースト状接合材４９をＸ字状に塗布することで、各稜被覆部４４１～４４４を含むフィレット部４２を形成しつつ、上記した意図せぬ短絡の発生やコスト増大を抑制することができる。
　上記実施形態の塗布工程では、ペースト状接合材４９を、軌道Ｌ１，Ｌ２に沿って直線状に塗布した場合を示したがこれに限定されない。たとえば図１６に示すように、ドット状の複数のペースト状接合材４９を、Ｘ字状に塗布してもよい。理解の便宜上、図１６において、上記実施形態におけるペースト状接合材４９（図１２参照）を想像線で示しておく。各ペースト状接合材４９は、たとえば半球体状である。この場合においても、図９～図１１と同様の接合材４が形成される。ペースト状接合材４９の他の塗布の態様としては、第１に、大型の矩形の平面形状（典型的には大型の正方形）を有する電子部品１において使用される、「＊（アスタリスク）」字状、「※（米印）」状の態様がある。「※」状とは、「Ｘ」字状に配置された４本の線分と、この４本の線分においてｘ方向またはｙ方向にそれぞれ隣り合う２つの線分の間にそれぞれ配置された４つの「・（ドット）」と、によって形成された形状である。第２に、横長の矩形の電子部品１において使用される、長手方向に沿って「＞」「－」「＜」の順に接してまたは近接して並ぶ形状の態様がある。
　電子装置Ａ１において、各側方被覆部４３１～４３４の形状は、上記したものに限定されない。たとえば図１７および図１８に示すように、各側方被覆部４３１～４３４に隆起部４３９（図１１参照）が形成されていなくてもよい。また、たとえば図１９および図２０に示すように、各側方被覆部４３１～４３４は、各長手方向における中央部が、各長手方向における両端縁部よりも、ｚ１方向に窪んでおらず、寸法ｄ１１と寸法ｄ１２とが略同じであってもよい。さらに、たとえば図２１に示すように、各側方被覆部４３１～４３４は、平面視において、各長手方向における中央部が、各長手方向における両端縁部よりも、各素子側面１３１～１３４側に窪んでいなくてもよい。あるいは、平面視において、各長手方向における中央部が、各長手方向における両端縁部よりも、各素子側面１３１～１３４と反対側に突き出ていてもよい。これらの変形例にかかる各側方被覆部４３１～４３４は、塗布工程におけるペースト状接合材４９の塗布量、塗布軌道、および、線幅Ｗ１や、載置工程におけるペースト状接合材４９の広がり方、ペースト状接合材４９の搭載部３１１（リードフレーム３）に対する濡れ性などを適宜調整することで、形成される。
　上記実施形態では、電子装置Ａ１が、ＱＦＮ型のパッケージ構造である場合を示したが、これに限定されない。たとえば、ＴＯ（Transistor Outline）パッケージ型、ＳＯＰ（Small Outline Package）型、ＱＦＰ（Quad Flat Package）型、ＢＧＡ（Ball Grid Array）型などその他のパッケージ構造であってもよい。この際、これらのパッケージ構造に応じて、リードフレーム３の形状は適宜変更される。
　上記実施形態では、電子装置Ａ１が、リードフレーム型である場合を示したが、これに限定されない。たとえば、インタポーザ型であってもよい。つまり、電子部品１が、リードフレーム３の代わりに、たとえばシリコン基板、セラミック基板、あるいは、ガラス基板などに接合される構造のものであってもよい。その他、ある支持部材（搭載部）に、接合材４を介して、電子部品１を接合する構造において、本開示の構成が適用されうる。
　本開示にかかる電子装置および電子装置の製造方法は、上記した実施形態に限定されるものではない。本開示の電子装置の各部の具体的な構成、および、本開示の電子装置の製造方法の各工程の具体的な処理は、種々に設計変更自在である。たとえば、本開示にかかる電子装置および電子装置の製造方法は、以下の付記に関する実施形態を含む。
［付記１］
　厚さ方向において離間する素子主面および素子裏面を有する電子部品と、
　前記素子裏面に対向する搭載面を有し、前記電子部品が搭載された搭載部と、
　前記電子部品を前記搭載部に接合する接合材と、
を備えており、
　前記接合材は、前記厚さ方向において前記電子部品と前記搭載部とに挟まれた基部と、前記基部に繋がり、かつ、前記厚さ方向に見て前記電子部品の外側に形成されたフィレット部とを含み、
　前記電子部品は、各々が前記素子主面および前記素子裏面に繋がる第１素子側面および第２素子側面と、前記第１素子側面と前記第２素子側面との交差部分であって前記厚さ方向に延びる稜と、を含み、
　前記フィレット部は、前記稜の少なくとも一部を覆う稜被覆部を含む、電子装置。
［付記２］
　前記フィレット部は、前記第１素子側面の少なくとも一部を覆う第１被覆部、および、前記第２素子側面の少なくとも一部を覆う第２被覆部をさらに含み、
　前記第１被覆部と前記第２被覆部はそれぞれ、前記稜被覆部に繋がる、付記１に記載の電子装置。
［付記３］
　前記第１素子側面においては、前記素子主面に繋がる端縁が、前記第１素子側面に直交する第１方向に見て、前記第１被覆部から露出し、
　前記第２素子側面においては、前記素子主面に繋がる端縁が、前記第２素子側面に直交する第２方向に見て、前記第２被覆部から露出する、付記２に記載の電子装置。
［付記４］
　前記電子部品は、前記厚さ方向に見て矩形状であり、
　前記厚さ方向、前記第１方向および前記第２方向は、互いに直交する、付記３に記載の電子装置。
［付記５］
　前記電子部品は、第３素子側面、第４素子側面、および、複数の追加の稜をさらに含み、
　前記第３素子側面は、前記素子主面および前記素子裏面に繋がり、かつ、前記第１方向において、前記第１素子側面と離間し、
　前記第４素子側面は、前記素子主面および前記素子裏面に繋がり、かつ、前記第２方向において、前記第２素子側面と離間し、
　前記複数の追加の稜は、前記第１素子側面と前記第４素子側面とが交わったところ、前記第２素子側面と前記第３素子側面とが交わったところ、および、前記第３素子側面と前記第４素子側面とが交わったところにそれぞれ生じ、かつ、各々が前記厚さ方向に延びており、
　前記フィレット部は、前記複数の追加の稜を覆う複数の追加の稜被覆部をさらに含む、付記４に記載の電子装置。
［付記６］
　前記第１被覆部においては、前記第２方向における中央部の前記厚さ方向の寸法が、前記稜被覆部に繋がる端縁部の前記厚さ方向の寸法よりも小さい、付記４または付記５に記載の電子装置。
［付記７］
　前記第１被覆部は、前記第２方向における中央部と、前記稜被覆部に繋がる端縁部との間において、前記素子主面側に隆起した隆起部を有する、付記４ないし付記６のいずれか１つに記載の電子装置。
［付記８］
　前記第１被覆部においては、前記厚さ方向に見て、前記第２方向における中央部が前記第１素子側面側に窪んでいる、付記４ないし付記７のいずれか１つに記載の電子装置。
［付記９］
　前記第１被覆部においては、前記稜被覆部に繋がる端縁部の前記搭載面に対する傾斜度が、前記第２方向における中央部の前記搭載面に対する傾斜度よりも大きい、付記４ないし付記８のいずれか１つに記載の電子装置。
［付記１０］
　前記第２被覆部においては、前記第１方向における中央部の前記厚さ方向の寸法が、前記稜被覆部に繋がる端縁部の前記厚さ方向の寸法よりも小さい、付記４ないし付記９のいずれか１つに記載の電子装置。
［付記１１］
　前記第２被覆部は、前記第１方向における中央部と、前記稜被覆部に繋がる端縁部との間において、前記素子主面側に隆起した隆起部を有する、付記４ないし付記１０のいずれか１つに記載の電子装置。
［付記１２］
　前記第２被覆部においては、前記厚さ方向に見て、前記第１方向における中央部が前記第２素子側面側に窪んでいる、付記４ないし付記１１のいずれかに記載の電子装置。
［付記１３］
　前記第２被覆部は、前記稜被覆部に繋がる端縁部の前記搭載面に対する傾斜度が、前記第１方向における中央部の前記搭載面に対する傾斜度よりも大きい、付記４ないし付記１２のいずれかに記載の電子装置。
［付記１４］
　前記フィレット部は、前記厚さ方向に見て、前記電子部品の全周にわたって形成されている、付記１ないし付記１３のいずれかに記載の電子装置。
［付記１５］
　前記電子部品は、半導体材料からなる、付記１ないし付記１４のいずれかに記載の電子装置。
［付記１６］
　前記電子部品は、前記素子主面に主面電極が形成されており、
　前記搭載部は、リードフレームの一部であり、
　前記リードフレームは、前記主面電極に導通し、かつ、前記搭載部から離間する端子部をさらに含む、付記１ないし付記１５のいずれかに記載の電子装置。
［付記１７］
　前記リードフレームは、構成材料がＣｕを含む金属である、付記１６に記載の電子装置。
［付記１８］
　前記電子部品は、前記素子裏面に裏面電極が形成されており、
　前記裏面電極は、前記接合材を介して、前記搭載部に導通する、付記１ないし付記１７のいずれかに記載の電子装置。
［付記１９］
　前記接合材は、焼結銀からなる、付記１ないし付記１８のいずれかに記載の電子装置。
［付記２０］
　厚さ方向において離間する素子主面および素子裏面を有する電子部品と、
　前記素子裏面に対向する搭載面を有し、前記電子部品が搭載された搭載部と、
　前記電子部品を前記搭載部に接合する接合材と、
を備えた電子装置の製造方法であって、
　前記搭載面にペースト状接合材を塗布する塗布工程と、
　前記ペースト状接合材上に前記電子部品を載置する載置工程と、
　前記ペースト状接合材を固化し、前記接合材を形成する固化工程と、
を含み、
　前記搭載部は、前記電子部品が接合される接合領域を含み、
　前記接合領域は、前記厚さ方向に見て、前記電子部品の角に重なるコーナー部を含み、
　前記ペースト状接合材は、前記厚さ方向に見て、前記電子部品の中央部から前記コーナー部に向かって少なくとも前記コーナー部まで塗布される、電子装置の製造方法。
Ａ１　　　：電子装置
１　　　　：電子部品
１１　　　：素子主面
１１１　　：主面電極
１２　　　：素子裏面
１２１　　：裏面電極
１３１～１３４：素子側面
１４１～１４４：稜
２　　　　：樹脂部材
２１　　　：樹脂主面
２２　　　：樹脂裏面
２３１～２３４：樹脂側面
３　　　　：リードフレーム
３１　　　：第１リード
３１１　　：搭載部
３１１ａ　：搭載面
３９１　　：接合領域
３９２　　：コーナー部
３９３　　：中心
３１１ｂ　：裏面
３１２　　：端子部
３１２ａ　：主面
３１２ｂ　：裏面
３１２ｃ　：端面
３１３　　：連結部
３１３ａ　：主面
３１３ｂ　：裏面
３２　　　：第２リード
３２１　　：端子部
３２１ａ　：主面
３２１ｂ　：裏面
３２１ｃ　：端面
３２２　　：接続部
３２２ａ　：主面
３２２ｂ　：裏面
４　　　　：接合材
４１　　　：基部
４２　　　：フィレット部
４３１～４３４：側方被覆部
４３９　　：隆起部
４４１～４４４：稜被覆部
４９　　　：ペースト状接合材
４９１　　：突出部
５　　　　：接続部材

Claims (20)

  1. 　厚さ方向において離間する素子主面および素子裏面を有する電子部品と、
    　前記素子裏面に対向する搭載面を有し、前記電子部品が搭載された搭載部と、
    　前記電子部品を前記搭載部に接合する接合材と、
    を備えており、
    　前記接合材は、前記厚さ方向において前記電子部品と前記搭載部とに挟まれた基部と、前記基部に繋がり、かつ、前記厚さ方向に見て前記電子部品の外側に形成されたフィレット部とを含み、
    　前記電子部品は、各々が前記素子主面および前記素子裏面に繋がる第１素子側面および第２素子側面と、前記第１素子側面と前記第２素子側面との交差部分であって前記厚さ方向に延びる稜と、を含み、
    　前記フィレット部は、前記稜の少なくとも一部を覆う稜被覆部を含む、
    電子装置。
  2. 　前記フィレット部は、前記第１素子側面の少なくとも一部を覆う第１被覆部、および、前記第２素子側面の少なくとも一部を覆う第２被覆部をさらに含み、
    　前記第１被覆部と前記第２被覆部はそれぞれ、前記稜被覆部に繋がる、
    請求項１に記載の電子装置。
  3. 　前記第１素子側面においては、前記素子主面に繋がる端縁が、前記第１素子側面に直交する第１方向に見て、前記第１被覆部から露出し、
    　前記第２素子側面においては、前記素子主面に繋がる端縁が、前記第２素子側面に直交する第２方向に見て、前記第２被覆部から露出する、
    請求項２に記載の電子装置。
  4. 　前記電子部品は、前記厚さ方向に見て矩形状であり、
    　前記厚さ方向、前記第１方向および前記第２方向は、互いに直交する、
    請求項３に記載の電子装置。
  5. 　前記電子部品は、第３素子側面、第４素子側面、および、複数の追加の稜をさらに含み、
    　前記第３素子側面は、前記素子主面および前記素子裏面に繋がり、かつ、前記第１方向において、前記第１素子側面と離間し、
    　前記第４素子側面は、前記素子主面および前記素子裏面に繋がり、かつ、前記第２方向において、前記第２素子側面と離間し、
    　前記複数の追加の稜は、前記第１素子側面と前記第４素子側面とが交わったところ、前記第２素子側面と前記第３素子側面とが交わったところ、および、前記第３素子側面と前記第４素子側面とが交わったところにそれぞれ生じ、かつ、各々が前記厚さ方向に延びており、
    　前記フィレット部は、前記複数の追加の稜を覆う複数の追加の稜被覆部をさらに含む、請求項４に記載の電子装置。
  6. 　前記第１被覆部においては、前記第２方向における中央部の前記厚さ方向の寸法が、前記稜被覆部に繋がる端縁部の前記厚さ方向の寸法よりも小さい、
    請求項４または請求項５に記載の電子装置。
  7. 　前記第１被覆部は、前記第２方向における中央部と、前記稜被覆部に繋がる端縁部との間において、前記素子主面側に隆起した隆起部を有する、
    請求項４ないし請求項６のいずれか１つに記載の電子装置。
  8. 　前記第１被覆部においては、前記厚さ方向に見て、前記第２方向における中央部が前記第１素子側面側に窪んでいる、
    請求項４ないし請求項７のいずれか１つに記載の電子装置。
  9. 　前記第１被覆部においては、前記稜被覆部に繋がる端縁部の前記搭載面に対する傾斜度が、前記第２方向における中央部の前記搭載面に対する傾斜度よりも大きい、
    請求項４ないし請求項８のいずれか１つに記載の電子装置。
  10. 　前記第２被覆部においては、前記第１方向における中央部の前記厚さ方向の寸法が、前記稜被覆部に繋がる端縁部の前記厚さ方向の寸法よりも小さい、
    請求項４ないし請求項９のいずれか１つに記載の電子装置。
  11. 　前記第２被覆部は、前記第１方向における中央部と、前記稜被覆部に繋がる端縁部との間において、前記素子主面側に隆起した隆起部を有する、
    請求項４ないし請求項１０のいずれか１つに記載の電子装置。
  12. 　前記第２被覆部においては、前記厚さ方向に見て、前記第１方向における中央部が前記第２素子側面側に窪んでいる、
    請求項４ないし請求項１１のいずれか１つに記載の電子装置。
  13. 　前記第２被覆部は、前記稜被覆部に繋がる端縁部の前記搭載面に対する傾斜度が、前記第１方向における中央部の前記搭載面に対する傾斜度よりも大きい、
    請求項４ないし請求項１２のいずれか１つに記載の電子装置。
  14. 　前記フィレット部は、前記厚さ方向に見て、前記電子部品の全周にわたって形成されている、
    請求項１ないし請求項１３のいずれか１つに記載の電子装置。
  15. 　前記電子部品は、半導体材料からなる、
    請求項１ないし請求項１４のいずれか１つに記載の電子装置。
  16. 　前記電子部品は、前記素子主面に主面電極が形成されており、
    　前記搭載部は、リードフレームの一部であり、
    　前記リードフレームは、前記主面電極に導通し、かつ、前記搭載部から離間する端子部をさらに含む、
    請求項１ないし請求項１５のいずれか１つに記載の電子装置。
  17. 　前記リードフレームは、構成材料がＣｕを含む金属である、
    請求項１６に記載の電子装置。
  18. 　前記電子部品は、前記素子裏面に裏面電極が形成されており、
    　前記裏面電極は、前記接合材を介して、前記搭載部に導通する、
    請求項１ないし請求項１７のいずれか１つに記載の電子装置。
  19. 　前記接合材は、焼結銀からなる、
    請求項１ないし請求項１８のいずれか１つに記載の電子装置。
  20. 　厚さ方向において離間する素子主面および素子裏面を有する電子部品と、
    　前記素子裏面に対向する搭載面を有し、前記電子部品が搭載された搭載部と、
    　前記電子部品を前記搭載部に接合する接合材と、
    を備えた電子装置の製造方法であって、
    　前記搭載面にペースト状接合材を塗布する塗布工程と、
    　前記ペースト状接合材上に前記電子部品を載置する載置工程と、
    　前記ペースト状接合材を固化し、前記接合材を形成する固化工程と、
    を含み、
    　前記搭載部は、前記電子部品が接合される接合領域を含み、
    　前記接合領域は、前記厚さ方向に見て、前記電子部品の角に重なるコーナー部を含み、
    　前記ペースト状接合材は、前記厚さ方向に見て、前記電子部品の中央部から前記コーナー部に向かって少なくとも前記コーナー部まで塗布される、
    電子装置の製造方法。
PCT/JP2021/001480 2020-01-23 2021-01-18 電子装置および電子装置の製造方法 WO2021149637A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US17/792,931 US20230094354A1 (en) 2020-01-23 2021-01-18 Electronic device and method for manufacturing electronic device
CN202180010467.2A CN115023804A (zh) 2020-01-23 2021-01-18 电子器件和电子器件的制造方法
DE112021000726.2T DE112021000726T5 (de) 2020-01-23 2021-01-18 Elektronikbauteil und verfahren zum herstellen eines elektronikbauteils
JP2021572719A JPWO2021149637A1 (ja) 2020-01-23 2021-01-18

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2020-008918 2020-01-23
JP2020008918 2020-01-23

Publications (1)

Publication Number Publication Date
WO2021149637A1 true WO2021149637A1 (ja) 2021-07-29

Family

ID=76992390

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2021/001480 WO2021149637A1 (ja) 2020-01-23 2021-01-18 電子装置および電子装置の製造方法

Country Status (5)

Country Link
US (1) US20230094354A1 (ja)
JP (1) JPWO2021149637A1 (ja)
CN (1) CN115023804A (ja)
DE (1) DE112021000726T5 (ja)
WO (1) WO2021149637A1 (ja)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08330487A (ja) * 1995-05-30 1996-12-13 Ibiden Co Ltd 電子部品搭載用基板の製造方法
JP2005516399A (ja) * 2002-01-18 2005-06-02 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド ダイのせん断応力を減少すべく、ダイアタッチ・フィレットの高さを制御する方法及び装置
JP2010245161A (ja) * 2009-04-02 2010-10-28 Denso Corp 電子装置およびその製造方法
JP2014130961A (ja) * 2012-12-28 2014-07-10 Renesas Electronics Corp 半導体装置の製造方法および半導体装置
US20180040530A1 (en) * 2016-08-04 2018-02-08 Infineon Technologies Ag Die Attach Methods and Semiconductor Devices Manufactured based on Such Methods
JP2019029662A (ja) * 2017-08-02 2019-02-21 ローム株式会社 半導体装置および半導体装置の製造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000277679A (ja) 1999-03-25 2000-10-06 Denso Corp 半導体装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08330487A (ja) * 1995-05-30 1996-12-13 Ibiden Co Ltd 電子部品搭載用基板の製造方法
JP2005516399A (ja) * 2002-01-18 2005-06-02 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド ダイのせん断応力を減少すべく、ダイアタッチ・フィレットの高さを制御する方法及び装置
JP2010245161A (ja) * 2009-04-02 2010-10-28 Denso Corp 電子装置およびその製造方法
JP2014130961A (ja) * 2012-12-28 2014-07-10 Renesas Electronics Corp 半導体装置の製造方法および半導体装置
US20180040530A1 (en) * 2016-08-04 2018-02-08 Infineon Technologies Ag Die Attach Methods and Semiconductor Devices Manufactured based on Such Methods
JP2019029662A (ja) * 2017-08-02 2019-02-21 ローム株式会社 半導体装置および半導体装置の製造方法

Also Published As

Publication number Publication date
US20230094354A1 (en) 2023-03-30
CN115023804A (zh) 2022-09-06
DE112021000726T5 (de) 2022-11-10
JPWO2021149637A1 (ja) 2021-07-29

Similar Documents

Publication Publication Date Title
KR100533673B1 (ko) 반도체 장치 및 그 제조 방법, 회로 기판 및 전자 기기
US10879203B2 (en) Stud bump structure for semiconductor package assemblies
JP3935370B2 (ja) バンプ付き半導体素子の製造方法、半導体装置及びその製造方法、回路基板並びに電子機器
TWI529878B (zh) 集成電路封裝件及其裝配方法
CN100423258C (zh) 半导体器件及其制造方法
TWI311348B (en) Semiconductor device
US6621152B2 (en) Thin, small-sized power semiconductor package
US6677674B2 (en) Semiconductor package having two chips internally connected together with bump electrodes and both chips externally connected to a lead frame with bond wires
JP3865055B2 (ja) 半導体装置の製造方法
JP3584930B2 (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
JP6847266B2 (ja) 半導体パッケージおよびその製造方法
JPH10200012A (ja) ボールグリッドアレイ半導体のパッケージ及び製造方法
JP3573133B2 (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
TW200415766A (en) Thermally enhanced semiconductor package with EMI shielding
JP2004031607A (ja) 半導体装置及びその製造方法
JP2003068931A (ja) 半導体パッケージ及びその製造方法
JP3971568B2 (ja) 半導体パッケージ及び半導体パッケージの製造方法
JP7149751B2 (ja) 半導体装置
JP2010528472A (ja) 熱性能の向上のためにフタをはんだ付けされた集積回路パッケージ
JP4307362B2 (ja) 半導体装置、リードフレーム及びリードフレームの製造方法
WO2021149637A1 (ja) 電子装置および電子装置の製造方法
JP2001345411A (ja) リードフレームとそれを用いた半導体装置及びその生産方法
JP3981817B2 (ja) 半導体装置の製造方法
WO2023280669A2 (en) Power module comprising a patterned sintered connection and method for producing a power module
JP2021027211A (ja) 電子装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21743895

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2021572719

Country of ref document: JP

Kind code of ref document: A

122 Ep: pct application non-entry in european phase

Ref document number: 21743895

Country of ref document: EP

Kind code of ref document: A1