TWI462196B - 使用非導電網版印刷及施配黏著劑之半導體晶粒附著方法 - Google Patents
使用非導電網版印刷及施配黏著劑之半導體晶粒附著方法 Download PDFInfo
- Publication number
- TWI462196B TWI462196B TW099116180A TW99116180A TWI462196B TW I462196 B TWI462196 B TW I462196B TW 099116180 A TW099116180 A TW 099116180A TW 99116180 A TW99116180 A TW 99116180A TW I462196 B TWI462196 B TW I462196B
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- Prior art keywords
- integrated circuit
- conductive material
- die
- semiconductor integrated
- wafer
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- 239000004065 semiconductor Substances 0.000 title claims description 48
- 239000000853 adhesive Substances 0.000 title claims description 26
- 230000001070 adhesive effect Effects 0.000 title claims description 26
- 238000000034 method Methods 0.000 title claims description 19
- 235000012431 wafers Nutrition 0.000 claims description 37
- 239000012811 non-conductive material Substances 0.000 claims description 28
- 238000007650 screen-printing Methods 0.000 claims description 10
- 238000010438 heat treatment Methods 0.000 claims description 8
- 239000003822 epoxy resin Substances 0.000 claims description 5
- 229920000647 polyepoxide Polymers 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 4
- 239000004593 Epoxy Substances 0.000 description 8
- 229910052709 silver Inorganic materials 0.000 description 8
- 239000004332 silver Substances 0.000 description 8
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 7
- 239000004020 conductor Substances 0.000 description 7
- 238000013508 migration Methods 0.000 description 7
- 230000005012 migration Effects 0.000 description 7
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000013011 mating Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000010292 electrical insulation Methods 0.000 description 2
- 230000007774 longterm Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000003378 silver Chemical class 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
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- Condensed Matter Physics & Semiconductors (AREA)
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- Ceramic Engineering (AREA)
- Die Bonding (AREA)
Description
本發明係關於至引線框之半導體積體電路晶粒附著,且更特定言之,係關於藉由使用非導電網版印刷及施配黏著劑(其亦使該半導體晶粒與該引線框之晶粒附著晶墊(die attach paddle)電絕緣)之至該等引線框之各自晶粒附著晶墊之半導體晶粒附著。
在半導體積體電路製造期間,將一半導體積體電路晶粒(其之背面)附著至一引線框之一晶粒附著晶墊。接著,使用接合線將該半導體積體電路晶粒之接合墊附著至該引線框之導體。典型地,該半導體積體電路晶粒之背面係使用一黏著劑(諸如環氧樹脂)附接至該引線框之晶粒附著晶墊。隨著時間的過去,在該半導體積體電路晶粒與該引線框之晶粒晶墊之間可形成導電路徑。此等導電路徑可藉由從該引線框之晶粒附著晶墊至該積體電路晶粒之背面之銀遷移而產生。最終,此銀遷移產生該半導體積體電路晶粒之背面與該晶粒晶墊之間之一連接,因此引起其間之一電短路。
當該半導體積體電路晶粒與該晶粒附著晶墊之間存在一電位差時,來自該晶粒附著晶墊之銀分子可隨著時間遷移。當操作該半導體積體電路晶粒及/或將備用電力施加於該半導體積體電路晶粒時,存在此電位差。當該半導體積體電路晶粒正汲取低靜態電流,諸如在操作之一備用模式(睡眠模式)期間時,銀遷移尤其活躍。在一低靜態電流運行該半導體積體電路晶粒係必須的使得該半導體積體電路晶粒可自備用(睡眠)模式被帶入至一操作模式。銀遷移在該半導體積體電路晶粒與該晶粒附著晶墊之間產生電路徑且因此引起該半導體積體電路晶粒中之高靜態電流最終到達該半導體積體電路晶粒之電路出現故障之點。
已使用各種實體附著組態來使該半導體積體電路晶粒與該晶粒附著晶墊電絕緣。一此種附著組態使用非導電環氧樹脂以實現實體附著及電絕緣。然而,時間已證明因該半導體積體電路晶粒與該晶粒附著晶墊之間之導電路徑之故,此組態在防止高靜態電流方面係無效且不可靠的。
另一類似但更有效的方法係將一或兩個非導電環氧樹脂層網版印刷至一積體電路晶圓之背面上。該積體電路晶圓包括複數個半導體積體電路晶粒。該經網版印刷之環氧樹脂經部分固化(B階段)且然後準備用於單一化成個別晶粒。接著,藉由對晶粒附著晶墊進行加熱且然後洗滌該等經加熱之晶粒附著晶墊上之非導電B階段環氧樹脂塗佈晶粒而將該等個別積體電路晶粒附著至複數個引線框之各自晶粒附著晶墊。在已將該等晶粒附著至該等各自晶粒附著晶墊之後,對其等進行加熱直至該非導電B階段環氧樹脂硬化(C階段)。此附著形式確實解決了長期銀遷移問題,但是該B階段環氧樹脂積體電路晶圓之有效儲存壽命僅為大約兩至四星期。
因此,需要使用一非導電材料塗佈一半導體積體電路晶圓之背面之一更佳方法使得該塗層具有一較長儲存(存放)壽命,幫助經單一化之半導體積體電路晶粒附著至引線框之晶粒附著晶墊,且在半導體積體電路晶粒操作期間防止或實質上降低自該晶粒附著晶墊之銀遷移。
根據本發明之教示,一均勻非導電材料(例如,環氧樹脂)層網版印刷至一積體電路晶圓之背面上達一所需厚度,且接著經加熱直至其硬化(C階段)。該網版印刷可以一圖案將該非導電材料塗敷於該積體電路晶圓之背面上。接著,將其上具有該經硬化之塗層之該積體電路晶圓鋸切開以在該晶圓中彼此分離個別積體電路晶粒(單一化),以準備附著至引線框之各自晶粒附著晶墊。所需的厚度可為從大約1毫英吋至大約3毫英吋,較佳為從大約1.5毫英吋至2.5毫英吋,且更佳為大約2毫英吋。
在將晶粒附著至一晶粒附著晶墊的程序期間,將一非導電黏著劑(例如,環氧樹脂)施配至該晶粒附著晶墊之配合面上。接著,將具有該經硬化之塗層之晶粒面放置於該晶粒附著晶墊之配合面上之剛施配的非導電黏著劑中。接著,對該晶粒與晶粒附著晶墊總成進行加熱以硬化該晶粒與晶粒附著晶墊之該等配合面之間之該黏著劑。在該黏著劑已硬化之後,可將積體電路接合墊引線接合至引線框引線(用於已製成的積體電路外部電路連接之導電引線)。因此提供該積體電路晶粒與該引線框之晶粒附著晶墊之長期電絕緣,且有效地消除引起增加該晶粒中之非所欲電流洩漏之導電路徑的形成並最終引起其之操作期間之故障之自該晶粒附著晶墊之銀遷移。
根據本發明之一特定實例實施例,一種用於將半導體晶粒附著至引線框晶粒附著晶墊之方法包括下列步驟:將一非導電材料塗敷於一半導體積體電路晶圓之一背面,該半導體積體電路晶圓包括複數個積體電路晶粒;對該半導體積體電路晶圓及其上之該非導電材料進行加熱直至該非導電材料硬化;將該半導體積體電路晶圓安裝於一晶圓載體上;其中該經硬化之非導電材料係介於該半導體積體電路晶圓與該晶圓載體之間;將該複數個積體電路晶粒之各者彼此分離;將非導電黏著劑施配於複數個引線框之晶粒附著晶墊之面上;將該複數個積體電路晶粒放置於該等晶粒附著晶墊之各自者之面上之該非導電黏著劑中;對該複數個積體電路晶粒及晶粒附著晶墊進行加熱直至該非導電黏著劑硬化;使用接合線將該複數個積體電路晶粒之接合墊附著至該複數個引線框之各自導電引線;及將該複數個引線框之各者分離成積體電路。
藉由結合隨附圖式參考以下描述可獲致對本發明之一更透徹理解。
雖然本發明可能具有各種修飾及替代形式,但是圖式中已展示其之特定實例實施例且本文中已詳細描述該等實施例。然而,應瞭解本文中之特定實例實施例之描述不旨在將本發明限制於本文所揭示之特定形式,而是相反地,本發明係旨在涵蓋如隨附申請專利範圍所定義之所有修飾及等效物。
現參考圖式,其示意性地繪示特定實例實施例之細節。圖式中相同的元件將由相同的元件符號表示,且類似元件將由具有一不同的小寫字母下標的相同元件符號表示。
參考圖1,其描繪的是根據本發明之一特定實例實施例之使用非導電網版印刷及施配黏著劑之半導體晶粒附著之一示意性程序圖。一半導體積體電路晶圓102係放置於一網版印刷固定具106中,且一非導電材料108係使用一網版印刷塗布器104塗布於該晶圓102之背面(非電路墊側)上。在塗布表面之技術中,該網版印刷固定具106之使用係熟知的。有了該網版印刷固定具106,可將一期望圖案之非導電材料108塗敷於該晶圓102之背面上。該非導電材料108可為(例如,但不限於)環氧樹脂及類似物。
在將該非導電材料108網版印刷至該晶圓102之背面之後,將該經塗布之晶圓102放置於一固化爐110內以用於該非導電材料108之硬化。該非導電材料108之硬化可包括(例如,但不限於)在約攝氏150度下加熱大約兩個小時。在該非導電材料108已於該晶圓102之背面硬化之後,可在進一步處理之前將該晶圓102儲存達經延長時段,或將該經硬化之塗布晶圓102附著至一處理基板112(例如,安裝帶),使得該晶圓102可被單一化(藉由切割分離)成複數個半導體積體電路晶粒124。
一引線框載體114包括複數個引線框116。該複數個引線框116之各者包括一晶粒附著晶墊116a及引線框導體116b。引線框116為積體電路製造之一般技術者所熟知。將黏著劑118施配至該等晶粒附著晶墊116a之各者之一面上。接著,將該經單一化(分離)之晶粒124放置於該等各自晶粒附著晶墊116a之各者上之該黏著劑118上。將該引線框載體114、複數個引線框116、黏著劑118及經塗布之晶粒124之總成放置於一固化爐120中,因此使得該黏著劑118硬化。該非導電黏著劑118之硬化可包括(例如,但不限於)在大約攝氏175度下加熱大約1小時。該接著材料118係實質上非導電且可為(例如,但不限於)環氧樹脂及類似物。
在該接著材料118已硬化且冷卻之後,將該等引線框116自該固化爐120移除並使用接合線122將該等晶粒124之各者上之該等接合墊126連接至該等引線框導體116b之各自者。積體電路接合墊126與引線框導體116b之引線接合為積體電路製造之一般技術者所熟知。
在將該等晶粒接合墊126之各者引線接合至該等引線框導體116b之各自者之後,已製成的積體電路總成經分離且可被囊封成經封裝積體電路(圖中未展示)。
參考圖2,其描繪的是根據本發明之一特定實例實施例之圖1中展示之該半導體晶粒附著程序之一示意流程圖。在步驟202中,使用非導電材料(108)塗布一半導體積體電路晶圓(102)之背面。在步驟204中,塗布於一半導體積體電路晶圓(102)之背面上之該非導電材料(108)被硬化。在步驟206中,將該經塗布之晶圓(102)安裝至一載體(112)上,且接著在步驟208中,將構成該晶圓(102)之複數個積體電路晶粒(124)彼此分離開來(單一化)。
在步驟210中,將黏著劑(118)施配至一引線框載體(114)上之引線框(116)之晶粒附著晶墊(116a)之面上。接著,在步驟212中,將該等經單一化之積體電路晶粒(124)放置於該等各自晶粒附著晶墊(116a)之面上之該黏著劑(118)中。在步驟214中,對該黏著劑(118)進行加熱以使其硬化(階段C)。在步驟216中,將該等晶粒(124)之接合墊(126)引線接合至該等引線框(116)之導體(116b)(例如,引線指狀物(leadfinger))之各自者。在步驟218中,將該等引線框(116)與該引線框載體(114)分離以成為已製成積體電路。如在電子技術中所熟知,在步驟220中,此等已製成積體電路可經囊封以變成經封裝積體電路。
雖然藉由參考本發明之若干實例實施例描繪、描述,及界定本發明之實施例,但是此等引用不意味對本發明之一限制,且不可推斷此種限制。如受益於本發明之一般相關技術者將想到,所揭示的標的能夠在形式及功能上實現相當多的修飾、變更,及等效物。本發明之所描繪及描述的實施例僅為實例,且未詳盡本發明之範疇。
102...半導體積體電路晶圓
104...網版印刷塗布器
106...固定具
108...非導電材料
110...固化爐
112...處理基板
114...引線框載體
116...引線框
116a...晶粒附著晶墊
116b...引線框導體
118...黏著劑
120...固化爐
122...接合線
124...經單一化之晶粒
126...接合墊
圖1係根據本發明之一特定實例實施例之使用非導電網版印刷及施配黏著劑之半導體晶粒附著之一示意程序圖;及
圖2係根據本發明之一特定實例實施例之圖1中展示之該半導體晶粒附著程序之一示意流程圖。
(無元件符號說明)
Claims (11)
- 一種用於將半導體晶粒附著至引線框晶粒附著晶墊之方法,該方法包括下列步驟:將一非導電材料塗敷於一半導體積體電路晶圓之一背面,該半導體積體電路晶圓包括複數個積體電路晶粒;對該半導體積體電路晶圓及其上之該非導電材料進行加熱直至該非導電材料硬化;將該半導體積體電路晶圓安裝於一晶圓載體上;其中該經硬化之非導電材料係介於該半導體積體電路晶圓與該晶圓載體之間;將該複數個積體電路晶圓之各者彼此分離;將非導電黏著劑施配於複數個引線框之晶粒附著晶墊之面上;將該複數個積體電路晶粒放置於該等晶粒附著晶墊之各自者之該等面上之該非導電黏著劑中;對該複數個積體電路晶粒及晶粒附著晶墊進行加熱直至該非導電黏著劑硬化;使用接合線將該複數個積體電路晶粒之接合墊附著至該複數個引線框之各自的導電引線;及將該複數個引線框之各者分離成積體電路。
- 如請求項1之方法,其進一步包括囊封該等積體電路以產生經封裝積體電路之步驟。
- 如請求項1之方法,其中該非導電材料係以從大約一毫英吋至大約三毫英吋之一厚度塗敷。
- 如請求項1之方法,其中該非導電材料係以從大約1.5毫英吋至大約2.5毫英吋之一厚度塗敷。
- 如請求項1之方法,其中該非導電材料係以大約兩毫英吋之一厚度塗敷。
- 如請求項1之方法,其中該非導電材料係環氧樹脂。
- 如請求項1之方法,其中該非導電黏著劑係環氧樹脂。
- 如請求項1之方法,其中塗敷該非導電材料之該步驟係藉由網版印刷而完成。
- 如請求項8之方法,其中該經網版印刷之非導電材料係以一圖案塗敷。
- 如請求項1之方法,其中對該半導體積體電路晶圓及該非導電材料進行加熱之該步驟包括在大約攝氏150度下加熱大約兩個小時之步驟。
- 如請求項1之方法,其中對該複數個積體電路晶粒及晶粒附著晶墊進行加熱直至該非導電黏著劑硬化之該步驟包括在大約攝氏175度下加熱大約一小時之步驟。
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US10234513B2 (en) | 2012-03-20 | 2019-03-19 | Allegro Microsystems, Llc | Magnetic field sensor integrated circuit with integral ferromagnetic material |
US9812588B2 (en) | 2012-03-20 | 2017-11-07 | Allegro Microsystems, Llc | Magnetic field sensor integrated circuit with integral ferromagnetic material |
US8822274B2 (en) | 2012-10-04 | 2014-09-02 | Texas Instruments Incorporated | Packaged IC having printed dielectric adhesive on die pad |
US10727085B2 (en) * | 2015-12-30 | 2020-07-28 | Texas Instruments Incorporated | Printed adhesion deposition to mitigate integrated circuit package delamination |
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US20050189658A1 (en) * | 2004-01-29 | 2005-09-01 | Tan Xiaochun | Semiconductor device assembly process |
US20080241998A1 (en) * | 2007-03-30 | 2008-10-02 | Motorola, Inc. | Method for fabricating a low cost integrated circuit (ic) package |
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US5012322A (en) * | 1987-05-18 | 1991-04-30 | Allegro Microsystems, Inc. | Semiconductor die and mounting assembly |
US5208188A (en) * | 1989-10-02 | 1993-05-04 | Advanced Micro Devices, Inc. | Process for making a multilayer lead frame assembly for an integrated circuit structure and multilayer integrated circuit die package formed by such process |
US6353268B1 (en) * | 1997-08-22 | 2002-03-05 | Micron Technology, Inc. | Semiconductor die attachment method and apparatus |
US6627517B1 (en) * | 1999-12-08 | 2003-09-30 | Altera Corporation | Semiconductor package with improved thermal cycling performance, and method of forming same |
US6943061B1 (en) * | 2004-04-12 | 2005-09-13 | Ns Electronics Bangkok (1993) Ltd. | Method of fabricating semiconductor chip package using screen printing of epoxy on wafer |
US7892894B2 (en) * | 2007-09-20 | 2011-02-22 | Stats Chippac Ltd. | Method of manufacturing integrated circuit package system with warp-free chip |
-
2009
- 2009-05-27 US US12/472,675 patent/US7927921B2/en active Active
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2010
- 2010-05-20 TW TW099116180A patent/TWI462196B/zh active
- 2010-05-21 CN CN201080004725.8A patent/CN102282658B/zh active Active
- 2010-05-21 WO PCT/US2010/035763 patent/WO2010138415A2/en active Application Filing
- 2010-05-21 SG SG2011066701A patent/SG174422A1/en unknown
- 2010-05-21 MY MYPI2011004373A patent/MY154082A/en unknown
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US20050189658A1 (en) * | 2004-01-29 | 2005-09-01 | Tan Xiaochun | Semiconductor device assembly process |
US20080241998A1 (en) * | 2007-03-30 | 2008-10-02 | Motorola, Inc. | Method for fabricating a low cost integrated circuit (ic) package |
Also Published As
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CN102282658A (zh) | 2011-12-14 |
US20100304532A1 (en) | 2010-12-02 |
TW201108337A (en) | 2011-03-01 |
US7927921B2 (en) | 2011-04-19 |
SG174422A1 (en) | 2011-10-28 |
WO2010138415A3 (en) | 2011-05-26 |
WO2010138415A2 (en) | 2010-12-02 |
CN102282658B (zh) | 2018-11-02 |
MY154082A (en) | 2015-04-30 |
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