FR3083643B1 - Procede de realisation d'un dispositif electronique - Google Patents

Procede de realisation d'un dispositif electronique Download PDF

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Publication number
FR3083643B1
FR3083643B1 FR1856171A FR1856171A FR3083643B1 FR 3083643 B1 FR3083643 B1 FR 3083643B1 FR 1856171 A FR1856171 A FR 1856171A FR 1856171 A FR1856171 A FR 1856171A FR 3083643 B1 FR3083643 B1 FR 3083643B1
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Prior art keywords
making
electronic device
electronic
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FR1856171A
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FR3083643A1 (fr
Inventor
Jean Brun
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Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Commissariat a lEnergie Atomique CEA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Priority to FR1856171A priority Critical patent/FR3083643B1/fr
Priority to US17/257,651 priority patent/US20210125957A1/en
Priority to EP19745566.0A priority patent/EP3818563A1/fr
Priority to PCT/EP2019/067944 priority patent/WO2020007960A1/fr
Publication of FR3083643A1 publication Critical patent/FR3083643A1/fr
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    • G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
    • G01L9/00—Measuring steady of quasi-steady pressure of fluid or fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Micromachines (AREA)
FR1856171A 2018-07-04 2018-07-04 Procede de realisation d'un dispositif electronique Active FR3083643B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR1856171A FR3083643B1 (fr) 2018-07-04 2018-07-04 Procede de realisation d'un dispositif electronique
US17/257,651 US20210125957A1 (en) 2018-07-04 2019-07-04 Method for fabricating an electronic device
EP19745566.0A EP3818563A1 (fr) 2018-07-04 2019-07-04 Dispositif electronique et son procede de realisation
PCT/EP2019/067944 WO2020007960A1 (fr) 2018-07-04 2019-07-04 Dispositif electronique et son procede de realisation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1856171A FR3083643B1 (fr) 2018-07-04 2018-07-04 Procede de realisation d'un dispositif electronique

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FR3083643A1 FR3083643A1 (fr) 2020-01-10
FR3083643B1 true FR3083643B1 (fr) 2023-01-13

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EP (1) EP3818563A1 (fr)
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WO (1) WO2020007960A1 (fr)

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CN114898671A (zh) * 2022-05-05 2022-08-12 昆山国显光电有限公司 邦定结构及显示装置

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JP3271631B2 (ja) * 1993-02-18 2002-04-02 太平洋セメント株式会社 半導体装置実装用基板
US7332819B2 (en) * 2002-01-09 2008-02-19 Micron Technology, Inc. Stacked die in die BGA package
US20030111720A1 (en) * 2001-12-18 2003-06-19 Tan Lan Chu Stacked die semiconductor device
JP4669270B2 (ja) * 2004-12-02 2011-04-13 富士通株式会社 Ｒｆｉｄタグおよびその製造方法
FR2905518B1 (fr) 2006-08-29 2008-12-26 Commissariat Energie Atomique Puce microelectronique a faces laterales munies de rainures et procede de fabrication
FR2928491A1 (fr) 2008-03-06 2009-09-11 Commissariat Energie Atomique Procede et dispositif de fabrication d'un assemblage d'au moins deux puces microelectroniques
FR2954588B1 (fr) * 2009-12-23 2014-07-25 Commissariat Energie Atomique Procede d'assemblage d'au moins une puce avec un element filaire, puce electronique a element de liaison deformable, procede de fabrication d'une pluralite de puces, et assemblage d'au moins une puce avec un element filaire
FR2971081B1 (fr) * 2011-02-02 2013-01-25 Commissariat Energie Atomique Procédé de fabrication de deux substrats relies par au moins une connexion mécanique et électriquement conductrice obtenue
FR3034566A1 (fr) * 2015-03-31 2016-10-07 Commissariat Energie Atomique Procede d'assemblage de substrats

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US20210125957A1 (en) 2021-04-29
WO2020007960A1 (fr) 2020-01-09
EP3818563A1 (fr) 2021-05-12
FR3083643A1 (fr) 2020-01-10

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