CN101517717B - 具有相容电介质层的有源区域 - Google Patents

具有相容电介质层的有源区域 Download PDF

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CN101517717B
CN101517717B CN2007800345522A CN200780034552A CN101517717B CN 101517717 B CN101517717 B CN 101517717B CN 2007800345522 A CN2007800345522 A CN 2007800345522A CN 200780034552 A CN200780034552 A CN 200780034552A CN 101517717 B CN101517717 B CN 101517717B
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oxide
comprised
substrate
dielectric layer
active region
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CN101517717A (zh
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P·拉纳德
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Intel Corp
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Intel Corp
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Abstract

描述一种用于形成具有有源区域和相容的电介质层的半导体结构的方法。在一个实施例中，半导体结构具有由第一半导体材料的氧化物组成的电介质层，其中在电介质层与第一半导体材料之间形成有第二(且成分不同的)半导体材料。在另一个实施例中，用第三半导体材料取代第二半导体材料的一部分，以便赋予第二半导体材料的晶格结构单轴应变。

Description

具有相容电介质层的有源区域
技术领域
本发明属于半导体结构领域。
背景技术
在过去数十年，利用掺杂晶体硅作为有源区域(如沟道区域)并利用非晶二氧化硅作为电介质区域(如栅极电介质层)而制造了诸如金属氧化物半导体场效应晶体管(MOS-FET)的半导体器件。硅/二氧化硅配对的妙处在于，可以经由在有氧的情况下加热晶体硅衬底而直接在晶体硅衬底的表面上形成二氧化硅。此工艺很好控制，并且可以可靠地提供薄至2-3个单层厚的二氧化硅薄膜。
但是，为了实现越来越快速的半导体器件，希望利用晶体硅以外的沟道材料。要注意一点，很少有其它半导体材料(如果有)能形成象晶体硅/二氧化硅配对那样相容的表面非晶氧化物层。这使得利用硅以外的沟道材料相当令人气馁。因此，本文描述一种形成具有相容的电介质层的有源区域的方法和所得结构。
附图说明
图1A-B示出表示根据本发明的一个实施例包含具有相容的电介质层的有源区域的半导体结构的横截面图。
图2A-N示出表示根据本发明的一个实施例包含具有相容的电介质层的有源区域的平面MOS-FET的形成的横截面图。
图3A-C示出表示根据本发明的一个实施例包含具有相容的电介质层的有源区域的三栅极MOS-FET的形成的横截面图。
具体实施方式
描述半导体器件的制造方法和所得器件。在以下描述中，阐述了众多具体细节，如具体的尺寸和化学法，以便充分理解本发明。本领域的技术人员将明白，在没有这些具体细节的情况下，也可实现本发明。在其它情况下，没有详细描述诸如图案化步骤或湿化学清洗的熟知的处理步骤，以免不必要地使本发明晦涩难懂。此外，将明白，图中示出的各个实施例只是说明性的表示，而不一定按比例绘制。
本文公开包含具有相容的电介质层的有源区域的半导体结构及其形成方法。经由在氧化工艺中消耗半导体衬底的上表面来使氧化物可控地热生长或自然生长，可提供可靠的电介质层。但是，希望在保留可靠电介质层的同时，还希望用不同的半导体材料来取代半导体衬底中直接位于可靠电介质层下方的那部分。这样在随后用不同的半导体材料来取代半导体衬底中直接位于电介质层下方的那一部分可使得能够形成具有可靠的电介质层的新的有源区域。因此，可形成这样的结构，其中直接在不同的第二半导体材料上保留包含第一半导体材料的氧化物的电介质层。在第二半导体材料的氧化物的特性比第一半导体材料的氧化物的特性差、但仍希望加入第二半导体材料的情况中，这种方法和所得结构尤其有益。此外，可以用第三半导体材料来取代第二半导体材料的一部分，以便赋予第二半导体材料的晶格结构单轴应变。加入最佳的半导体材料来形成有源区域以及对该有源区域施加单轴应变这两者的组合可使半导体器件的沟道区域中的电荷载流子迁移率增大。因此，可实现高性能半导体器件的优化。
经由氧化工艺来可控地消耗半导体衬底的上表面可在该衬底的表面上提供可靠(即，厚度均匀且成分一致)的电介质层。例如，在晶体硅衬底的表面上热或自然生长二氧化硅可提供薄至3-10埃(即，1-3个单层)的可靠电介质层。所得氧化物层可用作半导体器件中的栅极电介质层或其组件。根据本发明的一个实施例，通过在有诸如O2、H2O或O3的氧化剂的情况下加热晶体硅衬底来在晶体硅衬底的表面上形成二氧化硅层。根据本发明的一个备选实施例，在原子层沉积(ALD)腔室中将晶体硅衬底暴露至水脉冲后形成自然的二氧化硅层。可通过直接在自然的二氧化硅层上方沉积高K电介质材料层来形成双层电介质层。
在一些应用中，晶体硅衬底可能并不是半导体器件中用作有源区域(如沟道区域)的最理想的材料。例如，根据本发明的一个实施例，在P型器件中希望使用锗作为沟道材料，而在N型器件中则希望使用III-V族材料作为沟道材料。在另一个实施例中，对于P型器件和N型器件，使用锗或III-V族材料之一。通过在这些器件中加入这些沟道材料，可分别优化空穴迁移率和电子迁移率，从而改善器件性能。但是，锗和III-V族材料的表面氧化往往会提供不稳定和/或厚度或成分不一致的氧化物层。因此，希望将一种半导体材料与不同半导体材料的氧化物层进行组合。因而，根据本发明的一个实施例，将否则会提供较差氧化物层的半导体材料与可靠的氧化物层进行组合，其中该氧化物层是不同半导体材料的氧化物。
为了提供包含与第一半导体材料的氧化物层组合的第二半导体材料的半导体结构，可以利用取代方法。实际上，可以在第一半导体材料上方形成氧化物层，然后，除去第一半导体材料的一部分以在氧化物层与第一半导体材料之间形成沟槽。接着，可在沟槽中形成第二半导体材料。因此，根据本发明的一个实施例，用直接位于预先形成的氧化物层与半导体衬底之间的第二半导体材料(即，有源区域)来取代由第一半导体材料组成的半导体衬底的一部分。
在晶体半导体材料之上或之中形成的半导体区域可赋予晶体半导体材料应变，并且因此，如果该半导体区域的晶格常数不同于晶体半导体材料的晶格常数，则该半导体区域可成为诱导应变的半导体区域。晶格常数是基于半导体区域和晶体半导体材料每个内的原子间距和晶胞取向的。因此，包含种类不同于晶体半导体材料的晶格形成原子的半导体区域可赋予晶体半导体材料应变。例如，根据本发明的一个实施例，只包含硅晶格形成原子的半导体区域赋予由锗晶格形成原子组成的晶体半导体材料应变。此外，包含种类与晶体半导体材料相同的晶格形成原子、但其中这些种类的晶格形成原子的化学计量浓度有所不同的半导体区域可赋予晶体半导体材料应变。例如，根据本发明的一个实施例，包含SixGe1-x晶格形成原子(其中0＜x＜1)的半导体区域赋予由SiyGe1-y晶格形成原子(其中0＜y＜1，且x≠y)组成的晶体半导体材料应变。
作为本发明的一个实施例的实例，图1A-B示出表示包含具有相容的电介质层的有源区域的半导体结构的横截面图。参照图1A，半导体结构100包括衬底102，衬底102由第一半导体材料组成。有源区域104位于衬底102上方，并且有源区域由第二半导体材料组成。根据本发明的一个实施例，第二半导体材料的成分(即，原子构成)不同于第一半导体材料的成分。电介质层106直接位于有源区域104上方，并且可包括第一半导体材料的氧化物层。导电区域108位于电介质层106上方，由此将导电区域108与有源区域104隔离开。
衬底102可包括能经受制造过程的任何半导体材料。在一个实施例中，衬底102由掺杂有电荷载流子的晶体硅或硅/锗层组成，其中电荷载流子例如但不限于磷、砷、硼或其组合。在一个实施例中，衬底102中硅原子的浓度大于97％。在另一个实施例中，衬底102由生长在截然不同的晶体衬底顶上的外延层组成，例如由生长在硼掺杂块状硅单晶衬底顶上的硅外延层组成。衬底102可包括位于块状晶体衬底与外延层之间的绝缘层，以便形成例如绝缘体上硅衬底。在一个实施例中，绝缘层由选自由二氧化硅、氮化硅、氧氮化硅或高k电介质层组成的组中的材料组成。
有源区域104可包括电荷可在其中迁移的任何半导体材料。在一个实施例中，有源区域104由III-V族材料组成，例如但不限于氮化镓、磷化镓、砷化镓、磷化铟、锑化铟、砷化铟镓、砷化铝镓、磷化铟镓或其组合。在另一个实施例中，有源区域104由锗、或其中锗原子的原子浓度大于5％的硅/锗组成。有源区域104中可加入电荷载流子掺杂剂杂质原子。在一个实施例中，有源区域104是化学计量比为SixGe1-x的晶体硅/锗有源区域，其中0≤x≤1，并且电荷载流子掺杂剂杂质原子选自由硼、砷、铟或磷组成的组。在另一个实施例中，有源区域104由III-V族材料组成，并且电荷载流子掺杂剂杂质原子选自由碳、硅、锗、氧、硫、硒或碲组成的组。
电介质层106可包括适于将导电区域108与有源区域104隔离开的任何电介质材料。此外，电介质层106可包括不同于有源区域104的半导体材料的氧化物层的半导体材料氧化物层。在一个实施例中，电介质层106由半导体材料的氧化物组成。在一个实施例中，电介质层106由二氧化硅或氧氮化硅组成。在一个实施例中，电介质层106由衬底102的半导体材料的氧化物层组成。在一个具体实施例中，衬底102由硅组成，并且电介质层106由二氧化硅或氧氮化硅组成。在一个实施例中，电介质层106由直接位于有源区域104上的氧化物层组成。在一个实施例中，电介质层106由衬底102的半导体材料的氧化物层组成，有源区域104由不同于衬底102的半导体材料的半导体材料组成，并且电介质层106的氧化物层直接位于有源区域104的上表面上。在一个具体实施例中，电介质层106由二氧化硅或氧氮化硅组成，衬底102由硅组成，并且有源区域104由锗或III-V族材料组成。或者，电介质层106可由高K电介质层组成。在一个实施例中，高K电介质层选自由以下材料组成的组：氧化铪、硅酸铪、氧化镧、氧化锆、硅酸锆、氧化钽、钛酸锶钡、钛酸钡、钛酸锶、氧化钇、氧化铝、氧化铅钪钽、铌酸铅锌(lead zinc niobate)或其组合。
导电区域108可包括适于传导电流的任何材料。在一个实施例中，导电区域108由掺杂多晶硅组成。在另一个实施例中，导电区域108由金属层组成，例如但不限于金属氮化物、金属碳化物、金属硅化物、铪、锆、钛、钽、铝、钌、钯、铂、钴、镍或导电金属氧化物(如氧化钌)。
参照图1B，可在半导体结构100中加入可用于制造半导体器件110的额外特征。在有源区域104中形成一对尖端延伸部112，并通过沟道区域114将其分隔，其中沟道区域114包括有源区域104的一部分。导电区域108可以为栅电极，其上表面可以用栅电极保护层116进行保护，且其侧壁用一对栅极隔离间隔物118进行保护。这对栅极隔离间隔物118位于这对尖端延伸部112上方。在有源区域104中、在栅极隔离间隔物118的两侧上形成一对源极/漏极区域120。如图1B所描绘，这对源极/漏极区域120可在有源区域104的上表面上方凸起。电介质层106可以是栅极电介质层，并且可以由两个不同的电介质层、即下层106A和上层106B组成，这同样如图1B所描绘。
这对尖端延伸部112可包括加入电荷载流子掺杂剂杂质原子的有源区域104的部分。在一个实施例中，有源区域104是化学计量比为SixGe1-x的晶体硅/锗有源区域，其中0≤x≤1，并且电荷载流子掺杂剂杂质原子选自由硼、砷、铟或磷组成的组。在另一个实施例中，有源区域104由III-V族材料组成，并且电荷载流子掺杂剂杂质原子选自由碳、硅、锗、氧、硫、硒或碲组成的组。
栅电极保护层116和这对栅极隔离间隔物118可包括适于隔离栅电极的任何材料。但是，栅电极保护层116和栅极隔离间隔物118不需要使用相同种类的材料。在一个实施例中，栅电极保护层116和栅极隔离间隔物118由绝缘材料组成。在一个特定实施例中，栅电极保护层116和栅极隔离间隔物118由选自由下列材料组成的组中的材料组成：二氧化硅、氧氮化硅、碳掺杂氧化硅、氮化硅、碳掺杂氮化硅或其组合。
这对源极/漏极区域120可包括加入电荷载流子掺杂剂杂质原子的有源区域104的部分。在一个实施例中，有源区域104是化学计量比为SixGe1-x的晶体硅/锗有源区域，其中0≤x≤1，并且电荷载流子掺杂剂杂质原子选自由硼、砷、铟或磷组成的组。在另一个实施例中，有源区域104由III-V族材料组成，并且电荷载流子掺杂剂杂质原子选自由碳、硅、锗、氧、硫、硒或碲组成的组。或者，这对源极/漏极区域120可包括不同于有源区域104的半导体材料的半导体材料。在一个实施例中，源极/漏极区域的半导体材料的晶格常数不同于有源区域104的半导体材料的晶格常数，并且因此，这对源极/漏极区域120是一对诱导单轴应变的源极/漏极区域。在一个实施例中，有源区域104由SixGe1-x组成，并且这对源极/漏极区域120由SiyGe1-y组成，其中0≤x，y≤1，且x≠y。在另一个实施例中，分别地，有源区域104由AlxGa1-xAs、InxGa1-xAs、InxGa1-xP或AlxIn1-xSb组成，而这对源极/漏极区域120由AlyGa1-yAs、InyGa1-yAs、InyGa1-yP或AlyIn1-ySb组成，其中0≤x，y≤1，且x≠y。
电介质层106可由两个不同的电介质层、即下层106A和上层106B组成。在一个实施例中，下层106A由半导体材料的氧化物组成。在一个实施例中，下层106A由二氧化硅或氧氮化硅组成。在一个实施例中，下层106A由衬底102的半导体材料的氧化物层组成。在一个具体实施例中，衬底102由硅组成，而下层106由二氧化硅或氧氮化硅组成。在一个实施例中，下层106A由直接位于有源区域104上的氧化物层组成。在一个实施例中，下层106A由衬底102的半导体材料的氧化物层组成，有源区域104由不同于衬底102的半导体材料的半导体材料组成，并且下层106A直接位于有源区域104的上表面上。在一个具体实施例中，下层106A由二氧化硅或氧氮化硅组成，衬底102由硅组成，并且有源区域104由锗或III-V族材料组成。在一个实施例中，上层106B由二氧化硅或氧氮化硅组成。在一个备选实施例中，上层106B由高K电介质层组成。在一个实施例中，高K电介质层选自由以下材料组成的组：氧化铪、硅酸铪、氧化镧、氧化锆、硅酸锆、氧化钽、钛酸锶钡、钛酸钡、钛酸锶、氧化钇、氧化铝、氧化铅钪钽、铌酸铅锌或其组合。在一个特定实施例中，半导体衬底102由硅组成，下层106A由二氧化硅或氧氮化硅组成，而上层106B由高K电介质层组成。
包含具有相容的电介质层的有源区域的半导体结构可用于形成半导体器件。在一个实施例中，半导体器件是平面MOS-FET、存储晶体管或微电子机器(MEM)。在另一个实施例中，半导体器件是非平面器件，如三栅极或FIN-FET晶体管、可独立访问的双栅极MOS-FET或具有纳米线沟道的围栅MOS-FET。图2A-N示出表示根据本发明的一个实施例形成包含具有相容的电介质层的有源区域的平面MOS-FET的横截面图。在一个实施例中，这种方法使得能够在由通常不产生高质量氧化物的半导体材料组成的有源区域(即，取代的第二半导体材料)上形成高质量电介质层(包含第一半导体材料的氧化物)。将明白，在典型的集成电路中，可在单个衬底或外延层中制作N-和P-沟道晶体管，以形成CMOS集成电路。
参照图2A，在衬底202上方形成栅极电介质层206。衬底202可包括结合图1A-B中的衬底102论述的任何材料。类似地，栅极电介质层206可包括结合图1A中的电介质层106论述的任何材料。栅极电介质层206可通过适于在衬底202的上表面上方提供可靠(即，成分和厚度一致)的电介质层的任何技术由衬底202的氧化物形成。根据本发明的一个实施例，通过消耗衬底202的上表面的一部分来形成栅极电介质层206。在一个实施例中，通过氧化衬底202的上表面以形成由衬底202的半导体材料的氧化物组成的氧化物层来形成栅极电介质层206。在一个特定实施例中，通过在有诸如O2、H2O或O3的氧化剂的情况下加热衬底202直到形成所需厚度的氧化物层来形成栅极电介质层206。在一个具体实施例中，衬底202由硅组成，栅极电介质层206由二氧化硅层组成，该二氧化硅层的形成是在摄氏600-800度范围内的温度、历时1分钟-1小时的时间进行的，并且二氧化硅层形成在5-15埃范围内的厚度。在另一个实施例中，通过在有含氮气体的情况下氧化衬底202的上表面以形成由衬底202的半导体材料的氧氮化物组成的氧氮化物层来形成栅极电介质层206。在一个特定实施例中，通过在有诸如O2、H2O或O3的氧化剂和氨的情况下加热衬底202直到形成所需厚度的氧氮化物层来形成栅极电介质层206。在一个具体实施例中，衬底202由硅组成，栅极电介质层206由氧氮化硅层组成，该氧氮化硅层的形成是在摄氏600-800度范围内的温度、历时1分钟-1小时的时间进行的，并且氧氮化硅层形成在5-15埃范围内的厚度。在一个备选实施例中，通过沉积法来形成栅极电介质层206。在一个实施例中，沉积法选自由化学气相沉积法、原子层沉积法或物理气相沉积法组成的组。
参照图2A’，栅极电介质层206可由两个不同的电介质层、即下层206A和上层206B组成。栅极电介质层206的下层206A和上层206B可包括结合图1B中的下层106A和上层106B论述的任何材料。根据本发明的一个实施例，在衬底202上方形成由氧化物或氧氮化物层组成的下层206A(如上所述)之后，可在下层206A上方形成上层206B。上层206B可通过适于在下层206A的上表面上方(above)提供可靠(即，成分和厚度一致)的电介质层的任何技术来形成。在一个实施例中，通过沉积法形成上层206B。在一个实施例中，沉积法选自由化学气相沉积法、原子层沉积法或物理气相沉积法组成的组。在一个备选实施例中，可在单个工序(即，在单个反应腔室中，而无需将衬底202多次引入到反应腔室中)中形成包括两个不同的电介质层、即下层206A和上层206B的栅极电介质层206。在一个实施例中，在原子层沉积(ALD)腔室中将衬底202暴露至水脉冲之后形成自然氧化物层(即，下层206A)。然后，可通过在ALD腔室中按顺序引入电介质前驱物来在自然氧化物层上方沉积电介质材料的上层206B。在一个特定实施例中，衬底202由硅组成，下层206A是厚度在3-10埃范围内的自然二氧化硅层，而上层206B是高K电介质层，其选自由氧化铪、硅酸铪、氧化镧、氧化锆、硅酸锆、氧化钽、钛酸锶钡、钛酸钡、钛酸锶、氧化钇、氧化铝、氧化铅钪钽、铌酸铅锌或其组合组成的组。
接着，如图2B所描绘，可在栅极电介质层206上方形成栅电极208。出于说明的目的，将栅极电介质层206描绘成单层薄膜(即，如图2A所示)，但应明白，它可包括多于一个层，如结合图2A’所论述。栅电极208可包括结合图1A-B中的导电区域108论述的任何材料。栅电极208可通过适于在栅极电介质层206的上表面上方提供导电区域而不会不利地影响栅极电介质层206的任何技术来形成。根据本发明的一个实施例，通过沉积表层薄膜、接着在随后将表层薄膜图案化以形成所需形状和尺寸的导电结构来形成栅电极208。在一个实施例中，如图2B所描绘，在图案化栅电极208期间还图案化栅极电介质层206以暴露衬底202的上表面。在一个具体实施例中，利用包括施加氢氟酸、氟化铵或两者的水溶液的湿化学清洗工序来图案化栅极电介质层206。同样如图2B所描绘，可在栅电极208上方形成栅电极保护层216。栅电极保护层216可包括结合图1B中的栅电极保护层116论述的任何材料。根据本发明的一个实施例，栅电极保护层216是来自用于形成栅电极208的图案化工序的人工产物。在一个备选实施例中，通过化学气相沉积法来在栅电极208上方图案化后(post-patterning)形成栅电极隔离层216。
参照图2C，可相邻于栅电极208的侧壁形成一对牺牲栅极隔离间隔物222。牺牲栅极隔离间隔物222可包括结合图1B中的栅极隔离间隔物118论述的任何材料。根据本发明的一个实施例，牺牲栅极隔离间隔物222用于在如下文论述的随后的衬底蚀刻步骤期间保护栅电极208。因此，在一个备选实施例中，栅电极208很坚固而能抵抗衬底蚀刻步骤，并且不需要这对牺牲栅极隔离间隔物222。这对牺牲栅极隔离间隔物222可通过适于提供对栅电极208的侧壁的全部覆盖的任何技术来形成。在一个实施例中，通过沉积、随后各向异性地蚀刻表层电介质薄膜来形成牺牲栅极隔离间隔物222。在另一个实施例中，通过在氧化工艺中消耗/钝化栅电极208的一部分来形成牺牲栅极隔离间隔物222。
图2C是沿图2C’中示出的俯视图的A-A’轴截取的横截面图。如图所描绘，可在衬底202中形成浅沟槽隔离区域224和226。根据本发明的一个实施例，为了使栅电极208和下面的栅极电介质层206能在随后的衬底蚀刻步骤期间保持圆滑(in tact)，必须存在浅沟槽隔离区域226。隔离型器件也可包括浅沟槽隔离区域224，并且出于说明的目的，将在前面包含该特征。但是，将了解，在嵌套式结构的情况下，不需要存在浅沟槽隔离区域224，并且衬底202可沿如图2C’所示的虚线延伸。本领域的技术人员将明白，通常是先在衬底202中形成浅沟槽隔离区域224和226，然后再形成电介质层206。例如，根据本发明的一个实施例，通过用化学气相沉积法沉积的电介质材料(如二氧化硅材料)填充在衬底202中形成的沟槽来形成浅沟槽隔离区域224和226。
参照图2D，可除去衬底202的一部分，以便直接在衬底202、栅极电介质层206和浅沟槽隔离区域224之间形成沟槽228。栅极电介质层206、栅电极208、牺牲栅极隔离间隔物222和栅电极保护层216的一部分悬浮在沟槽228上方，而这些结构的另一部分通过浅沟槽隔离区域226(如图2C’所示)紧固，如虚线所描绘。沟槽228可通过适于选择性地除去衬底202的一部分而不会显著影响栅极电介质层206或栅电极208的任何技术(如干蚀刻或湿蚀刻法)来形成。根据本发明的一个实施例，栅电极保护层216和牺牲栅极隔离间隔物222在沟槽208形成期间保护栅电极208。在一个实施例中，通过利用选自由NF3、HBr、SF6/Cl或Cl2组成的组中的气体的干等离子体蚀刻步骤来形成沟槽228。在一个具体实施例中，如图2D所描绘，均匀除去衬底202的多个部分，而留下在所有位置具有相等厚度的沟槽228。在另一个实施例中，使用利用NH4OH或四甲基氢氧化铵的水溶液的湿蚀刻步骤来形成沟槽228。在一个实施例中，这些湿蚀刻剂受到衬底202的高密度平面(如硅衬底中的<111>面)的抑制，并且沟槽228因此呈现锥形分布，如图2D’所描绘。在一个具体实施例中，通过对由晶体硅组成的衬底202施加温度在摄氏20-35度范围内、浓度在10-30％范围内的NH4OH水溶液来形成沟槽228，并且锥形分布为55度的表面角。但是，出于说明的目的，在随后步骤中示出图2D中的均匀沟槽228。沟槽228可形成为足以从衬底202除去所有沟道活性和/或足以容纳由不同半导体材料组成的源极/漏极区域的深度，这如下文所论述。在一个实施例中，将沟槽228形成为在800-1200埃范围内的深度。
参照图2E，在沟槽228中、直接在衬底202与栅极电介质层206之间形成有源区域204。有源区域204可由结合图1A-B中的有源区域104论述的任何材料组成。另外，有源区域204中可加入电荷载流子掺杂剂杂质原子。在一个实施例中，有源区域204是化学计量比为SixGe1-x的晶体硅/锗有源区域，其中0≤x≤1，并且电荷载流子掺杂剂杂质原子选自由硼、砷、铟或磷组成的组。在另一个实施例中，有源区域204由III-V族材料组成，并且电荷载流子掺杂剂杂质原子选自由碳、硅、锗、氧、硫、硒或碲组成的组。根据本发明的一个实施例，有源区域204由成分不同于衬底202的半导体材料的半导体材料组成，并且与电介质层206相容。
有源区域204可通过适于形成非常均匀(即，低表面缺陷密度，例如在有源区域204的表面处小于106个位错/cm2)的晶体层的任何技术形成。在一个实施例中，有源区域204是均匀的外延层。在另一个实施例中，有源区域204是分级的外延层，其中分级法将表面缺陷减至最少。在一个备选实施例中，有源区域204在衬底202的界面处的缺陷密度大于108个位错/cm2，但是有源区域204的上表面的缺陷密度小于105个位错/cm2。在一个实施例中，通过选自由化学气相外延法、分子束外延法或激光废除外延法组成的组中的方法来沉积源区域204。在一个实施例中，在进行湿化学清洗之后立即沉积有源区域204。在一个具体实施例中，湿化学清洗工序包括施加氢氟酸、氟化铵或两者的水溶液。
在沟槽228形成期间和/或在有源区域204沉积期间采用牺牲栅极隔离间隔物222来保护栅电极208的情况下，可在沉积有源区域204之后除去这些间隔物，如图2F所描绘。根据本发明的一个实施例，除去牺牲栅极隔离间隔物222以使得能够优化如下文所论述的尖端植入步骤。在一个实施例中，利用包括施加氢氟酸、氟化铵或两者的水溶液的湿化学清洗工序来除去牺牲栅极隔离间隔物222，以便暴露栅电极208的侧壁。
参照图2G，可通过在有源区域204中植入电荷载流子掺杂剂杂质原子来形成一对尖端延伸部212。这对尖端延伸部212可由结合图1B中的那对尖端延伸部112论述的任何电荷载流子掺杂剂杂质原子形成。根据本发明的一个实施例，栅电极208用于掩盖有源区域204的一部分，以便形成自对准尖端延伸部212。通过将尖端延伸部212与栅电极208自对准，可在有源区域204的位于栅电极208和栅极电介质层206下方的那部分中形成沟道区域214，如图2G所描绘。在一个实施例中，经植入以形成这对尖端延伸部212的电荷载流子掺杂剂杂质原子具有与沟道区域214相反的导电性。在一个具体实施例中，通过植入能量在0.2keV-10keV范围内、用量在5E14个原子/cm2-5E15个原子/cm2范围内的电荷载流子掺杂剂杂质原子以形成在1E20个原子/cm3-1E21个原子/cm3范围内的掺杂剂浓度和在5-30纳米范围内的厚度来形成这对尖端延伸部212。为了激活植入有电荷载流子掺杂剂杂质原子的有源区域204以形成这对尖端延伸部212，可使用任何合适的退火技术。根据本发明的一个实施例，用来使这对尖端延伸部212的电荷载流子掺杂剂杂质原子变成取代地结合于有源区域204的原子晶格的退火技术选自由热退火、激光退火或快速退火组成的组。
接着，可形成一对栅极隔离间隔物。在一个实施例中，参照图2H，通过化学气相沉积法来沉积电介质材料层230，该层230与栅电极208的侧壁和有源区域204的上表面共形。电介质材料层230可由结合图1B中的那对栅极隔离间隔物118论述的任何材料组成。电介质材料层230可沉积至经选择以确定这对栅极隔离间隔物的最终宽度的厚度。
参照图2I，可通过各向异性蚀刻法由电介质材料层230形成一对栅极隔离间隔物218。在一个实施例中，通过远程等离子体蚀刻或反应性离子蚀刻法来干式蚀刻电介质材料层230。在另一个实施例中，通过利用包括通式为CxFy(其中x和y是自然数)的氟碳化合物的垂直干式或等离子体蚀刻法来将电介质材料层230图案化以形成这对栅极隔离间隔物218。这对栅极隔离间隔物218可位于有源区域204的上表面上方，并且其在有源区域204的上表面处的宽度可基本等于电介质材料层230的原始厚度。根据本发明的一个实施例，如图2I所描绘，这对栅极隔离间隔物218位于这对尖端延伸部212的上方。在一个实施例中，这对栅极隔离间隔物218与栅电极208和有源区域204的上表面形成密封以封装栅极电介质层206。
接着，结合图2I描述的结构可经历用于完成MOS-FET的形成的典型的工序，例如用于在有源区域204中形成一对源极/漏极区域的植入步骤和硅化步骤。或者，可在有源区域204中形成诱导应变(strain-inducing)的源极/漏极区域。参照图2J，在有源区域204中形成一对蚀空区域(etched-out region)240，其与这对栅极隔离间隔物218的外表面对准，从而令这对尖端延伸部212的位于这对栅极隔离间隔物218下方的那些部分受到保护。在一个实施例中，栅电极保护层216在形成蚀空区域240期间保护栅电极208。根据本发明的一个实施例，蚀空区域240形成在600-1100埃范围内、不会暴露衬底202的深度。在一个具体实施例中，各向同性地除去有源区域204的一些部分，而留下具有弯曲度的蚀空区域240，如图2J所描绘。在另一个实施例中，使用利用NH4OH或四甲基氢氧化铵的水溶液的湿式蚀刻步骤来形成蚀空区域240。在一个实施例中，这些湿蚀刻剂受到有源区域204的高密度平面的抑制，并且蚀空区域240因此呈现锥形分布。但是，出于说明的目的，在随后的步骤中示出图2J中的弯曲的蚀空区域240。
在晶体半导体材料的蚀空部分中形成的诱导应变的源极/漏极区域可赋予晶体半导体材料的沟道区域单轴应变。反之，晶体半导体材料又可赋予诱导应变的源极/漏极区域单轴应变。在一个实施例中，诱导应变的源极/漏极区域的晶格常数小于晶体半导体材料的晶格常数，并且诱导应变的源极/漏极区域赋予晶体半导体材料拉伸单轴应变，而晶体半导体材料赋予诱导应变的源极/漏极区域拉伸应变。因此，当填充晶体半导体材料的蚀空部分的诱导应变的源极/漏极区域的晶格常数小于晶体半导体材料的晶格常数时，诱导应变的源极/漏极区域的晶格形成原子从它们的正常的静止状态被拉开(即，拉伸应变)，并且因此当它们试图放松时在晶体半导体材料上诱导拉伸应变。在另一个实施例中，诱导应变的源极/漏极区域的晶格常数大于晶体半导体材料的晶格常数，并且诱导应变的源极/漏极区域赋予晶体半导体材料压缩单轴应变，而晶体半导体材料赋予诱导应变的源极/漏极区域压缩应变。因此，当填充晶体半导体材料的蚀空部分的诱导应变的源极/漏极区域的晶格常数大于晶体半导体材料的晶格常数时，诱导应变的源极/漏极区域的晶格形成原子从它们的正常的静止状态被挤压在一起(即，压缩应变)，并且因此当它们试图放松时在晶体半导体材料上诱导压缩应变。
因此，参照图2K，在蚀空区域240中形成一对源极/漏极区域220。这对源极/漏极区域220可由结合图1B中的那对源极/漏极区域120论述的任何材料组成。另外，根据本发明的一个实施例，这对源极/漏极区域220的成分不同于有源区域204的半导体材料的成分，并且赋予沟道区域214单轴应变。这对源极/漏极区域220可通过适于形成非常均匀(即，低表面缺陷密度，例如在这对源极/漏极区域220的表面处少于106个位错/cm2)的晶体层的任何技术来形成。在一个实施例中，这对源极/漏极区域220包括均匀的外延层。在另一个实施例中，这对源极/漏极区域220包括分级的外延层，其中分级法将表面缺陷减至最少。在一个实施例中，通过选自由化学气相外延法、分子束外延法或激光废除外延法组成的组中的方法来沉积这对源极/漏极区域220。在一个实施例中，在进行湿化学清洗之后立即沉积这对源极/漏极区域220。在一个具体实施例中，湿化学清洗工序包括施加氢氟酸、氟化铵或两者的水溶液。这对源极/漏极区域220中可加入电荷载流子掺杂剂杂质原子。在一个实施例中，这对源极/漏极区域220是化学计量比为SixGe1-x的晶体硅/锗区域，其中0≤x≤1，并且电荷载流子掺杂剂杂质原子选自由硼、砷、铟或磷组成的组。在另一个实施例中，这对源极/漏极区域220由III-V族材料组成，并且电荷载流子掺杂剂杂质原子选自由碳、硅、锗、氧、硫、硒或碲组成的组。可在形成这对源极/漏极区域220的同时(即，原位)或作为后离子植入步骤将电荷载流子掺杂剂杂质原子结合于这对源极/漏极区域220中。
接着，结合图2K描述的结构可经历用于完成MOS-FET的形成的典型的工艺，如硅化步骤。或者，在形成这对源极/漏极区域220之后，可进行与取代栅极工艺方案相容的工序。根据本发明的一个实施例，如图2L所描绘，在这对源极/漏极区域220、浅沟槽隔离区域224、这对栅极隔离间隔物218和栅电极保护层216和/或栅电极208上方形成层间电介质层250(如二氧化硅层)。然后，如图2M所描绘，可返回抛光层间电介质层250，并利用化学机械抛光步骤除去栅电极保护层216，以露出栅电极208。在一个实施例中，栅电极保护层216用作抛光中止层，并且随后使用湿蚀刻法来除去栅电极保护层216，以便露出栅电极208的上表面。
参照图2N，可除去栅电极208并用备选栅电极260来取代。根据本发明的一个实施例，备选栅电极260由结合图1A-B中的导电区域108论述的任何材料组成。另外，在除去栅电极208之后、在用备选栅电极260取代之前，可在栅极电介质层206中添加额外的电介质层270。根据本发明的一个实施例，额外的电介质层270可由结合图1B中的上层106B论述的任何材料组成。额外的电介质层260可通过原子层或化学气相沉积法形成，并且因此也可形成在这对栅极隔离间隔物218的内壁上，如图2N所描绘。
因此，参照图2N，可形成包括具有相容的栅极电介质层的有源区域的平面MOS-FET。平面MOS-FET可以是N型或P型半导体器件，并且可以通过本领域中已知的常规处理步骤结合于集成电路。将明白，在典型的集成电路中，可在单个衬底或外延层中制作N-和P-沟道晶体管以形成CMOS集成电路。
本发明不限于形成包括具有相容的栅极电介质层的有源区域的平面MOS-FET。例如，具有三维体系结构的诸如三栅极器件的器件也可得益于以上方法。作为根据本发明的一个示范性实施例，图3A-C示出表示形成包含具有相容的电介质层的有源区域的三栅极MOS-FET的横截面图。
参照图3A，形成单衬底三栅极MOS-FET 300的基座。三栅极MOS-FET 300由三维衬底302组成。三维衬底302可由结合图1A-B中的衬底102描述的任何材料形成。在三维衬底302的周围形成栅极电介质层306。栅极电介质层306可由结合图1A-B中的电介质层106、下层106A和上层106B描述的任何材料形成。在栅极电介质层306上方形成栅电极308。栅电极308可由结合图1A-B中的导电区域108描述的任何材料形成。栅极电介质层306和栅电极308可通过一对栅极隔离间隔物318进行保护。
参照图3B，可除去三维衬底302的部分以形成沟槽328。沟槽328可通过结合图2D和2D’中的沟槽228的形成描述的任何技术来形成。参照图3C，在沟槽328中和三维衬底302的剩余部分上选择性地形成三维有源区域304。因此，描述了用于形成包含具有相容的栅极电介质层的有源区域的三栅极MOS-FET器件的方法。三栅极MOS-FET可通过本领域中已知的常规处理步骤结合于集成电路。
因此，公开了用于形成具有有源区域和相容的电介质层的半导体结构的方法。在一个实施例中，半导体结构具有由第一半导体材料的氧化物组成的电介质层，其中在电介质层与第一半导体材料之间形成有第二(且成分不同的)半导体材料。在另一个实施例中，用第三半导体材料取代第二半导体材料的一部分，以便赋予第二半导体材料的晶格结构单轴应变。

Claims (41)

1.一种半导体结构，包括：
用半导体材料形成的衬底；
直接在所述衬底上并由III-V族材料构成的有源区域，其中所述有源区域的成分不同于所述衬底的成分；以及
直接布置在所述有源区域上的电介质层，其中在所述电介质层和所述有源区域的界面处，所述电介质层包括所述衬底的氧化物层。
2.如权利要求1所述的半导体结构，其中所述衬底由硅组成，并且所述氧化物层选自由二氧化硅或氧氮化硅层组成的组。
3.如权利要求2所述的半导体结构，其中所述衬底中硅原子的原子浓度大于97％。
4.如权利要求1所述的半导体结构，其中所述III-V族材料选自由以下材料组成的组：氮化镓、磷化镓、砷化镓、磷化铟、锑化铟、砷化铟镓、砷化铝镓和磷化铟镓。
5.如权利要求4所述的半导体结构，其中所述衬底由硅组成，并且所述氧化物层选自由二氧化硅或氧氮化硅层组成的组。
6.如权利要求1所述的半导体结构，其中所述电介质层还包括布置在所述衬底的所述氧化物层上方的高K电介质材料层。
7.如权利要求6所述的半导体结构，其中所述衬底由硅组成，所述氧化物层选自由二氧化硅或氧氮化硅层组成的组，并且所述高K电介质材料选自由以下材料组成的组：氧化铪、硅酸铪、氧化镧、氧化锆、硅酸锆、氧化钽、钛酸锶钡、钛酸钡、钛酸锶、氧化钇、氧化铝、氧化铅钪钽、铌酸铅锌或其组合。
8.一种半导体器件，包括：
用半导体材料形成的衬底；
直接布置在所述衬底上并由III-V族材料构成的有源区域，其中所述有源区域的成分不同于所述衬底的成分；
直接布置在所述有源区域上的栅极电介质层，其中在所述栅极电介质层和所述有源区域的界面处，所述栅极电介质层由所述衬底的氧化物层组成；
位于所述栅极电介质层上方的栅电极；
在所述有源区域中、在所述栅电极的两侧上的一对尖端延伸部；
位于所述一对尖端延伸部的上方、与所述栅电极的侧壁相邻的一对栅极隔离间隔物；以及
在所述有源区域中、在所述一对栅极隔离间隔物的两侧上的一对源极/漏极区域。
9.如权利要求8所述的半导体器件，其中所述衬底由硅组成，并且所述氧化物层选自由二氧化硅或氧氮化硅层组成的组。
10.如权利要求9所述的半导体器件，其中所述衬底中硅原子的原子浓度大于97％。
11.如权利要求8所述的半导体器件，其中所述III-V族材料选自由以下材料组成的组：氮化镓、磷化镓、砷化镓、磷化铟、锑化铟、砷化铟镓、砷化铝镓和磷化铟镓。
12.如权利要求11所述的半导体器件，其中所述衬底由硅组成，并且所述氧化物层选自由二氧化硅或氧氮化硅层组成的组。
13.如权利要求8所述的半导体器件，其中所述栅极电介质层还包括位于所述衬底的所述氧化物层上方的高K电介质材料层。
14.如权利要求13所述的半导体器件，其中所述衬底由硅组成，所述氧化物层选自由二氧化硅或氧氮化硅层组成的组，并且所述高K电介质材料选自由以下材料组成的组：氧化铪、硅酸铪、氧化镧、氧化锆、硅酸锆、氧化钽、钛酸锶钡、钛酸钡、钛酸锶、氧化钇、氧化铝、氧化铅钪钽、铌酸铅锌或其组合。
15.如权利要求8所述的半导体器件，其中所述一对源极/漏极区域由不同于所述有源区域的半导体材料的半导体材料组成。
16.一种制造半导体结构的方法，包括：
形成包含第一半导体材料的衬底；
在所述衬底上方形成电介质层，其中所述电介质层包括直接位于所述衬底上的所述第一半导体材料的氧化物层；
除去所述衬底的一部分以便在所述电介质层与所述衬底的剩余部分之间形成沟槽；以及
在所述沟槽中形成有源区域，其中所述有源区域由III-V族材料构成，所述III-V族材料的成分不同于所述第一半导体材料的成分，并且所述有源区域直接形成在所述电介质层与所述衬底的剩余部分之间。
17.如权利要求16所述的方法，其中形成所述电介质层包括：在有氧化剂的情况下加热所述衬底，直到形成所需厚度的所述氧化物层为止。
18.如权利要求17所述的方法，其中所述衬底由硅组成，所述氧化物层选自由二氧化硅或氧氮化硅层组成的组，加热所述衬底是在摄氏600-800度范围内的温度、历时1分钟-1小时的时间进行的，并且所述氧化物层形成5-15埃范围内的厚度。
19.如权利要求18所述的方法，还包括：
在形成所述氧化物层之后，在所述氧化物层上方形成高K电介质材料层，其中所述高K电介质材料选自由氧化铪、硅酸铪、氧化镧、氧化锆、硅酸锆、氧化钽、钛酸锶钡、钛酸钡、钛酸锶、氧化钇、氧化铝、氧化铅钪钽、铌酸铅锌或其组合组成的组。
20.如权利要求16所述的方法，其中形成所述电介质层包括在ALD反应腔室中在自然二氧化硅层上方形成高K电介质材料层，其中所述高K电介质材料选自由氧化铪、硅酸铪、氧化镧、氧化锆、硅酸锆、氧化钽、钛酸锶钡、钛酸钡、钛酸锶、氧化钇、氧化铝、氧化铅钪钽、铌酸铅锌或其组合组成的组，并且所述自然二氧化硅层的厚度在3-10埃范围内。
21.如权利要求16所述的方法，其中所述第一半导体材料由硅原子的原子浓度大于97％的硅组成，并且所述氧化物层选自由二氧化硅或氧氮化硅层组成的组。
22.如权利要求16所述的方法，其中所述III-V族材料选自由氮化镓、磷化镓、砷化镓、磷化铟、锑化铟、砷化铟镓、砷化铝镓和磷化铟镓组成的组，并且所述氧化物层选自由二氧化硅或氧氮化硅层组成的组。
23.如权利要求16所述的方法，其中所述电介质层还包括位于所述第一半导体材料的所述氧化物层上方的高K电介质材料层。
24.如权利要求23所述的方法，其中所述第一半导体材料由硅组成，所述氧化物层选自由二氧化硅或氧氮化硅层组成的组，并且所述高K电介质材料选自由氧化铪、硅酸铪、氧化镧、氧化锆、硅酸锆、氧化钽、钛酸锶钡、钛酸钡、钛酸锶、氧化钇、氧化铝、氧化铅钪钽、铌酸铅锌或其组合组成的组。
25.一种制造半导体器件的方法，包括：
形成包含第一半导体材料的衬底；
在所述衬底上方形成栅极电介质层，其中所述栅极电介质层包括直接位于所述衬底上的所述第一半导体材料的氧化物层；
在所述栅极电介质层上方形成栅电极；以及在形成所述栅电极之启，
除去所述衬底的一部分以便在所述栅极电介质层与所述衬底的剩余部分之间形成沟槽；
在所述沟槽中形成有源区域，其中所述有源区域由III-V族材料构成，所述III-V族材料的成分不同于所述第一半导体材料的成分，并且所述有源区域直接形成在所述电介质层与所述衬底的剩余部分之间；
在所述有源区域中、在所述栅电极的两侧上形成一对尖端延伸部；
在所述一对尖端延伸部的上方、相邻于所述栅电极的侧壁形成一对栅极隔离间隔物；以及
在所述有源区域中、在所述一对栅极隔离间隔物的两侧上形成一对源极/漏极区域。
26.如权利要求25所述的方法，其中形成所述栅极电介质层包括：在有氧化剂的情况下加热所述衬底，直到形成所需厚度的所述氧化物层为止。
27.如权利要求26所述的方法，其中所述衬底由硅组成，所述氧化物层选自由二氧化硅或氧氮化硅层组成的组，加热所述衬底是在摄氏600-800度范围内的温度、历时1分钟-1小时的时间进行的，并且所述氧化物层形成5-15埃范围内的厚度。
28.如权利要求27所述的方法，还包括：
在形成所述氧化物层之后，在所述氧化物层上方形成高K电介质材料层，其中所述高K电介质材料选自由氧化铪、硅酸铪、氧化镧、氧化锆、硅酸锆、氧化钽、钛酸锶钡、钛酸钡、钛酸锶、氧化钇、氧化铝、氧化铅钪钽、铌酸铅锌或其组合组成的组。
29.如权利要求25所述的方法，其中形成所述电介质层包括在ALD反应腔室中在自然二氧化硅层上方形成高K电介质材料层，其中所述高K电介质材料选自由氧化铪、硅酸铪、氧化镧、氧化锆、硅酸锆、氧化钽、钛酸锶钡、钛酸钡、钛酸锶、氧化钇、氧化铝、氧化铅钪钽、铌酸铅锌或其组合组成的组，并且所述自然二氧化硅层的厚度在3-10埃范围内。
30.如权利要求25所述的方法，其中形成所述一对源极/漏极区域包括除去所述有源区域的一部分以便在所述有源区域中形成一对沟槽以及在所述一对沟槽中形成第三半导体材料，并且所述第三半导体材料的成分不同于所述III-V族材料的成分。
31.如权利要求25所述的方法，还包括：
在形成所述一对源极/漏极区域之后，在所述一对源极/漏极区域、所述一对栅极隔离间隔物和所述栅电极上方形成层间电介质层；
抛光所述层间电介质层以暴露所述栅电极的上表面；
除去所述栅电极以在所述一对栅极隔离间隔物之间提供沟槽；以及
在所述沟槽中形成金属层以形成金属栅电极。
32.如权利要求31所述的方法，还包括：
在除去所述栅电极之后、在形成所述金属栅电极之前，直接在所述栅极电介质层上形成高K电介质材料层。
33.如权利要求25所述的方法，还包括：
在除去所述衬底的所述部分之前，相邻于所述栅电极的侧壁形成一对牺牲栅极隔离间隔物；以及
在所述栅电极的两侧上形成所述一对尖端延伸部之前，除去所述一对牺牲栅极隔离间隔物。
34.如权利要求25所述的方法，其中所述第一半导体材料由硅原子的原子浓度大于97％的硅组成，并且所述氧化物层选自由二氧化硅或氧氮化硅层组成的组。
35.如权利要求25所述的方法，其中所述III-V族材料选自由氮化镓、磷化镓、砷化镓、磷化铟、锑化铟、砷化铟镓、砷化铝镓和磷化铟镓组成的组，并且所述氧化物层选自由二氧化硅或氧氮化硅层组成的组。
36.如权利要求25所述的方法，其中所述栅极电介质层还包括位于所述第一半导体材料的所述氧化物层上方的高K电介质材料层。
37.如权利要求36所述的方法，其中所述第一半导体材料由硅组成，所述氧化物层选自由二氧化硅或氧氮化硅层组成的组，并且所述高K电介质材料选自由氧化铪、硅酸铪、氧化镧、氧化锆、硅酸锆、氧化钽、钛酸锶钡、钛酸钡、钛酸锶、氧化钇、氧化铝、氧化铅钪钽、铌酸铅锌或其组合组成的组。
38.一种制造半导体器件的方法，包括：
形成包含第一半导体材料的衬底；
在所述衬底上方形成栅极电介质层；
在所述栅极电介质层上方形成栅电极；以及在形成所述栅电极之后，
除去所述衬底的一部分以便在所述栅极电介质层与所述衬底的剩余部分之间形成沟槽；
在所述沟槽中形成有源区域，其中所述有源区域由III-V族材料构成，所述III-V族材料的成分不同于所述第一半导体材料的成分，并且所述有源区域直接形成在所述电介质层与所述衬底的剩余部分之间；
在所述有源区域中、在所述栅电极的两侧上形成一对尖端延伸部；
在所述一对尖端延伸部的上方、相邻于所述栅电极的侧壁形成一对栅极隔离间隔物；以及
在所述有源区域中、在所述一对栅极隔离间隔物的两侧上形成一对源极/漏极区域，其中所述一对源极/漏极区域由第三半导体材料组成，并且所述第三半导体材料的成分不同于所述III-V族材料的成分。
39.如权利要求38所述的方法，其中所述第一半导体材料中硅原子的原子浓度大于97％。
40.如权利要求39所述的方法，其中所述III-V族材料选自由以下材料组成的组：氮化镓、磷化镓、砷化镓、磷化铟、锑化铟、砷化铟镓、砷化铝镓和磷化铟镓。
41.如权利要求38所述的方法，其中所述栅极电介质层由选自由以下材料组成的组中的材料组成：二氧化硅、氧氮化硅、氧化铪、硅酸铪、氧化镧、氧化锆、硅酸锆、氧化钽、钛酸锶钡、钛酸钡、钛酸锶、氧化钇、氧化铝、氧化铅钪钽、铌酸铅锌或其组合。
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US20150179742A1 (en) 2015-06-25
US9515142B2 (en) 2016-12-06
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US9646822B2 (en) 2017-05-09
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US20170207336A1 (en) 2017-07-20
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US9397165B2 (en) 2016-07-19
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