US20080121932A1 - Active regions with compatible dielectric layers - Google Patents

Active regions with compatible dielectric layers Download PDF

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Publication number
US20080121932A1
US20080121932A1 US11/523,105 US52310506A US2008121932A1 US 20080121932 A1 US20080121932 A1 US 20080121932A1 US 52310506 A US52310506 A US 52310506A US 2008121932 A1 US2008121932 A1 US 2008121932A1
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United States
Prior art keywords
semiconductor material
layer
oxide
comprised
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
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US11/523,105
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English (en)
Inventor
Pushkar Ranade
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Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to US11/523,105 priority Critical patent/US20080121932A1/en
Priority to EP07842712.7A priority patent/EP2064735B1/en
Priority to CN2007800345522A priority patent/CN101517717B/zh
Priority to PCT/US2007/078791 priority patent/WO2008036681A1/en
Priority to JP2009524824A priority patent/JP5484052B2/ja
Priority to KR1020097005500A priority patent/KR101060439B1/ko
Assigned to INTEL CORPORATION reassignment INTEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: RANADE, PUSHKAR
Publication of US20080121932A1 publication Critical patent/US20080121932A1/en
Priority to US14/624,530 priority patent/US9287364B2/en
Priority to US15/018,408 priority patent/US9397165B2/en
Priority to US15/199,168 priority patent/US9515142B2/en
Priority to US15/351,169 priority patent/US9646822B2/en
Priority to US15/473,503 priority patent/US9847420B2/en
Abandoned legal-status Critical Current

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Definitions

  • Dielectric layer 106 may be comprised of two distinct dielectric layers, a lower layer 106 A and an upper layer 106 B.
  • lower layer 106 A is comprised of comprised of an oxide of a semiconductor material.
  • lower layer 106 A is comprised of silicon dioxide or silicon oxy-nitride.
  • lower layer 106 A is comprised of an oxide layer of the semiconductor material of substrate 102 .
  • substrate 102 is comprised of silicon and lower layer 106 A is comprised of silicon dioxide or silicon oxy-nitride.
  • lower layer 106 A is comprised of an oxide layer that is directly above active region 104 .
  • the charge carrier dopant impurity atoms implanted to form the pair of tip extensions 212 are of opposite conductivity to channel region 214 .
  • the pair of tip extensions 212 is formed by implanting charge-carrier dopant impurity atoms with an energy in the range of 0.2 keV-10 keV at a dose in the range of 5E14 atoms/cm 2 -5E15 atoms/cm 2 to form a dopant concentration in the range of 1E20 atoms/cm 3 -1E21 atoms/cm 3 and to a depth in the range of 5-30 nanometers.
  • the pair of source/drain regions 220 comprises a uniform epitaxial layer. In another embodiment, the pair of source/drain regions 220 comprises a graded epitaxial layer, wherein the grading process minimizes surface defects. In an embodiment, the pair of source/drain regions 220 is deposited by a process selected from the group consisting of chemical vapor epitaxy, molecular-beam epitaxy or laser-abolition epitaxy. In one embodiment, a wet chemical clean is carried out immediately prior to the deposition of the pair of source/drain regions 220 .

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Nanotechnology (AREA)
  • General Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Recrystallisation Techniques (AREA)
US11/523,105 2005-02-17 2006-09-18 Active regions with compatible dielectric layers Abandoned US20080121932A1 (en)

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US11/523,105 US20080121932A1 (en) 2006-09-18 2006-09-18 Active regions with compatible dielectric layers
KR1020097005500A KR101060439B1 (ko) 2006-09-18 2007-09-18 융화성있는 유전체 층들을 갖는 활성 영역들
CN2007800345522A CN101517717B (zh) 2006-09-18 2007-09-18 具有相容电介质层的有源区域
PCT/US2007/078791 WO2008036681A1 (en) 2006-09-18 2007-09-18 Active regions with compatible dielectric layers
JP2009524824A JP5484052B2 (ja) 2006-09-18 2007-09-18 半導体構造、半導体デバイス、半導体構造製造方法、半導体デバイス製造方法
EP07842712.7A EP2064735B1 (en) 2006-09-18 2007-09-18 Active regions with compatible dielectric layers
US14/624,530 US9287364B2 (en) 2006-09-18 2015-02-17 Active regions with compatible dielectric layers
US15/018,408 US9397165B2 (en) 2006-09-18 2016-02-08 Active regions with compatible dielectric layers
US15/199,168 US9515142B2 (en) 2005-02-17 2016-06-30 Active regions with compatible dielectric layers
US15/351,169 US9646822B2 (en) 2006-09-18 2016-11-14 Active regions with compatible dielectric layers
US15/473,503 US9847420B2 (en) 2006-09-18 2017-03-29 Active regions with compatible dielectric layers

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US14/624,530 Expired - Fee Related US9287364B2 (en) 2006-09-18 2015-02-17 Active regions with compatible dielectric layers
US15/018,408 Expired - Fee Related US9397165B2 (en) 2005-02-17 2016-02-08 Active regions with compatible dielectric layers
US15/199,168 Expired - Fee Related US9515142B2 (en) 2005-02-17 2016-06-30 Active regions with compatible dielectric layers
US15/351,169 Active US9646822B2 (en) 2006-09-18 2016-11-14 Active regions with compatible dielectric layers
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US15/018,408 Expired - Fee Related US9397165B2 (en) 2005-02-17 2016-02-08 Active regions with compatible dielectric layers
US15/199,168 Expired - Fee Related US9515142B2 (en) 2005-02-17 2016-06-30 Active regions with compatible dielectric layers
US15/351,169 Active US9646822B2 (en) 2006-09-18 2016-11-14 Active regions with compatible dielectric layers
US15/473,503 Expired - Fee Related US9847420B2 (en) 2006-09-18 2017-03-29 Active regions with compatible dielectric layers

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US (6) US20080121932A1 (zh)
EP (1) EP2064735B1 (zh)
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KR (1) KR101060439B1 (zh)
CN (1) CN101517717B (zh)
WO (1) WO2008036681A1 (zh)

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US20090189189A1 (en) * 2008-01-29 2009-07-30 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof
US20100258168A1 (en) * 2009-04-09 2010-10-14 Sierra Solar Power, Inc. Silicon-based dielectric stack passivation of si-epitaxial thin-film solar cells
US20100276732A1 (en) * 2007-12-26 2010-11-04 Yuji Ando Semiconductor device
US20110133162A1 (en) * 2009-12-04 2011-06-09 International Business Machines Corporation Gate-All-Around Nanowire Field Effect Transistors
US20110133164A1 (en) * 2009-12-04 2011-06-09 International Business Machines Corporation Omega Shaped Nanowire Field Effect Transistors
US20110133165A1 (en) * 2009-12-04 2011-06-09 International Business Machines Corporation Self-aligned contacts for nanowire field effect transistors
US20110133167A1 (en) * 2009-12-04 2011-06-09 International Business Machines Corporation Planar and nanowire field effect transistors
US20110133161A1 (en) * 2009-12-04 2011-06-09 International Business Machines Corporation Omega Shaped Nanowire Tunnel Field Effect Transistors
US20110133169A1 (en) * 2009-12-04 2011-06-09 International Business Machines Corporation Gate-All-Around Nanowire Tunnel Field Effect Transistors
US20110168982A1 (en) * 2010-01-08 2011-07-14 International Business Machines Corporation Nanowire pin tunnel field effect devices
US20110223736A1 (en) * 2010-03-09 2011-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. LDD Epitaxy for FinFETs
US20110233522A1 (en) * 2010-03-25 2011-09-29 International Business Machines Corporation p-FET with a Strained Nanowire Channel and Embedded SiGe Source and Drain Stressors
US20120146101A1 (en) * 2010-12-13 2012-06-14 Chun-Hsien Lin Multi-gate transistor devices and manufacturing method thereof
US8324030B2 (en) 2010-05-12 2012-12-04 International Business Machines Corporation Nanowire tunnel field effect transistors
US8324940B2 (en) 2010-04-13 2012-12-04 International Business Machines Corporation Nanowire circuits in matched devices
US8361907B2 (en) 2010-05-10 2013-01-29 International Business Machines Corporation Directionally etched nanowire field effect transistors
US8513068B2 (en) 2010-09-17 2013-08-20 International Business Machines Corporation Nanowire field effect transistors
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