CN106653694A - Cmos纳米线结构 - Google Patents
Cmos纳米线结构 Download PDFInfo
- Publication number
- CN106653694A CN106653694A CN201710010690.2A CN201710010690A CN106653694A CN 106653694 A CN106653694 A CN 106653694A CN 201710010690 A CN201710010690 A CN 201710010690A CN 106653694 A CN106653694 A CN 106653694A
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- nano wire
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
- H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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Abstract
描述了互补金属氧化物半导体纳米线结构。例如,第一半导体器件包含设置于基底上方的第一纳米线。所述第一纳米线在所述基底上方的第一距离处具有中点,并且所述第一纳米线包含分离的沟道区和在所述分离的沟道区的两侧上的源区和漏区。第一栅电极叠层完全围绕所述第一纳米线的所述分离的沟道区。所述半导体结构还含第二半导体器件。所述第二半导体器件包含设置于所述基底上方的第二纳米线。所述第二纳米线在所述基底上方的第二距离处具有中点,并且所述第二纳米线包括分离的沟道区和在所述分离的沟道区的两侧上的源区和漏区。所述第一距离不同于所述第二距离。第二栅电极叠层完全围绕所述第二纳米线的所述分离的沟道区。
Description
本申请为分案申请,其原申请是2014年6月20日进入中国国家阶段、国际申请日为2011年12月23日的国际专利申请PCT/US2011/067225,该原申请的中国国家申请号是201180075765.6,发明名称为“CMOS纳米线结构”。
技术领域
本发明的实施例是纳米线(nanowire)半导体器件领域,并且特别是互补金属氧化物半导体(CMOS)纳米线结构。
背景技术
对于过去的数十年,集成电路中的特征的按比例制作(scaling)是不断增长的半导体工业后面的驱动力。按比例制作至越来越小的特征使得能够在半导体芯片的有限的占用面积(real estate)上实现功能单元的增大的密度。例如,缩小晶体管尺寸容许在芯片上并入增大数量的存储器件,适于以增大容量制造产品。然而,对不断增大的容量的驱动不是没有问题的。必需优化每一个器件的性能变得日益重要。
随着微电子器件尺度按比例制作越过15纳米(nm)的节点,保持迁移率提高和短沟道控制在器件制造中提供了挑战。用于制造器件的纳米线提供了提高的短沟道控制。例如,硅锗(SixGe1-x)纳米线沟道结构(其中,x<0.5)在适用于利用较高电压操作的许多常规产品中的相当大的(respectable)Eg处提供了迁移率增高。此外,硅锗(SixGe1-x)纳米线沟道(其中,x>0.5)在例如适合用于移动/手持领域中的低电压产品的较低Eg处提供了增高的迁移率。
许多不同的技术已经尝试提高晶体管的迁移率。然而,在对于半导体器件的电子和/或空穴迁移率提高的领域中仍然需要显著的提高。
发明内容
本发明的实施例包括互补金属氧化物半导体(CMOS)纳米线结构。
在实施例中,第一半导体器件包含设置于基底上方的第一纳米线。所述第一纳米线在所述基底上方的第一距离处具有中点,并且所述第一纳米线包含分离的沟道区和在所述分离的沟道区的两侧上的源区和漏区。第一栅电极叠层完全围绕所述第一纳米线的所述分离的沟道区。所述半导体结构还含第二半导体器件。所述第二半导体器件包含设置于所述基底上方的第二纳米线。所述第二纳米线在所述基底上方的第二距离处具有中点,并且所述第二纳米线包括分离的沟道区和在所述分离的沟道区的两侧上的源区和漏区。所述第一距离不同于所述第二距离。第二栅电极叠层完全围绕所述第二纳米线的所述分离的沟道区。
在另一实施例中,一种半导体结构包含第一半导体器件。所述第一半导体器件包含设置于基底上方的第一纳米线。所述第一纳米线具有分离的沟道区和在所述分离的沟道区的两侧上的源区和漏区。所述分离的沟道区由半导体主干材料构成。第一栅电极叠层完全围绕所述第一纳米线的所述分离的沟道区。所述半导体结构还包含第二半导体器件。所述第二半导体器件包含设置于所述基底上方的第二纳米线。所述第二纳米线具有分离的沟道区和在所述分离的沟道区的两侧上的源区和漏区。所述分离的沟道区由所述半导体主干材料以及未包含于所述第一半导体器件的所述沟道区中的围绕包覆材料层。第二栅电极叠层完全围绕所述第二纳米线的所述分离的沟道区。
在另一实施例中,一种制造CMOS纳米线半导体结构的方法,所述方法包含于基底上方形成第一有源层,所述第一有源层具有第一晶格常数。在所述第一有源层上形成第二有源层,所述第二有源层具有大于所述第一晶格常数的第二晶格常数。由所述第一有源层形成第一纳米线。所述第一纳米线包含分离的沟道区和在所述分离的沟道区的两侧上的源区和漏区。由所述第二有源层形成第二纳米线。所述第二纳米线包含分离的沟道区和在所述分离的沟道区的两侧上的源区和漏区。形成第一栅电极叠层,所述第一栅电极叠层完全围绕所述第一纳米线的所述分离的沟道区。形成第二栅电极叠层,所述第二栅电极叠层完全围绕所述第二纳米线的所述分离的沟道区。
附图说明
图1A示例了根据本发明的实施例的基于纳米线的半导体结构的三维横截面视图;
图1B示例了根据本发明的实施例的图1A的基于纳米线的半导体结构的沿a-a’轴取得的横截面沟道视图;
图1C示例了根据本发明的实施例的图1A的基于纳米线的半导体结构的沿b-b’轴取得的横截面间隔物视图;
图2示例了根据本发明的实施例的CMOS基于纳米线的半导体结构的横截面视图;
图3A-3F示例了根据本发明的实施例的表示制造CMOS纳米线半导体结构的方法中的各种操作的三维横截面视图;
图4示例了根据本发明的实施例的另一CMOS基于纳米线的半导体结构的三维横截面视图;
图5A和5B示例了根据本发明的另一实施例的表示制造另一CMOS纳米线半导体结构的方法中的各种操作的横截面视图;
图6示例了根据本发明的实施例的示例在CMOS纳米线结构的制造中在纳米线上形成包覆层的数个途径的横截面视图;
图7示例了根据本发明的一个实施的计算器件。
具体实施方式
描述了互补金属氧化物半导体(CMOS)纳米线结构。在以下描述中,提出了诸如具体的纳米线集成和材料状况(regime)的许多具体细节,以提供对本发明的实施例的彻底的理解。对本领域技术人员将明显的是,可以实践本发明的实施例而没有这些细节。在其它实例中,不详细描述诸如集成电路设计布局的公知的特征,以便不会不必要地使本发明的实施例模糊。此外,应当理解,图中示出的各种实施例是示例性的表示而不必是按照比例绘制的。
本发明的一个或更多实施例涉及对NMOS和PMOS利用独立的沟道材料的集成围栅(gate-all-around)纳米线CMOS结构。于此描述了高性能、低泄漏CMOS晶体管技术途径。在范例中,对从一个公共多层外延叠层开始的NMOS/PMOS利用不同的沟道材料。在另一范例中,独立地优化的沟道材料可以通过在主干(backbone)线上生长包覆外延层来提供较高电子和空穴迁移率的沟道形成。
于此处理了对NMOS和PMOS二者使用相同沟道材料的同时提高电子和空穴迁移率的困难。可以使用应变解决方案、较高迁移率的沟道材料、或较高迁移率的沟道取向来增高器件性能。例如,嵌入式SiGe(e-SiGe)、嵌入式Si-C(e-SiC)、应力记忆(memorization)、接触刻蚀停层(CESL)是当前的应变解决方案。也已经研究了SiGe、Ge和III-V、不同的取向、以及SiGe上的各种应变Si(或相反)。
在实施例中,代替对NMOS和PMOS独立地生长外延膜或并入嵌入式应变层,制造了多外延层结构(超晶格)并且随后使用用于NMOS纳米线器件的第一部分和用于PMOS纳米线器件的第二部分对其进行分解。归因于应变驰豫问题,特别是随着鳍状物几何结构变得更高,生长厚的应变层是困难的。应变驰豫可以在外延层中引起过量的缺陷并劣化器件性能、良率(yield)、和可靠性。虽然使用超晶格(例如Si/SiGe)对于制作不同材料的良好控制的应变层的问题是已知的,但是在实施例中,首先制造超晶格并且随后对其进行分割以分别对NMOS或PMSO最大化迁移率。
可以通过选择性地从多层外延叠层刻蚀牺牲层来形成纳米线/纳米带(nanoribbon)结构。外延层可以用作沟道或可以被选择性地去除以形成用于围栅结构的间隙。外延线之下的隔离层可以提供电隔离并形成用于围栅(all-around gate)的底部间隙。最简单的CMOS集成方案采用以相同材料制造的N/P MOS沟道。工艺对于制造是较简单的,因为其采用单个选择性刻蚀。然而,可能需要应变技术来提升器件性能。例如,当硅用于沟道材料时,PMOS通过压应力得到了增高,且NMOS通过沿沟道方向的张应力得到了增高,增高了载流子迁移率。
根据本发明的实施例,应用了开始材料叠层的独特特征来集成为了较高的迁移率而被优化的不同的NMOS和PMOS沟道材料。例如,在一个实施例中,NMOS器件的牺牲层用作PMOS沟道,且PMOS器件的牺牲层用作NMOS沟道。因为可以在处理期间去除牺牲层,所以使得沟道材料和优化的独立选择成为可能。
本发明的一个或更多实施例涉及提高对于NMOS或PMOS晶体管,或二者,的沟道迁移率。可以使用例如沟道区中的应变来提高迁移率。从而,于此描述的一个或更多途径在用于NMOS和PMOS晶体管二者的沟道区中提供了合适的应变。在实施例中,提供了应变NMOS和PMOS纳米线。
在第一方面,图1A示例了根据本发明的实施例的基于纳米线的半导体结构的三维横截面视图。图1B示例了图1A的基于纳米线的半导体结构的沿a-a’轴取得的横截面沟道视图。图1C示例了图1A的基于纳米线的半导体结构的沿b-b’轴取得的横截面间隔物视图。
参照图1A,半导体器件100包含设置于基底102上方的一个或更多竖直层叠的纳米线(104组)。于此的实施例针对单线器件和多线器件二者。作为范例,为示例目的示出了具有纳米线104A、104B和104C的基于三纳米线的器件。为描述方便,纳米线104A用作范例,其中描述仅集中于一个纳米线上。应当理解,在描述了一个纳米线的属性的地方,基于多个纳米线的实施例可以对于纳米线中的每一个纳米线具有相同的属性。
纳米线104中的每一个纳米线包含设置于纳米线中的沟道区106。沟道区106具有长度(L)。参照图1B,沟道区也具有正交于长度(L)的周边(perimeter)。参照图1A和1B二者,栅电极叠层108围绕沟道区106中的每一个沟道区的整个周边。栅电极叠层108包含栅电极以及设置于沟道区106与栅电极之间的栅电介质层(图1B中示为围绕沟道区106的虚线)。沟道区106是分离的(discrete),因为其由栅电极叠层108完全围绕。即,在栅电极叠层108围绕沟道区106的地方,已经去除了诸如在下基底材料或在上沟道制造材料的任何介入材料。因而,在具有多个纳米线104的实施例中,纳米线的沟道区106相对于彼此也是分离的,如图1B中描绘的。
再次参照图1A,纳米线104中的每一个纳米线也包含设置于纳米线中的在沟道区104的两侧上的源区和漏区110和112。接触部对设置于源/漏区110/112之上。在具体实施例中,接触部对114围绕源/漏区110/112中的每者的整个周边,如图1A中描绘的。即,在实施例中,源/漏区110/112是分离的,因为它们由接触部114完全围绕,而无诸如在下基底材料或在上沟道制造材料的任何介入材料。因而,在具有多个纳米线104的该实施例中,纳米线的源/漏区110/112相对于彼此也是分离的。
再次参照图1A,在实施例中,半导体器件100还包含一对间隔物116。间隔物116设置于栅电极叠层108与该对接触部114之间。如上所述,沟道区和源/漏区在至少七个实施例中被制作为分离的。然而,不是纳米线104的所有区需要是分离的。例如,参照图1C,纳米线104A-104C在在间隔物116之下的位置处不是分离的。在一个实施例中,纳米线104A-104C的叠层具有其间的介入半导体材料118,诸如介入于硅纳米线之间的硅锗,或反之亦然,如以下关于图3A-3F描述的。在一个实施例中,底部纳米线104A仍然与基底102的部分接触,例如与设置于体基底上的绝缘层部分接触。从而,在实施例中,在间隔物中的一个或二者之下的多个竖直层叠的纳米线的部分是非分离的。
虽然上述器件100是针对单个器件,例如NMOS或PMOS器件,但是也可以将CMOS架构形成为包含设置于相同基底上或上方的NMOS和PMOS基于纳米线的器件。例如,图2示例了根据本发明的实施例的基于纳米线的CMOS半导体结构的横截面视图。
参照图2,半导体结构200包含第一半导体器件200A。第一半导体器件200A包含设置于基底202上方的第一纳米线(例如,纳米线叠层204的最底部纳米线204A)。第一纳米线204A在基底202上方第一距离(d1)处具有中点(M1)。能够将第一栅电极叠层(未示出)形成为完全围绕第一纳米线204A。即,一旦包含了栅叠层,第一纳米线204A就具有分离的沟道区和在分离的沟道区的两侧上的源区和漏区。
半导体结构200还包含第二半导体器件200B。第二半导体器件200B包含设置于基底202上方的第二纳米线(例如,纳米线叠层205的最底部纳米线205A)。第二纳米线205A在基底202上方第二距离(d2)处具有中点(M2)。能够将第二栅电极叠层(未示出)形成为完全围绕第二纳米线205A。即,一旦包含了第二栅叠层,第二纳米线205A就具有分离的沟道区和在分离的沟道区的两侧上的源区和漏区。
再次参照图2,第一距离(d1)不同于第二距离(d2)。即,器件200A和200B的中点M1和M2未对齐。替代地,在实施例中,中点是交错的,并且当形成了多个线(例如204和205)的叠层时,用于每一个器件200A和200B的线相对于彼此交错。应当理解,图2中的虚线能够表示公共基底202上的器件200A和200B的相对小或相当大的间隔距离。在实施例中,诸如氧化层的隔离层206将纳米线204和205与基底202隔离,如图2中描绘的。
在实施例中,第一纳米线由诸如但不限于硅、应变硅、硅锗(SixGey,其中0<x<100,且0<y<100)、碳化硅、掺杂碳的硅锗或III-V族化合物的材料构成,并且第二纳米线由不同的诸如但不限于硅、应变硅、硅锗(SixGey,其中0<x<100,且0<y<100)、掺杂碳的硅锗或III-V族化合物的材料构成。在一个该实施例中,第一半导体器件是NMOS器件,且第二半导体器件是PMOS器件。在实施例中,通过考虑对于例如电子或空穴的不同载流子类型的迁移率益处,能够利用列出的材料的任何合适的组合。
在实施例中,第一和第二纳米线设置于体晶体基底上方,该体晶体基底具有设置于其上的介入电介质层。可以通过例如在下鳍状物氧化(UFO)、掩埋氧化物形成(BOX)、或替换电介质来制造介入电介质层。在实施例中,第一和第二纳米线设置于体晶格基底上方,该体晶格基底不具有设置于其上的介入电介质层。在另一实施例中,使用SiGe/Si缓冲层。
在实施例中,第一和第二纳米线中的每一个纳米线的源区和漏区是分离的,第一半导体器件还包含完全围绕第一纳米线的分离的源区和漏区的第一对接触部,且第二半导体器件还包含完全围绕第二纳米线的分离的源区和漏区的第二对接触部。在一个该实施例中,第一对间隔物设置于第一栅电极叠层与第一对接触部之间,并且第二对间隔物设置于第二栅电极叠层与第二对接触部之间。在具体的该实施例中,第一和第二纳米线中的每一个纳米线的部分是非分离的。
在实施例中,第一半导体器件还包含与第一纳米线一起竖直层叠的一个或更多附加纳米线,且第二半导体器件还包含与第二纳米线一起竖直层叠的一个或更多附加纳米线。以下提供了更一般的实施例。
再次参照图1A和2,基底102或202可以由适合于半导体器件制造的材料构成。在一个实施例中,基底102或202包含下体基底,该下体基底由可以包含但不限于硅、锗、硅锗或III-V化合物半导体材料的材料的单晶构成。上绝缘体层设置于下体基底上,该上绝缘体层由可以包含但不限于二氧化硅、氮化硅或氮氧化硅的材料构成。从而,可以从开始绝缘体上半导体基底制造结构100或200。同样,在一个实施例中,多个竖直层叠的纳米线104、204或205设置于体晶体基底上方,该体晶体基底具有设置于其上的介入电介质层,如图1A-1C和2中描绘的。替代地,直接从体基底形成结构100或200,并且局部氧化用于形成电绝缘分代替上述上绝缘体层。同样,在另一实施例中,多个竖直层叠的纳米线104、204或205设置于体晶体基底上方,该体晶体基底不具有设置于其上的介入电介质层。
在实施例中,可以将纳米线104、204或205的尺寸制作为线或带(以下描述后者),并且可以具有方形(squared-off)的或圆形的角。在实施例中,纳米线104、204或205由诸如但不限于硅、锗、或其组合的材料构成。在一个该实施例中,纳米线是单晶。例如,对于硅纳米线,单晶纳米线可以基于(100)全局取向,例如<100>面在z方向上。在实施例中,从图1B中示出的横截面透视图,纳米线104、204或205的尺度在纳米级。例如,在具体实施例中,纳米线的最小尺度小于大致20纳米。根据本发明的实施例,半导体器件100或结构200的该一个或更多纳米线104、204或205包含一个或更多单轴应变纳米线。单轴应变纳米线或多个纳米线可以例如对NMOS或PMOS分别是以张应变或以压应变单轴应变的。
沟道区106中的每一个沟道区的宽度和高度在图1B中示为大致相同,然而,它们是必需的。例如,在另一实施例中(未示出),纳米线104(或204或205)的宽度基本大于高度。在具体实施例中,宽度大致是高度的2-10倍。具有该几何结构的纳米线可以被称为纳米带。在替代实施例中(也未示出),纳米带竖直取向。即,纳米线104(或204或205)中的每一个纳米线具有宽度和高度,宽度基本小于高度。在具体实施例中,高度大致是宽度的2-10倍大。
在实施例中,再次参照图1A,栅电极叠层108的栅电极由金属栅构成并且栅电介质层由高K材料构成。例如,在一个实施例中,栅电介质层由诸如但不限于氧化铪、氮氧化铪、硅酸铪、氧化镧、氧化锆、硅酸锆、氧化钛、钛酸锶钡、钛酸钡、钛酸锶、氧化钇、氧化铝、铅钪钽氧化物、铌酸锌铅、或其组合的材料构成。此外,栅电介质层的部分可以包含从纳米线104的顶部几层形成的原生氧化物(native oxide)层。在实施例中,栅电介质层由顶部高k部分和由半导体材料的氧化物构成的下部分构成。在一个实施例中,栅电介质层由氧化铪的顶部部分和二氧化硅或氮氧化硅的底部部分构成。
在一个实施例中,栅电极由诸如但不限于金属氮化物、金属碳化物、金属硅化物、金属铝化物、铪、锆、钛、钽、铝、钌、钯、铂、钴、镍或导电金属氧化物的金属层构成。在具体实施例中,栅电极由形成于金属功函数设定(workfunction-setting)层上方的非功函数设定填充材料构成。
在实施例中,间隔物116由诸如但不限于二氧化硅、氮氧化硅或氮化硅的绝缘电介质材料构成。在实施例中,接触部114由金属物种制造。金属物种可以是诸如镍或钴的纯金属,或可以是诸如金属-金属合金或金属-半导体合金(诸如硅化物材料)的合金。应当理解,可以使用其它的导电材料来形成接触部114。
在另一方面,提供了制造CMOS纳米线半导体结构的方法。例如,图3A-3F示例了根据本发明的实施例的表示制造CMOS纳米线半导体结构的方法中的各种操作的三维横截面视图。
在实施例中,制造纳米线半导体结构的方法可以包含形成PMOS基于纳米线的半导体器件和相邻的NMOS基于纳米线的半导体器件。可以通过在基底上方形成纳米线来制造每一个器件。在最终提供用于NMOS和PMOS基于纳米线的半导体器件中的每一个器件的两个纳米线的形成的具体实施例中,图3A示例了初始结构300,初始结构300具有基底302(例如,由体基底硅基底302A构成,该体基底硅基底302A上具有绝缘二氧化硅层302B)和设置于基底302上的硅层304/硅锗层306/硅层308/硅锗层310叠层。与图2相关联地提供了对于材料和具体组合的其它可能性。在示范性实施例中,通过在初始绝缘体上硅晶片(为层304的硅部分)上生长硅锗和硅层来提供结构300。
参照图3B,例如利用掩模和等离子刻蚀工艺将硅层304/硅锗层306/硅层308/硅锗层310叠层的部分以及二氧化硅层302B的顶部部分构图为鳍状物类型的结构312。从而,在实施例中,通过构图以提供鳍状物类型的结构312,在硅和硅锗层中的每一层的任一侧上形成了自由表面。应当理解,可以使用任何合适的构图工艺来形成结构312。
在示出三个栅结构的形成的具体范例中,图3C示例了鳍状物类型的结构312,该鳍状物类型的结构312具有设置于其上的三个牺牲栅314A、314B、以及314C。在一个该实施例中,三个牺牲栅314A、314B、以及314C由牺牲栅氧化层316和牺牲多晶硅栅层318构成,牺牲栅氧化层316和牺牲多晶硅栅层318是例如以等离子刻蚀工艺沉积和构图的覆盖层(blanket)。
在构图以形成三个牺牲栅314A、314B、以及314C后,可以在三个牺牲栅314A、314B、以及314C的侧壁上形成间隔物,可以在图3C中示出了鳍状物类型的结构312的区域320中执行掺杂(例如,尖端和/或源和漏类型掺杂),并且可以形成中间层电介质层以覆盖三个牺牲栅314A、314B、以及314C。然后可以对中间层电介质层进行抛光以重新暴露三个牺牲栅314A、314B、以及314C用于替代栅或后栅(gate-last)工艺。参照图3D,连同间隔物322和中间层电介质层324暴露三个牺牲栅314A、314B、以及314C。
然后可以例如在替代栅或后栅工艺流中去除牺牲栅314A、314B、以及314C,以暴露鳍状物类型的结构312的沟道部分。参照图3E的左手部分,在鳍状物类型的结构312用于制造NMOS器件的情况下,去除牺牲栅314A、314B、以及314C以提供沟槽326。去除由沟槽326暴露的硅锗层306和310的部分以及绝缘二氧化硅层302B的暴露的部分,剩下硅层304和308的分离的部分。参照图3E的右手部分,在鳍状物类型的结构312用于制造PMOS器件的情况下,去除牺牲栅314A、314B、以及314C以提供沟槽328。去除由沟槽328暴露的硅锗层304和308的部分,剩下硅锗层306和310的分离的部分。
在实施例中,利用湿法刻蚀选择性地刻蚀硅层304和308,该湿法刻蚀选择性地去除硅304、308,而不刻蚀硅锗纳米线结构306和310。可以利用作为包含例如氢氧化铵和氢氧化钾的水成氢氧化物化学品(chemistry)的该刻蚀化学品来选择性地刻蚀硅。在另一实施例中,利用湿法刻蚀选择性地刻蚀硅锗层306和310,该湿法刻蚀选择性地去除硅锗,而不刻蚀硅纳米线结构304和308。可以利用作为例如柠檬酸/硝酸/HF的羧酸/硝酸/HF化学品的刻蚀化学品来选择性地刻蚀硅锗。从而,可以从鳍状物类型的结构312去除任一硅层以形成硅锗纳米线,或可以从鳍状物类型的结构312去除硅锗层以形成硅沟道纳米线。
在一个实施例中,图3E中示出的硅层304和308(NMOS)或硅锗层(PMOS)的分离的部分将最终变为基于纳米线的结构中的沟道区。从而,在图3E中描绘的工艺阶段,可以执行沟道操纵或调整。例如,在一个实施例中,使用氧化和刻蚀工艺来对图3E的左手部分中示出的硅层304和308的分离的部分或在图3E的右手部分中示出的硅锗层306和310的分离的部分进行减薄。可以在通过刻蚀相对的硅或硅锗层而将线分开的同时执行该刻蚀工艺。因而,从硅层304和308或从硅锗层306和310形成的初始线开始较厚并且被减薄至适合用于纳米线器件中的沟道区的尺寸,而与器件的源区和漏区的尺寸制作不相关。
在如图3E中描绘地形成分离的沟道区之后,可以执行高k栅电介质和金属栅处理,并且可以增加源和漏接触部。在示出两个硅纳米线(NMOS)之上或两个硅锗纳米线(PMOS)之上的三个栅结构的形成的具体范例中,图3F示例了在沉积NMOS栅叠层330或PMOS栅叠层332之后的结构。栅叠层可以由高k栅电介质层和分别N型或P型金属栅电极层构成。附加地,图3F描绘形成永久栅叠层之后,随后去除中间层电介质层324的结构。可以在图3E中剩余的中间层电介质层324部分处形成接触部。在实施例中,在去除324并形成接触部334的工艺期间的一些阶段,可以执行源和漏操纵。
从而,以或许更一般的术语,在实施例中,制造纳米线半导体结构的方法包含在基底上方形成第一有源层。第一有源层具有第一晶格常数。然后在第一有源层上形成第二有源层。第二有源层具有比第一晶格常数大的第二晶格常数。在一个该实施例中,第一有源层由硅构成,并且第二有源层由硅锗(SixGey,其中0<x<100,且0<y<100)构成。有源层的数量这里能够停止,例如对于具有单线PMOS器件和单线NMOS器件的CMOS结构。替代地,如以上示范的,可以重复附加的第一和第二有源层以最终提供多线器件。
在实施例中,第一有源层形成于体晶体基底上方,该体晶体基底具有设置于其上的介入电介质层。第一有源层形成于介入电介质层上。在一个该实施例中,第一有源层由硅构成。方法然后包含由第一有源层形成第一纳米线。第一纳米线包含分离的沟道区和在分离的沟道区的两侧上的源区和漏区。由第二有源层形成第二纳米线。第二纳米线包含分离的沟道区和在分离的沟道区的两侧上的源区和漏区。在实施例中,由第一有源层形成第一纳米线包含选择性地去除第二有源层的部分。同时,由第二有源层形成第二纳米线包含选择性地去除第一有源层的部分。
方法然后包括形成第一栅电极叠层以完全围绕第一纳米线的分离的沟道区。将第二栅电极叠层形成为完全围绕第二纳米线的分离的沟道区。然后可以执行诸如接触部形成和后端互连形成的随后的处理操作。
在替代实施例中,在体晶片上而不是绝缘体上硅晶片上制造与以上描述的纳米线结构类似的结构。例如,图4示例了根据本发明的实施例的另一CMOS基于纳米线的半导体结构的三维横截面视图。
参照图4,将诸如体硅基底的体基底412部分构图为鳍状物402并且用于提供用于硅锗层404和408(PMOS)的模板(template)或连同硅层406和410(NMOS)一起包括。基底412,在基底412上,使用掺杂(例如,使得底部线为欧米伽-FET)或后在下鳍状物氧化工艺后进行鳍状物构图来将鳍状物402与线隔离。在第一有源层与体基底的缓冲层之间没有设置介入全局电介质层。在具体实施例中,制造硅纳米线和硅锗纳米线,例如以图4中描绘的交错方式。
在第二方面,与以上描述的实施例相反,由相同的半导体层形成CMOS结构的对应的NMOS和PMOS纳米线。例如,图5A和5B示例了根据本发明的另一实施例的表示在制造另一COMS纳米线半导体结构的方法中的各种操作的横截面视图。应当理解,开始结构和相关的处理参数可以与与图3A-3F相关联地描述的那些处理参数相类似或相同。
参照图5A,半导体结构500包含第一半导体区500A。第一半导体区500A包含设置于基底502上方的第一纳米线(例如,纳米线叠层504的底部纳米线504A)。第一纳米线504A在基底502上方的第一距离(d1)处具有中点(M1)。半导体结构500还包含第二半导体区500B。第二半导体区500B包含设置于基底502上方的第二纳米线(例如,纳米线叠层505的底部纳米线505A)。第二纳米线505A在基底502上方的第二距离(d2)处具有中点(M2)。
再次参照图5A,第一距离(d1)与第二距离(d2)相同。即,区500A和500B的中点M1和M2对齐。同样,在实施例中,当形成多个线(例如504和505)的叠层时,每一个区500A和500B的线相对于彼此对齐,例如因为每一个对应的线由相同的半导体层形成。应当理解,图5A中的虚线能够表示公共基底502上的区500A和500B的相对小或相当大的间隔距离。在实施例中,诸如氧化层的隔离层506将纳米线504和505与基底502隔离,如图5A中描绘的。
图5A的结构可以被视为主干结构。如以下与图5B相关联地描述的,通过围绕主干结构的部分生长外延包覆层,主干结构可以用于对沟道材料进行调整。增加包覆外延层可以提供迁移率益处。在去除牺牲层以形成图5A的结构之后,在NMOS或PMOS上或在二者上生长外延包覆层。为了展宽线之间的间隙并给包覆外延栅电介质和栅金属保留足够的空间,可以通过湿法刻蚀、干法刻蚀、氧化、或氢退火来对主干线进行减薄,如以下与图6相关联地描述的。
从而,参照图5B,半导体结构500’包含第一半导体器件500A’。第一半导体器件500A’包含设置于基底502上方的第一纳米线(例如,纳米线叠层504’的底部纳米线504A’)。第一纳米线504A’具有由半导体主干材料520构成的分离的沟道区。半导体结构500’还包含第二半导体器件500B’。第二半导体器件500B’包含设置于基底502上方的第二纳米线(例如,纳米线叠层505’的底部纳米线505A’)。第二纳米线505A’具有由半导体主干材料520构成的分离的沟道区。。
然而,第一纳米线504A’的分离的沟道区还包含不包含在第二半导体器件500B’的分离的沟道区中的包覆材料层530。能够将第一栅电极叠层(未示出)形成为完全围绕第一纳米线504A’,包含围绕包覆层520。即,一旦包含了栅叠层,则第一纳米线504A’就具有分离的沟道区和在分离的沟道区的两侧上的源区和漏区。能够将第二栅电极叠层(未示出)形成为完全围绕第二纳米线505A’。即,一旦包含了第二栅叠层,则第二纳米线505A’就具有分离的沟道区和在分离的沟道区的两侧上的源区和漏区。同样,图5B的结构可以用于CMOS器件制造。在一个实施例中,第一纳米线用于NMOS器件制造,而第二纳米线用于PMOS器件制造。在另一实施例中,第一纳米线用于PMOS器件制造,而第二纳米线用于NMOS器件制造。
在实施例中(未示出),第二纳米线还包含不同于第一纳米线的包覆材料层的围绕包覆材料层。在一个该实施例中,第一纳米线用于NMOS器件制造,而第二纳米线用于PMOS器件制造。在另一该实施例中,第一纳米线用于PMOS器件制造,而第二纳米线用于NMOS器件制造。在实施例中,第二纳米线不包含围绕包覆材料层,如图5B中描绘的。在一个该实施例中,第一纳米线用于NMOS器件制造,而第二纳米线用于PMOS器件制造。在另一该实施例中,第一纳米线用于PMOS器件制造,而第二纳米线用于NMOS器件制造。从而,可以利用公共主干,但是不同的整体半导体组分来制造器件。
在实施例中,由相同的层来形成第一和第二纳米线的半导体主干材料,例如层未彼此交错,如图5A和5B中描绘的。在实施例中,第一纳米线的半导体主干材料比第一纳米线的半导体主干材料具有小的直径,例如,在包覆层形成之前对第一纳米线进行减薄。在该实施例中,可以对齐对应的NMOS/PMOS纳米线的中点,但是线具有彼此不同的直径。
在实施例中,半导体主干材料是诸如但不限于硅、应变硅、硅锗(SixGey,其中0<x<100,且0<y<100)、碳化硅、掺杂碳的硅锗或III-V族化合物之一。在该实施例中,包覆材料层由不同的诸如但不限于硅、应变硅、硅锗(SixGey,其中0<x<100,且0<y<100)、碳化硅、掺杂碳的硅锗或III-V族化合物的材料构成。
虽然以上在一些实施例中描述了替代栅工艺,但是在另一实施例中,形成了其中形成的第一栅结构是永久栅结构的器件。还有,虽然以上对于一些实施例描述了每一线单个包覆层,但是可以对单个纳米线使用一个以上的包覆层,例如,作为包覆层叠层。
各种途径可以用于在器件制造期间在一个或更多纳米线上提供包覆材料层。例如,图6示例了根据本发明的实施例的,示例在CMOS纳米线结构的制造中在纳米线上形成包覆层的数个途径的横截面视图。
参照图6的工艺A,在在多个纳米线上形成包覆层之前的主干形状和尺寸操纵包含在第一操作中以设置于基底600A上方的多个分离的纳米线602A开始。在第二操作中,采用各向同性刻蚀(例如,对纳米线602A的材料是选择性的各向同性湿法或干法刻蚀)来提供纳米线604A,与纳米线602A相比,纳米线604A具有减小的尺度,但是大致相同的形状,例如具有圆形角的正方向或矩形。在第三操作中,例如通过外延生长工艺,将包覆材料层606A(例如,由与纳米线602A的半导体材料不同的半导体材料构成的层)形成为与纳米线604A共形。
参照图6的工艺B,在在多个纳米线上形成包覆层之前的主干形状和尺寸操纵包含在第一操作中以设置于基底600B上方的多个分离的纳米线602B开始。在第二操作中,采用偏好具体刻面取向的刻蚀(例如,对纳米线602B的材料是选择性的并且偏好具体刻面取向的湿法或干法刻蚀)来提供纳米线604B,与纳米线602B相比,纳米线604B具有减小的尺度和不同的形状,例如是棱形形状的。在第三操作中,例如通过外延生长工艺,将包覆材料层606B(例如,由与纳米线602B的半导体材料不同的半导体材料构成的层)形成为与纳米线604B共形。
参照图6的工艺C,在在多个纳米线上形成包覆层之前的主干形状和尺寸操纵包含在第一操作中以设置于基底600C上方的多个分离的纳米线602C开始。在第二操作中,采用利用氧化/氢退火的各向同性刻蚀(例如,对纳米线602C的材料是选择性的各向同性湿法或干法刻蚀后进行氧化/氢退火)来提供纳米线604C,与纳米线602C相比,纳米线604C具有减小的尺度和不同的形状,例如圆形。在第三操作中,例如通过外延生长工艺,将包覆材料层606C(例如,由与纳米线602C的半导体材料不同的半导体材料构成的层)形成为与纳米线604C共形。
从而,参照图6的工艺流A、B和C,可以执行主干形状操纵用于外延生长。可以操纵主干材料的横截面形状和晶体方向以提高外延质量迁移率以及使得能够提高间隙填充。主干形状操纵可以涉及使用诸如各向同性刻蚀、偏好具体刻面取向、或利用氧化/氢退火的各向同性刻蚀的不同方法。
如始终简要地提及的,本发明的一个或更多实施例包含用于对于PMOS基于纳米线的器件的提高的空穴迁移率的压应变和用于对于NMOS基于纳米线的器件的提高的电子迁移率的张应变。在实施例中,由该层形成应变硅和应变硅锗器件,以提高或最大化器件性能。在实施例中,通过一个或更多以上描述的途径在公共基底上或上方制造NMOS和PMOS单轴应变纳米线或纳米带器件。PMOS晶体管可以包含SiGe,而NMOS晶体管可以包含硅,该SiGe具有沿电流流动(current flow)方向的单轴压应变,该硅具有沿电流流动方向的单轴张应变。
图7示例了根据本发明的一个实施的计算器件700。计算器件700容纳板子702。板子702可以包含若干部件,包含但不限于处理器704和至少一个通信芯片706。处理器704物理上和电气上耦合至板子702。在一些实施中,该至少一个通信芯片706也物理上和电气上耦合至板子702。在另一实施中,通信芯片706是处理器704的部分。
取决于其应用,计算器件700可以包含其它部件,该其它部件物理上和电气上可以或可以不耦合至板子702。这些其它部件包含但不限于易失性存储器(例如,DRAM)、非易失性存储器(例如,ROM)、闪速存储器、图形处理器、数字信号处理器、密码术处理器、芯片组、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编码解码器、视频编码解码器、功率放大器、全球定位系统(GPS)器件、罗盘、加速计、陀螺仪、扬声器、照相机、以及大容量储存器件(诸如硬盘驱动器、压缩盘(CD)、数字通用盘(DVD)、等)。
通信芯片706使得能够进行无线通信,以将数据转移至计算器件700和转移来自计算器件700的数据。术语“无线”和其衍生物可以用于描述电路、器件、系统、方法、技术、通信信道等,其可以通过非固态介质经由使用调制的电磁辐射来传送数据。术语不暗示关联的器件不含有任何线,然而在一些实施例中,它们可以不含有任何线。通信芯片706可以实施任何数量的无线标准或协议,包含但不限于Wi-Fi(IEEE 802.11家族)、WiMAX(IEEE 802.16家族)、IEEE 802.20、长期演变(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙、其衍生物,以及叫做3G、4G、5G及以上的任何其它无线协议。计算器件700可以包含多个通信芯片706。例如,第一通信芯片706可以专用于诸如Wi-Fi和蓝牙的较短范围的无线通信,而第二通信芯片706可以专用于诸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO等的较长范围的无线通信。
计算器件700的处理器704包含封装于处理器704内的集成电路管芯。在本发明的一些实施中,处理器的集成电路管芯包含一个或更多器件,诸如根据本发明的实施构建的MOS-FET晶体管。术语“处理器”可以指处理来自寄存器和/或存储器的电子数据以将该电子数据变换为可以储存在寄存器和/或存储器中的其它电子数据的任何器件或器件的任何部分。
通信芯片706还包含封装于通信芯片706内的集成电路。根据本发明的另一实施,通信芯片的集成电路管芯包含一个或更多器件,诸如根据本发明的实施构建的MOS-FET晶体管。
在进一步的实施中,容纳于计算器件700内的另一部件可以含有集成电路管芯,该集成电路管芯包含一个或更多器件,诸如根据本发明的实施构建的MOS-FET晶体管。
在各种实施中,计算器件700可以是膝上型电脑、上网本、笔记本、超级本(ultrabook)、智能电话、平板、个人数字助理(PDA)、超级移动PC、移动电话、桌上型计算机、服务器、打印机、扫描仪、监视器、置顶盒、娱乐控制单元、数字照相机、便携式音乐播放器、或数字视频记录器。在另一实施中,计算器件700可以是处理数据的任何其它电子器件。
从而,公开了CMOS纳米线结构。在实施例中,半导体结构包含第一半导体器件。第一半导体器件包含设置于基底上方的第一纳米线。所述第一纳米线在所述基底上方的第一距离处具有中点,并且所述第一纳米线包含分离的沟道区和在所述分离的沟道区的两侧上的源区和漏区。第一栅电极叠层完全围绕所述第一纳米线的所述分离的沟道区。所述半导体结构还含第二半导体器件。所述第二半导体器件包含设置于所述基底上方的第二纳米线。所述第二纳米线在所述基底上方的第二距离处具有中点,并且所述第二纳米线包括分离的沟道区和在所述分离的沟道区的两侧上的源区和漏区。所述第一距离不同于所述第二距离。第二栅电极叠层完全围绕所述第二纳米线的所述分离的沟道区。在一个该实施例中,所述第一纳米线由诸如但不限于硅、应变硅、硅锗(SixGey,其中0<x<100,且0<y<100)、碳化硅、掺杂碳的硅锗或III-V族化合物的材料构成,并且所述第二纳米线由不同的诸如但不限于硅、应变硅、硅锗(SixGey,其中0<x<100,且0<y<100)、掺杂碳的硅锗或III-V族化合物的材料构成。
Claims (32)
1.一种半导体结构,包括:
第一半导体器件,包括:
设置于基底上方的第一纳米线,所述第一纳米线在所述基底上方的第一距离处具有中点而在所述第一纳米线与所述基底之间没有任何介入纳米线,并且所述第一纳米线包括分离的沟道区和在所述分离的沟道区的两侧上的分离的源区和漏区;
第一栅电极叠层,完全围绕所述第一纳米线的所述分离的沟道区;以及
第一对接触部,完全围绕所述第一纳米线的所述分离的源区和漏区;以及
与所述第一半导体器件横向相邻的第二半导体器件,所述第二半导体器件包括:
第二纳米线,所述第二纳米线设置于所述基底上方而在所述第二纳米线与所述基底之间没有任何介入纳米线,所述第二纳米线在所述基底上方的第二距离处具有中点,并且所述第二纳米线包括分离的沟道区和在所述分离的沟道区的两侧上的分离的源区和漏区,其中,所述第一距离不同于所述第二距离;
第二栅电极叠层,完全围绕所述第二纳米线的所述分离的沟道区;以及
第二对接触部,完全围绕所述第二纳米线的所述分离的源区和漏区。
2.如权利要求1所述的半导体结构,其中,所述第一纳米线本质上包含选自于由硅、应变硅、硅锗(SixGey,其中0<x<100,且0<y<100)、碳化硅、掺杂碳的硅锗和III-V族化合物构成的组中的材料,并且其中,所述第二纳米线本质上包含选自于由硅、应变硅、硅锗(SixGey,其中0<x<100,且0<y<100)、掺杂碳的硅锗和III-V族化合物构成的组中的不同材料。
3.如权利要求2所述的半导体结构,其中,所述第一半导体器件是NMOS器件,并且所述第二半导体器件是PMOS器件。
4.如权利要求1所述的半导体结构,其中,所述第一纳米线和所述第二纳米线设置于体晶体基底上方,所述体晶体基底具有设置于其上的介入电介质层。
5.如权利要求1所述的半导体结构,其中,所述第一纳米线和所述第二纳米线设置于体晶体基底上方,所述体晶体基底不具有设置于其上的介入电介质层。
6.如权利要求1所述的半导体结构,还包括:
第一对间隔物,设置于所述第一栅电极叠层与所述第一对接触部之间;以及
第二对间隔物,设置于所述第二栅电极叠层与所述第二对接触部之间。
7.如权利要求6所述的半导体结构,其中,所述第一纳米线和所述第二纳米线中的每一个纳米线的一部分是非分离的。
8.一种制造半导体结构的方法,所述方法包括:
形成第一半导体器件,所述第一半导体器件包括形成于基底上方的第一纳米线,所述第一纳米线在所述基底上方的第一距离处具有中点而在所述第一纳米线与所述基底之间没有任何介入纳米线,并且所述第一纳米线包括分离的沟道区和在所述分离的沟道区的两侧上的分离的源区和漏区,所述第一半导体器件包括完全围绕所述第一纳米线的所述分离的沟道区的第一栅电极叠层,并且所述第一半导体器件包括完全围绕所述第一纳米线的所述分离的源区和漏区的第一对接触部;以及
形成与所述第一半导体器件横向相邻的第二半导体器件,所述第二半导体器件包括第二纳米线,所述第二纳米线形成于所述基底上方而在所述第二纳米线与所述基底之间没有任何介入纳米线,所述第二纳米线在所述基底上方的第二距离处具有中点,并且所述第二纳米线包括分离的沟道区和在所述分离的沟道区的两侧上的分离的源区和漏区,其中,所述第一距离不同于所述第二距离,所述第二半导体器件包括完全围绕所述第二纳米线的所述分离的沟道区的第二栅电极叠层,并且所述第二半导体器件包括完全围绕所述第二纳米线的所述分离的源区和漏区的第二对接触部。
9.如权利要求8所述的方法,其中,所述第一纳米线本质上包含选自于由硅、应变硅、硅锗(SixGey,其中0<x<100,且0<y<100)、碳化硅、掺杂碳的硅锗和III-V族化合物构成的组中的材料,并且其中,所述第二纳米线本质上包含选自于由硅、应变硅、硅锗(SixGey,其中0<x<100,且0<y<100)、掺杂碳的硅锗和III-V族化合物构成的组中的不同材料。
10.如权利要求8所述的方法,其中,所述第一半导体器件是NMOS器件,并且所述第二半导体器件是PMOS器件。
11.如权利要求8所述的方法,其中,所述第一纳米线和所述第二纳米线形成于体晶体基底上方,所述体晶体基底具有形成于其上的介入电介质层。
12.如权利要求8所述的方法,其中,所述第一纳米线和所述第二纳米线形成于体晶体基底上方,所述体晶体基底不具有形成于其上的介入电介质层。
13.如权利要求8所述的方法,还包括:
在所述第一栅电极叠层与所述第一对接触部之间形成第一对间隔物;以及
在所述第二栅电极叠层与所述第二对接触部之间形成第二对间隔物。
14.如权利要求13所述的方法,其中,所述第一纳米线和所述第二纳米线中的每一个纳米线的一部分是非分离的。
15.一种半导体结构,包括:
第一半导体器件,包括:
设置于基底上方的第一纳米线,所述第一纳米线包括分离的沟道区和在所述分离的沟道区的两侧上的源区和漏区,所述分离的沟道区包括半导体主干材料;以及
第一栅电极叠层,完全围绕所述第一纳米线的所述分离的沟道区;以及
第二半导体器件,包括:
设置于所述基底上方的第二纳米线,所述第二纳米线包括分离的沟道区和在所述分离的沟道区的两侧上的源区和漏区,所述分离的沟道区包括所述半导体主干材料以及未包含于所述第一半导体器件的所述沟道区中的围绕包覆材料层;以及
第二栅电极叠层,完全围绕所述第二纳米线的所述分离的沟道区。
16.如权利要求15所述的半导体结构,其中,所述第一纳米线还包括与所述第二纳米线的所述包覆材料层不同的围绕包覆材料层。
17.如权利要求15所述的半导体结构,其中,所述第一纳米线不包括围绕包覆材料层。
18.如权利要求15所述的半导体结构,其中,所述第一纳米线和所述第二纳米线的所述半导体主干材料由相同的层形成。
19.如权利要求15所述的半导体结构,其中,所述第二纳米线的所述半导体主干材料具有的直径比所述第一纳米线的所述半导体主干材料具有的直径小。
20.如权利要求15所述的半导体结构,其中,所述半导体主干材料选自于由硅、应变硅、硅锗(SixGey,其中0<x<100,且0<y<100)、碳化硅、掺杂碳的硅锗和III-V族化合物构成的组,并且所述包覆材料层本质上包含选自于由硅、应变硅、硅锗(SixGey,其中0<x<100,且0<y<100)、碳化硅、掺杂碳的硅锗和III-V族化合物构成的组中的不同材料。
21.如权利要求15所述的半导体结构,其中,所述第一纳米线和所述第二纳米线设置于体晶体基底上方,所述体晶体基底具有设置于其上的介入电介质层。
22.如权利要求15所述的半导体结构,其中,所述第一纳米线和所述第二纳米线设置于体晶体基底上方,所述体晶体基底不具有设置于其上的介入电介质层。
23.如权利要求15所述的半导体结构,其中,所述第一纳米线和所述第二纳米线中的每一个纳米线的所述源区和所述漏区是分离的,所述第一半导体器件还包括完全围绕所述第一纳米线的分离的所述源区和所述漏区的第一对接触部,并且所述第二半导体器件还包括完全围绕所述第二纳米线的分离的所述源区和所述漏区的第二对接触部。
24.如权利要求23所述的半导体结构,还包括:
第一对间隔物,设置于所述第一栅电极叠层与所述第一对接触部之间;以及
第二对间隔物,设置于所述第二栅电极叠层与所述第二对接触部之间。
25.如权利要求24所述的半导体结构,其中,所述第一纳米线和所述第二纳米线中的每一个纳米线的一部分是非分离的。
26.如权利要求15所述的半导体结构,其中,所述第一半导体器件还包括与所述第一纳米线竖直层叠的一个或更多附加纳米线,并且所述第二半导体器件还包括与所述第二纳米线竖直层叠的一个或更多附加纳米线。
27.一种制造CMOS纳米线半导体结构的方法,所述方法包括:
于基底上方形成第一有源层,所述第一有源层具有第一晶格常数;
在所述第一有源层上形成第二有源层,所述第二有源层具有大于所述第一晶格常数的第二晶格常数;
由所述第一有源层形成第一纳米线,所述第一纳米线包括分离的沟道区和在所述分离的沟道区的两侧上的源区和漏区;
由所述第二有源层形成第二纳米线,所述第二纳米线包括分离的沟道区和在所述分离的沟道区的两侧上的源区和漏区;
形成第一栅电极叠层,所述第一栅电极叠层完全围绕所述第一纳米线的所述分离的沟道区;以及
形成第二栅电极叠层,所述第二栅电极叠层完全围绕所述第二纳米线的所述分离的沟道区。
28.如权利要求27所述的方法,其中,由所述第一有源层形成所述第一纳米线包括选择性地去除所述第二有源层的一部分,并且由所述第二有源层形成所述第二纳米线包括选择性地去除所述第一有源层的一部分。
29.如权利要求27所述的方法,其中,所述第一有源层本质上包含硅,并且所述第二有源层本质上包含硅锗(SixGey,其中0<x<100,且0<y<100)。
30.如权利要求29所述的方法,其中,所述第一栅电极叠层是NMOS栅电极叠层,并且其中所述第二栅电极叠层是PMOS栅电极叠层。
31.如权利要求27所述的方法,其中,所述第一有源层形成于体晶体基底上方,所述体晶体基底具有设置于其上的介入电介质层,所述第一有源层形成于所述介入电介质层上。
32.如权利要求27所述的方法,其中,所述第一有源层由体晶体基底形成。
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DE112011106004B4 (de) | 2017-07-13 |
CN104011849A (zh) | 2014-08-27 |
US10074573B2 (en) | 2018-09-11 |
DE112011106004T5 (de) | 2014-09-04 |
US20160086951A1 (en) | 2016-03-24 |
WO2013095646A1 (en) | 2013-06-27 |
TW201342580A (zh) | 2013-10-16 |
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