CN105990413B - 具有纳米线结构的半导体结构与制造方法 - Google Patents

具有纳米线结构的半导体结构与制造方法 Download PDF

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CN105990413B
CN105990413B CN201510063099.4A CN201510063099A CN105990413B CN 105990413 B CN105990413 B CN 105990413B CN 201510063099 A CN201510063099 A CN 201510063099A CN 105990413 B CN105990413 B CN 105990413B
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CN105990413A (zh
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刘恩铨
童宇诚
杨智伟
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United Microelectronics Corp
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Abstract

本发明公开一种具有纳米线结构的半导体结构与制造方法，包含一基底，基底上包含有至少一第一纳米线结构，该第一纳米线结构包含有一栅极区域以及至少一源/漏极区域，其中该第一纳米线结构的该栅极区域的直径与该源/漏极区域的直径不同。

Description

具有纳米线结构的半导体结构与制造方法
技术领域
本发明涉及纳米线结构场效晶体管，尤其是一种在栅极区以及在源/漏极区具有不同直径大小的纳米线结构场效晶体管。
背景技术
具有环绕纳米线结构通道的一栅极导体的纳米线结构场效晶体管(FET)(也称为栅极全环绕(gate-all-around)的纳米线结构FET)的制造包括纳米线结构的悬浮。纳米线结构的悬浮允许栅极导体覆盖纳米线结构的所有表面。
栅极全环绕的纳米线结构FET的制造通常包括以下步骤：
(1)通过图案化绝缘体上覆硅(silicon-on-insulator；SOI)层来界定源极区与漏极区之间的纳米线结构。(2)通过各向同性蚀刻，以底切其上静置有纳米线结构的绝缘体，来悬浮纳米线结构，此蚀刻步骤也底切在源极区及漏极区边缘的绝缘体。(3)共形地包覆、沉积栅极介电层与栅极导体，栅极介电层与栅极导体环绕悬浮的纳米线结构，并且填充于源极区及漏极区的边缘底切处。(4)界定栅极线，其包括蚀刻栅极线，及移除栅极线外部所有区域栅极导体材料，包括移除沉积于源极区及漏极区边缘的栅极材料。
发明内容
本发明提供一半导体结构，包含一基底，基底上包含有至少一第一纳米线结构，该第一纳米线结构包含有一栅极区域以及至少一源/漏极区域，其中该第一纳米线结构的该栅极区域的直径与该源/漏极区域的直径不同。
本发明又提供一种半导体结构的制作方法，至少包含以下步骤：首先，提供一基底，基底上包含一绝缘层以及至少一第一纳米通道结构，且有一第一区域以及一第二区域定义于该基底上，然后形成一掩模层，覆盖该第一区域内的该第一纳米通道结构以及该绝缘层，接着进行一蚀刻步骤，移除该第二区域内的部分该绝缘层，并进行一外延步骤，在该第一纳米通道结构上形成一外延层，其中位于该第一区域的外延层与位于该第二区域的外延层厚度不同，以及进行一热处理步骤，将该第一纳米通道结构与该外延层转换成一第一纳米线结构，其中该第一区域内的该第一纳米线结构的直径与该第二区域内的该第一纳米线结构的直径不同。
本发明提供数种纳米线结构的制作方法，完成的纳米线结构中，同一纳米线结构的栅极区域以及源/漏极区域，分别具有不同的直径大小，或是不同的纳米线结构之间，具有不同的直径大小。由于纳米线结构的直径大小，将会影响后续纳米线结构场效晶体管的阈值电压(Threshold Voltage，Vt)，因此本发明可以增加纳米线结构场效晶体管应用的灵活性。
附图说明
图1为本发明第一优选实施例的纳米线结构的上视图；
图1A为本发明第一优选实施例的纳米线结构的立体图；
图2A～图2B则分别为第一优选实施例中的纳米线结构的栅极区以及源/漏极区域的剖视图；
图3为以本发明多条纳米线结构制作成纳米线结构场效晶体管的示意图；
图4为本发明第二优选实施例的纳米线结构的立体图；
图5A～图5B则分别为第二优选实施例中的纳米线结构的栅极区以及源/漏极区域的剖视图；
图6为本发明第三优选实施例中制作多条纳米线结构的示意图；
图7～图8为图6中沿着剖面线E-E’所得的剖视图。
主要元件符号说明
100 基底
102 绝缘层
104 第一通道结构
104A 栅极区域
104B 源/漏极区域
105 支撑部
106 外延层
108 掩模层
110 第一纳米线结构
114 氧化层
120 材料层
122 栅极介电层
124 栅极层
126 介电材料层
128 接触结构
130 掩模层
204 第二通道结构
204A 栅极区域
204B 源/漏极区域
210 第二纳米线结构
214 氧化层
A 第一区域
B 第二区域
R 凹槽
E1 第一蚀刻步骤
C-C’ 剖面线
D-D’ 剖面线
E-E’ 剖面线
具体实施方式
请参考图1、图1A、图2A与图2B，图1绘示本发明第一优选实施例的纳米线结构的上视图，图1A绘示本发明第一优选实施例的纳米线结构的立体图，图2A～图2B则分别绘示第一优选实施例中的纳米线结构的栅极区以及源/漏极区域的剖视图。图2A左侧为沿着图1A中剖面线C-C’所得的剖视图，图2A右侧为沿着图1A中剖面线D-D’所得的剖视图。
如图1与图1A所示，提供一基底100，基底100可能包括一硅基底，或是一绝缘层上覆硅基底(silicon-on-insulator；SOI)等的半导体基底，本实施例中以硅基底为例，但不限于此。基底100上包含有一绝缘层102以及至少一第一通道结构104，本实施例中，绝缘层102例如为浅沟隔离结构(shallow trench isolation，STI)，优选为氧化硅，而第一通道结构104则与基底100的材质相同，优选为硅，此外在本实施例中，第一通道结构104与基底100相连，例如为一长条状或鳍状结构，但是不限于此，后续将通过一热处理步骤，将上述的第一通道结构转换成一纳米线结构，而栅极、源/漏极等元件也将依序形成，优选横跨在上述的纳米线结构上，上述步骤将在后续段落进行更详细说明。此外，当使用的基底为绝缘层上覆硅基底，第一通道结构104优选位于一绝缘层(图未示)上，而不与基底相连。另外，第一通道结构104两侧可包含有支撑部105，其材质优选与第一通道结构104相同，为简化说明，图1A省略支撑部105而未绘示。
接着，形成一外延层106，覆盖第一通道结构104，其中外延层106可包含硅、硅锗层(Silicon-germanium，SiGe)、硅磷层或硅碳层(SiC)等的单一材料层或复合层，优选为一硅锗层，其可利用一选择性外延制作工艺加以制得，且由于沿特定结晶面的成长速率较快，故从图1A或图2A上来看，外延层106的截面可能为一多角形的结构。
接下来，请仍参考图1、图1A与图2A，本实施例中，基底100上包含有一第一区域A以及一第二区域B，第一区域A内包含有第一通道结构104的一栅极区域104A，而第二区域B内包含有第一通道结构104的至少一源/漏极区域104B，也就是说，第一通道结构104具有栅极区域104A与至少一源/漏极区域104B，分别位于第一区域A与第二区域B内。本实施例中，在第二区域B内覆盖一掩模层108，例如为光致抗蚀剂层等，遮住源/漏极区域104B，并曝露出第一区域A的栅极区域104A，接着进行一蚀刻步骤E1，蚀刻位于第一区域A内，且位于第一通道结构104两旁的绝缘层102，从图2A上来看，未被第一区域A内的外延层106覆盖的绝缘层102会被部分移除，而在第一通道结构104两侧各形成一凹槽R。上述的第一蚀刻步骤E1例如为一干蚀刻及/或湿蚀刻，本实施例中以稀释氢氟酸(DHF)进行湿蚀刻，但不以此为限。随后去除掩模层108，并可选择性进行一清洗制作工艺。
接下来，如图2B所示，对外延层106以及第一通道结构104进行一热处理步骤，上述热处理步骤温度例如为600至1100℃，还可选择性伴随一氧化步骤。热处理步骤以外延层106为硅锗层为例，在经过热处理步骤之后，外延层106以及第一通道结构104会转换为第一纳米线结构110，其中第一纳米线结构110主要由锗组成，以及一氧化层114包覆在第一纳米线结构110外围。其中在热处理步骤进行后，外延层106中的硅原子会和氧原子结合而形成氧化层114，因此锗原子会向中心聚集，另外在第一纳米线结构110的核心部分含锗元素的比例会比外部的氧化层114高，且剖视图上优选具有圆形的截面。
另外值得注意的是，如图2B所示，在热处理步骤进行过程中，部分的第一通道结构104会直接转换成第一纳米线结构110，也就是说第一通道结构104所含的硅会被部分消耗。更详细说明，本实施例中，由于第一区域A内，在第一通道结构104两侧形成有凹槽R，因此第一区域A内的第一通道结构104，比起第二区域B内的第一通道结构104，周围接触气体环境的表面积较大。如此一来，当热处理步骤完成后，第一区域A内的第一纳米线结构110的直径将会比第二区域B内的第一纳米线结构110的直径更大。
上述图1、图1A、图2A～图2B中，虽然仅绘出一条纳米线结构，但是本发明不限于此，在其他实施例中，基底100上可能包含多条第一纳米线结构110，也属于本发明的涵盖范围内。请参考图3，图3绘示以本发明多条纳米线结构制作成纳米线结构场效晶体管的示意图。在上述热处理步骤之后，以蚀刻方式移除第一纳米线结构110周围的氧化层114，第一纳米线结构110仅由两端的支撑部105将其支撑。在其他实施例中，第一纳米线结构110可由剩余的第一通道结构104所支撑。接着依序形成栅极介电层122与栅极层124，跨越于第一纳米线结构110上，然后全面性覆盖一介电材料层126于基底100以及第一纳米线结构110上，之后进行一平坦化步骤以移除多余的介电材料层126后，在栅极区域104A以及源/漏极区域104B内(请一并参考图1)，形成多个接触结构128，分别连接第一纳米线结构110，并完成纳米线结构场效晶体管。上述相关步骤与现有制作晶体管的步骤类似，在此不多加赘述。另外，下面本发明其他实施例所制作的纳米线结构，后续也可以整合此处所提及的制作工艺。
由于纳米线结构的直径大小，包括核心部分或是氧化层的厚度，会影响纳米线结构场效晶体管的阈值电压(Threshold Voltage，Vt)，因此使用上述方法，可以制作一纳米线结构，用该纳米线结构制成的纳米线结构场效晶体管中，栅极区域以及源/漏极区域中的纳米线结构分别具有不同的直径大小，进而应用到同一纳米线场效晶体管，其栅极区域与源/漏极区域拥有不同的阈值电压。
本发明第二优选实施例的纳米线结构场效晶体管制作方法请参考图4、图5A以及5B。图4绘示本发明第二优选实施例的纳米线结构制作方法的立体图，图5A～图5B则分别绘示第二优选实施例中的纳米线结构的栅极区以及源/漏极区域的剖视图。为简化说明，以下说明主要针对各实施例不同之处进行详述，而不再对相同之处作重复赘述。此外，本发明的各实施例中相同的元件以相同的标号进行标示，以利于各实施例间互相对照。
请参考图4、图5A，本实施例中与第一实施例相同，包含有一基底100、一绝缘层102、一第一通道结构104，上述各元件位置与第一优选实施例中所述相同。本实施例与第一优选实施例不同之处在于，本实施例中，掩模层108覆盖在第一区域A内(可一并参考第一实施例所述的第一区域A与第二区域B)，尤其是覆盖第一通道结构104的栅极区域104A，而曝露出源/漏极区域104B，亦即，掩模层108是先直接覆盖住鳍状结构的中央部位。然后先进行第一蚀刻步骤E1，在第二区域B移除部分的绝缘层102，并于第一通道结构104两侧形成凹槽R。接着去除掩模层108，并可选择性进行一清洗制作工艺。之后，才形成一外延层106于第一通道结构104上，由于第二区域B内的部分绝缘层102被移除，使得第二区域B内有部分外延层106形成于凹槽R内，因此第二区域B内外延层106的厚度将会比第一区域A内所形成的外延层106更厚。
再来，如图5B所示，进行一热处理步骤，将外延层106以及第一通道结构转换成第一纳米线结构110。由于第二区域B内所形成的外延层106较第一区域A内所形成的外延层106厚，因此热处理步骤后，第二区域B的纳米线结构110比起第一区域A内的纳米线结构110，具有较大的直径。
同样地，使用上述方法，可制作一纳米线结构，该纳米线结构制成的纳米线结构场效晶体管中的栅极区域以及源/漏极区域，具有不同的直径大小，进而应用到同一纳米线场效晶体管，不同的区域拥有不同的阈值电压。
另外，本发明第一优选实施例中，是先形成外延层106，然后才形成凹槽R，而第二优选实施例中，是先形成凹槽R然后才形成外延层106，上述顺序都属于本发明的涵盖范围内。
此外，当基底上拥有多个通道结构时，本发明的另一实施例可调整不同的纳米线结构之间，具有不同直径大小，详细如下所述：
图6绘示本发明第三优选实施例中制作多条纳米线结构的示意图。图7～图8则绘示的图6中沿着剖面线E-E’所得的剖视图。如图6所示，基底100上除了第一通道结构104之外，还包含有至少一第二通道结构204，其中第二通道结构204的材料特性大致与第一通道结构104相同，但是其宽度、高度等可与第一通道结构104相同或不同。第一纳米线结构110包含有栅极区域104A与源/漏极区域104B，而第二纳米线结构210也同样包含有一栅极区域204A与至少一源/漏极区域204B，第一通道结构104与第二通道结构204两侧优选有的支撑部105。一外延层106同时覆盖于第一通道结构104、第二通道结构204上，为简化说明，绝缘层在本实施例中被省略而未表示于图上。本实施例中。接下来，例如以一沉积步骤，同时在第一通道结构104与第二通道结构204上的外延层106上形成一材料层120，材料层120可能包含一氧化层或是一外延层。接下来如图6～图7所示，先在第一通道结构104上方覆盖一掩模层130，接着以一蚀刻步骤将第二通道结构204上的材料层120去除，然后移除上述掩模层130，再进行一热处理步骤。
由于在进行热处理步骤之前，第一通道结构104比起第二通道结构204更多了一层材料层120覆盖于其上，因此热处理步骤进行后，如图8所示，第一通道结构104形成的第一纳米线结构110以及氧化层114的直径，将会大于第二通道结构204形成的第二纳米线结构210以及一氧化层214的直径。
本实施例还可以与上述第一优选实施例或是第二优选实施例组合。因此，除了第一纳米线结构110与第二纳米线结构210各自的栅极区域以及源/漏极区域具有不同的半径之外，第一纳米线结构110的栅极区域104A内的直径，会较第二纳米线结构210的栅极区域204A内的直径更大；第一纳米线结构110的源/漏极区域104B内的直径，也会较第二纳米线结构210的源/漏极区域204B内的直径更大。
上述第三优选实施例中，先在第一通道结构104与第二通道结构204上都形成材料层120之后，再以蚀刻步骤，将第二通道结构204上的材料层120移除，但在本发明的另外一实施例中，也可先以掩模层覆盖第二通道结构204，然后以一沉积步骤等方式，单独在第一通道结构104上形成材料层120，也属于本发明的涵盖范围内。
综上所述，本发明提供数种纳米线结构的制作方法，完成的纳米线结构中，同一纳米线结构的栅极区域以及源/漏极区域，分别具有不同的直径大小，或是不同的纳米线结构之间，具有不同的直径大小。由于纳米线结构的直径大小，将会影响后续纳米线结构场效晶体管的阈值电压(Threshold Voltage，Vt)，因此本发明可以增加纳米线结构场效晶体管应用的灵活性。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (9)

1.一种半导体结构的制作方法，至少包含以下步骤：
提供一基底，基底上包含绝缘层以及至少一第一纳米通道结构，且有一第一区域以及一第二区域定义于该基底上；
形成一掩模层，覆盖该第一区域内的该第一纳米通道结构以及该绝缘层；
进行一蚀刻步骤，移除该第二区域内的部分该绝缘层；
进行一外延步骤，在该第一纳米通道结构上形成一外延层，其中位于该第一区域的外延层与位于该第二区域的外延层厚度不同；以及
进行一热处理步骤，将该第一纳米通道结构与该外延层转换成一第一纳米线结构，其中该第一区域内的该第一纳米线结构的直径与该第二区域内的该第一纳米线结构的直径不同。
2.如权利要求1所述的制作方法，其中该第一纳米线结构的一栅极区域位于该第一区域内，该第一纳米线结构的一源/漏极区域位于该第二区域内。
3.如权利要求1所述的制作方法，其中该第一纳米线结构的一栅极区域包含该第二区域，该第一纳米线结构的一源/漏极区域包含该第一区域。
4.如权利要求1所述的制作方法，其中该外延层包含一硅锗层。
5.如权利要求1所述的制作方法，其中还包含形成一第二纳米线结构于该基底上，该第二纳米线结构包含有一栅极区域以及至少一源/漏极区域。
6.如权利要求5所述的制作方法，其中该第二纳米线结构的该栅极区域的直径与该第一纳米线结构的该栅极区域的直径不同。
7.如权利要求5所述的制作方法，其中该第二纳米线结构的该源/漏极区域的直径与该第一纳米线结构的该源/漏极区域的直径不同。
8.如权利要求5所述的制作方法，其中形成该第二纳米线结构的方法包含：
形成一第二纳米通道结构于该基底上；
形成一氧化层，覆盖于该第一纳米通道结构上，而不覆盖该第二纳米通道结构；以及
进行一热处理步骤，将该第二纳米通道结构转换成该第二纳米线结构。
9.如权利要求1所述的制作方法，其中该蚀刻步骤在该外延步骤之后进行。
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