TWI656088B - 半導體元件的形成方法 - Google Patents

半導體元件的形成方法 Download PDF

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TWI656088B
TWI656088B TW104126915A TW104126915A TWI656088B TW I656088 B TWI656088 B TW I656088B TW 104126915 A TW104126915 A TW 104126915A TW 104126915 A TW104126915 A TW 104126915A TW I656088 B TWI656088 B TW I656088B
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forming
nanowire structure
semiconductor device
layer
nanowire
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TW201708096A (zh
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楊柏宇
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聯華電子股份有限公司
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Abstract

一種半導體元件的形成方法，該方法包含以下步驟。首先，在一基底上形成一第一奈米線結構及一第二奈米線結構。接著，在該第一奈米線結構上形成一壓縮應力層，並且，進行一第一趨入製程，將該第一奈米線結構趨入為一壓縮奈米線結構。然後，在該第二奈米線結構上形成一伸張應力層，且進行一第二趨入製程，將該第二奈米線結構趨入為一伸張奈米線結構。

Description

半導體元件的形成方法
本發明係關於一種半導體元件的製程，特別是一種具有奈米線(nanowire)結構之半導體元件的製程。
當半導體元件發展至65奈米技術世代後，使用傳統平面式(planar)的金氧半導體(metal-oxide-semiconductor,MOS)電晶體製程難以持續微縮，因此，習用技術提出以非平面(non-planar)多閘極電晶體元件取代平面電晶體元件的解決途徑。舉例來說，雙閘極(dual-gate)鰭式場效電晶體(fin field effect transistor,FinFET)元件、三閘極(tri-gate)鰭式場效電晶體元件、以及Ω式(omega)鰭式場效電晶體元件等都已被提出。現在，則更發展出利用奈米線(nanowire)結構作為通道的全閘極(gate-all-around,GAA)電晶體元件，作為繼續提昇元件積集度與元件效能的方案。
本發明提供一種半導體元件的製程，其形成有奈米線結構，而能達到較佳的元件效能。
為達上述目的，本發明之一實施例提供一種半導體元件的形成方法，包含以下步驟。首先，在一基底上形成一第一奈米線結構及一第二奈米線結構。接著，在該第一奈米線結構上形成一壓縮應力層，並且，進行一第一趨入製程，將該第一奈米線結構趨入為一壓縮奈米線結構。然後，在該第二奈米線結構上形成一伸張應力層，且進行一第二趨入製程，將該第二奈米線結構趨入為一伸張奈米線結構。
本發明之半導體元件的形成方法，主要是先在由單晶矽構成的奈米線結構表面形成磊晶層，再進行趨入製程。使得該磊晶層與氧反應而轉變為一氧化層，同時使磊晶層發生緻密化效應而將其內的壓縮應力材質(如矽鍺或鍺)或伸張應力材質(如碳化矽、磷化矽或碳磷化矽)往奈米線結構內推擠。因此，源自於的磊晶層的應力材質則會大量累積在奈米線結構內，形成一壓縮奈米線結構或一伸張奈米線結構，以對全閘極電晶體元件的閘極通道區產生所需的應力。
100‧‧‧矽覆絕緣基底
101‧‧‧基底
102‧‧‧絕緣層
103‧‧‧單晶矽層
110‧‧‧軸心體
130‧‧‧遮罩層
131‧‧‧連接部
133‧‧‧延伸部
150‧‧‧奈米線結構
151、155‧‧‧連接墊
153、157‧‧‧奈米線
157a‧‧‧通道區
157b‧‧‧壓縮/伸張奈米線
170‧‧‧閘極結構
171‧‧‧閘極介電層
173‧‧‧閘極
175‧‧‧側壁子
190‧‧‧圖案化遮罩
200‧‧‧磊晶層
A‧‧‧第一主動區域
B‧‧‧第二主動區域
P‧‧‧趨入製程
第1圖至第10圖為本發明一實施例中形成半導體元件的製程示意圖，其中第2圖為第1圖中沿A-A’切線獲得之剖面示意圖，第6圖為第5圖中沿B-B’切線獲得之剖面示意圖。
第11圖為本發明另一實施例中形成半導體元件的製程示意圖。
為使熟習本發明所屬技術領域的一般技藝者能更進一步了解本發明，下文特列舉本發明的數個較佳實施例，並配合所附圖式，詳細說明本發明的構成內容及所欲達成的功效。
請參照第1圖至第10圖，所繪示者為本發明一實施例中形成半導體元件的製程示意圖。首先，提供一基底101，基底101上依序形成有一絕緣層102與一半導體層，其中，該半導體層例如是一單晶矽層103。是以，基底101、絕緣層102與單晶矽層103可共同構成一矽覆絕緣(silicon-on-insulator,SOI)基底100，如第1圖所示。接著，在矽覆絕緣基底100上形成至少一軸心體110。軸心體110的材質可包含氧化矽，或是其他與下方矽覆絕緣基底100(特別是指單晶矽層103)具蝕刻選擇比的材質，如多晶矽(polysilicon)、氧化矽等。具體來說，各軸心體110之間較佳是相互分隔，使任兩相鄰的軸心體110之間大體上具有一間距，如第1圖所示，但不以此為限。
接著，在矽覆絕緣基底100上形成一遮罩層130，以作為後續形成奈米線結構的遮罩。遮罩層130可包含氮化矽或是其他與軸心體110及下方矽覆絕緣基底100(特別是指單晶矽層103)具蝕刻選擇比的材質，其形成方式例如是先在矽覆絕緣基底100上形成一遮罩材料層(未繪示)，覆蓋矽覆絕緣基底100及軸心體110，並進行一微影暨蝕刻製程，部分移除該遮罩材料層，形成部分覆蓋軸心體110的遮罩層130。需特別注意的是，遮罩層130除了包含部分覆蓋各軸心體110的一連接部131之外，還具有一延伸部133，其緊鄰且環繞各軸心體110側壁，如第3圖所示。
然後，移除軸心體110，並利用遮罩層130作為遮罩進行一蝕刻製程。藉此，可移除一部分的單晶矽層103，並在矽覆絕緣基底100的單晶矽層103形成一奈米線結構150，其包含一連接墊151，可作為一源極/汲極結構，以及位在連接墊151之間的至少一奈米線153。具體來說，本實施例是在軸心體110移除之後，分別進行兩階段的蝕刻製程，例如是先操作一非等向性蝕刻製程或是垂直方向蝕刻製程，如乾蝕刻，使矽覆絕緣基底100未被遮罩層130覆蓋之區域內的絕緣層102可被暴露出，如第4圖所示。在一實施例中，在進行該非等向性蝕刻製程或是垂直方向蝕刻製程時，較佳可調整蝕刻製程的參數，以形成底切，並隨即移除遮罩層130。而後，繼續進行一等向性蝕刻製程或是側向蝕刻製程，如濕蝕刻，以進一步等向蝕刻奈米線結構150的側壁。然而，本發明的蝕刻製程並不限於前述步驟，在另一實施例中，也可選擇在遮罩層130的遮蔽下，依序進行兩階段的蝕刻製程，形成連接墊的上表面與奈米線的一上表面齊平的一奈米線結構(未繪示)，最後再移除遮罩層130。
值得注意的是，在進行該蝕刻製程時，奈米線結構150因受到遮罩層130的阻擋，是以，接近遮罩層130的單晶矽層103蝕刻速率相對較慢，遠離遮罩層130的單晶矽層103則蝕刻速率相對較快。另一方面，因奈米線153相對於連接墊151具有較小的尺寸，當奈米線153的兩側同時被等向蝕刻時，遠離遮罩層130的單晶矽層103容易被蝕穿。也就是說，奈米線153緊鄰下方絕緣層102的部分會被移除，僅有緊靠遮罩層130的部分奈米線153可被保留，因而可形成懸跨於連接墊151之間 的奈米線153，如第5圖及第6圖所示。此外，在另一實施例中，也可選擇性再蝕刻部分的絕緣層102，使奈米線153與絕緣層102間之距離更遠，以確保後續形成的閘極結構可完全環繞奈米線153。
後續，形成跨越於奈米線153之上的一閘極結構170。具體來說，閘極結構170的形成方法例如是包含依序在矽覆絕緣基底100及奈米線結構150上形成全面覆蓋的一閘極介電層(未繪示)，例如是氧化矽、氮化矽、氮氧化矽或適用的高介電常數材料等介電材質，以及一閘極層(未繪示)，例如是多晶矽、金屬矽化物或是所需的功函數金屬與金屬等導電材質，再形成一圖案化遮罩層190，並據此圖案化該閘極層及該閘極介電層，形成至少部分環繞奈米線153的閘極173，以及位在閘極173與奈米線153之間的閘極介電層171，如第7圖所示。本實施例較佳是使閘極結構170大體上環繞奈米線153長度的1/5至1/3，但不以此為限。在一實施例中，也可選擇形成環繞整個奈米線153的一閘極結構(未繪示)。
此外，還可進一步形成環繞閘極結構170的一側壁子175，如第8圖所示。側壁子175例如是包含氮化矽、氧化矽等單層或多層結構，而其形成方式則可與普遍應用的閘極製程整合，應為本領域者所熟知，於此不再贅述。
而後，進行一選擇性磊晶成長製程製程，以在奈米線結構150暴露於閘極結構170之外的表面上形成一磊晶層200。在本實施例中，磊晶層200可以是共形地形成在奈米線結構150所暴露的所有表面上， 如第9圖所示。其中，磊晶層200可因應後續形成之金氧半導體電晶體的導電特性而包含不同的材質。舉例來說，若為P型金氧半導體電晶體，磊晶層200可包含能使其通道區具壓縮應力的材質，例如是矽鍺(silicon germanium,SiGe)或鍺等；反之，若為N型半導體電晶體，磊晶層200則可選擇包含能使其通道區具伸張應力的材質，例如是碳化矽(silicon carbide,SiC)、磷化矽或碳磷化矽等，但不以此為限。
隨後，進行一趨入(driving)製程P。具體來說，該趨入製程P可包含一退火製程(annealing process)、快速熱退火製程(rapid thermal annealing process,RTP)或濃縮製程(condensation process)，例如可在約為800℃至1100℃的含氧環境下進行，使磊晶層200可與氧反應而形成一氧化層(未繪示)，同時，在該氧化反應下，磊晶層200內具壓縮應力的材質(如矽鍺或鍺)或具伸張應力的材質(如碳化矽、磷化矽或碳磷化矽)可發生緻密化效應(condensation)而逐漸往其內側的奈米線結構150內聚集。在此情況下，大量的壓縮應力材質或伸張應力材質可累積在奈米線結構150內，使得部分的奈米線結構150的材質由原先的單晶矽轉變為單晶矽化物，進而形成一壓縮奈米線結構或一伸張奈米線結構。具體來說，該壓縮奈米線結構或該伸張奈米線結構包含連接墊155以及奈米線157，其中，奈米線157是由一通道區157a及其兩側的壓縮/伸張奈米線157b所構成，如第10圖所示。後續，則可選擇完全移除該氧化層。
值得特說明的是，在一較佳實施例中，壓縮應力的材質或伸張應力的材質是被均勻地趨入至奈米線結構150內，與部分奈米線結構 150的單晶矽反應，形成均勻分布於通道區157a兩側且含單晶矽化物的壓縮/伸張奈米線157b及連接墊155，藉此可達到有效增加通道區的載子遷移率(carrier mobility)的效果。此外，在一實施例中，在形成磊晶層200時，可同時進行一摻雜製程(未繪示)，在閘極結構170未覆蓋的奈米線結構150上摻雜具合適導電型的離子，以形成合適的源極/汲極摻雜區(未繪示)，但不以此為限。在另一實施例中，也可選擇於該趨入製程P後，再進行該摻雜製程。
由此，即獲得本發明一實施例的半導體元件，其具有環繞奈米線結構通道的一閘極結構，因而可構成一全閘極電晶體元件。此外，本發明半導體元件的製程主要是先在由單晶矽構成的奈米線結構表面形成磊晶層，再進行趨入製程P。使得該磊晶層與氧反應而轉變為一氧化層，同時使磊晶層發生緻密化效應而將其內的壓縮應力材質(如矽鍺或鍺)或伸張應力材質(如碳化矽、磷化矽或碳磷化矽)往部分的奈米線結構內推擠。因此，源自於的磊晶層的應力材質則會大量累積在奈米線結構內，形成一壓縮奈米線結構或一伸張奈米線結構，以對該全閘極電晶體元件的閘極通道區產生所需的應力。
此外，本領域者應可輕易了解，本發明的半導體元件亦可能以其他方式形成，並不限於前述的製作步驟。因此，下文將進一步針對本發明半導體元件及其形成方法的其他實施例或變化型進行說明。且為簡化說明，以下說明主要針對各實施例不同之處進行詳述，而不再對相同之處作重覆贅述。此外，本發明之各實施例中相同之元件係以相同之標號進行標示，以利於各實施例間互相對照。
請參照第11圖所示，所繪示者為本發明另一實施例中形成半導體元件之方法的步驟剖面示意圖。本實施例的形成方法大體上和前述實施例的第1圖至第10圖相同，其同樣形成有矽覆絕緣基底100及奈米線結構150。本實施例與前述實施例之主要差異在於，矽覆絕緣基底100可預先定義有彼此電性絕緣的一第一主動區域A以及一第二主動區域B，且矽覆絕緣基底100的第一主動區域A以及第二主動區域B分別形成有如前述實例的第10圖所示的奈米線結構150以及分別橫跨奈米線結構150的閘極結構170。
詳細來說，本實施例是選擇在第一主動區域A與第二主動區域B的矽覆絕緣基底100上分別形成具有不同導電型的全閘極電晶體元件。其中，位在兩主動區域A、B內的全閘極電晶體元件可分別包含一壓縮奈米線結構或一伸張奈米線結構。也就是說，在本實施例中，分別在第一主動區域A與第二主動區域B的矽覆絕緣基底100上形成前述第一實施例的第8圖所示結構之後，可選擇在第一主動區域A與第二主動區域B的奈米線結構150上形成具有不同材質的磊晶層(未繪示)，再同時進行趨入製程P。舉例來說，第一主動區域A的奈米線結構150上形成能使其通道區具壓縮應力的一壓縮應力層(未繪示)，例如是矽鍺層或鍺層；並在第二主動區域B的奈米線結構150上形成能使其通道區具伸張應力的一伸張應力層(未繪示)，例如是碳化矽、磷化矽或碳磷化矽，但不以此為限。在其他實施例中，也可選擇在第一主動區域A與第二主動區域B形成具有相同導電型但包含不同應力材質的兩全閘極電晶體元件(未繪示)。
由此，即獲得本發明另一實施例的半導體元件。然而，本實施例的形成方法並不限於前述製程，熟習該項技藝之人士應知，在本實施例的其他變化型中，也可選擇分別進行第一主動區域A與第二主動區域B的趨入製程。也就是說，在第一主動區域A與第二主動區域B的矽覆絕緣基底100上形成前述第一實施例的第8圖所示結構之後，可再形成一遮罩層(未繪示)，覆蓋位在第二主動區域B的奈米線結構150，選擇僅在第一主動區域A的奈米線結構150上形成如前述第一實施例的第9圖所示的一磊晶層(未繪示)，例如是能使其通道區具壓縮應力的磊晶層(未繪示)，如矽鍺層或鍺層，並且進行第一主動區域A的趨入製程，以在第一主動區域A形成壓縮奈米線結構。而後，移除該遮罩層，並形成另一遮罩層(未繪示)，覆蓋位在第一主動區域A的奈米線結構150。接著在第二主動區域B的奈米線結構150上形成如前述第一實施例的第9圖所示的一磊晶層(未繪示)，例如是能使其通道區具伸張應力的磊晶層(未繪示)，如碳化矽、磷化矽或碳磷化矽，並進行第二主動區域B的趨入製程，以在第二主動區域B形成拉伸奈米線結構。最後再一併移除兩主動區域A、B內的氧化層(該磊晶層在趨入製程P與氧反應後所形成)。
承上所述，本實施例的形成方法可形成包含奈米線電晶體的互補式金氧半導體。此外，本發明半導體元件的製程主要是先在由單晶矽構成的奈米線結構表面形成磊晶層，再進行趨入製程。使得該磊晶層與氧反應而轉變為一氧化層，同時使磊晶層發生緻密化效應而將其內的壓縮應力材質(如矽鍺或鍺)或伸張應力材質(如碳化矽、磷 化矽或碳磷化矽)往部分的奈米線結構內推擠。因此，源自於的磊晶層的應力材質則會大量累積在部分的奈米線結構內，分別在基底的不同主動區域上形成一壓縮奈米線結構及一伸張奈米線結構。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。

Claims (18)

  1. 一種半導體元件的形成方法，包含以下步驟： 在一基底上形成一第一奈米線結構及一第二奈米線結構； 在該第一奈米線結構上形成一壓縮應力層； 進行一第一趨入製程，將該第一奈米線結構趨入為一壓縮奈米線結構； 在該第二奈米線結構上形成一伸張應力層； 進行一第二趨入製程，將該第二奈米線結構趨入為一伸張奈米線結構。
  2. 如申請專利範圍第1項所述之半導體元件的形成方法，其中，該第一趨入製程及該第二趨入製程是透過退火製程、濃縮製程或快速熱退火製程進行。
  3. 如申請專利範圍第1項所述之半導體元件的形成方法，其中，該第一趨入製程及該第二趨入製程是同時進行。
  4. 如申請專利範圍第1項所述之半導體元件的形成方法，其中，該第一趨入製程及該第二趨入製程是分別進行。
  5. 如申請專利範圍第1項所述之半導體元件的形成方法，更包含： 分別形成橫跨該第一奈米線結構及該第二奈米線結構的一閘極結構。
  6. 如申請專利範圍第1項所述之半導體元件的形成方法，其中，該壓縮奈米線結構及該伸張奈米線結構分別包含一通道區以及位在該通道區兩側的壓縮/伸張奈米線。
  7. 如申請專利範圍第5項所述之半導體元件的形成方法，其中，該閘極結構是在該第一趨入製程及該第二趨入製程之前形成。
  8. 如申請專利範圍第5項所述之半導體元件的形成方法，其中，該閘極結構包含一閘極層以及一閘極介電層，該閘極層環繞該第一奈米線結構及該第二奈米線結構，該閘極介電層形成在該閘極層與該第一奈米線結構及該第二奈米線結構之間。
  9. 如申請專利範圍第5項所述之半導體元件的形成方法，更包含： 形成環繞該閘極結構的一側壁子。
  10. 如申請專利範圍第1項所述之半導體元件的形成方法，其中，該壓縮應力層包含矽鍺或鍺。
  11. 如申請專利範圍第1項所述之半導體元件的形成方法，其中，該伸張應力層包含碳化矽、磷化矽或碳磷化矽。
  12. 如申請專利範圍第1項所述之半導體元件的形成方法，其中，該第一奈米線結構與該第二奈米線結構的形成步驟包含： 在基底上形成一遮罩層； 利用該遮罩層進行一第一蝕刻製程；以及 進行一第二蝕刻製程，在該基底上形成該第一奈米線結構及該第二奈米線結構。
  13. 如申請專利範圍第12項所述之半導體元件的形成方法，更包含： 在該第二蝕刻製程之後移除該遮罩層。
  14. 如申請專利範圍第12項所述之半導體元件的形成方法，更包含： 在該第一蝕刻製程之後移除該遮罩層。
  15. 如申請專利範圍第1項所述之半導體元件的形成方法，更包含： 在該第一奈米線結構及該第二奈米線結構上進行一離子佈植製程。
  16. 如申請專利範圍第15項所述之半導體元件的形成方法，其中，該離子佈植製程是在該第一趨入製程及該第二趨入製程之後進行。
  17. 如申請專利範圍第15項所述之半導體元件的形成方法，其中，該離子佈植製程是在形成該壓縮應力層及該伸張應力層時同時進行。
  18. 如申請專利範圍第1項所述之半導體元件的形成方法，其中，該基底包含一矽覆絕緣基底。
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Citations (2)

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US20110133163A1 (en) * 2009-12-04 2011-06-09 International Business Machines Corporation Nanowire fet having induced radial strain
US20140034908A1 (en) * 2012-08-01 2014-02-06 International Business Machines Corporation Epitaxially Thickened Doped or Undoped Core Nanowire FET Structure and Method for Increasing Effective Device Width

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US7902541B2 (en) 2009-04-03 2011-03-08 International Business Machines Corporation Semiconductor nanowire with built-in stress
US8841189B1 (en) 2013-06-14 2014-09-23 International Business Machines Corporation Transistor having all-around source/drain metal contact channel stressor and method to fabricate same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110133163A1 (en) * 2009-12-04 2011-06-09 International Business Machines Corporation Nanowire fet having induced radial strain
US20140034908A1 (en) * 2012-08-01 2014-02-06 International Business Machines Corporation Epitaxially Thickened Doped or Undoped Core Nanowire FET Structure and Method for Increasing Effective Device Width

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