US20160233301A1 - Semiconductor structure with nanowire structures and manufacturing method thereof - Google Patents

Semiconductor structure with nanowire structures and manufacturing method thereof Download PDF

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US20160233301A1
US20160233301A1 US14/663,464 US201514663464A US2016233301A1 US 20160233301 A1 US20160233301 A1 US 20160233301A1 US 201514663464 A US201514663464 A US 201514663464A US 2016233301 A1 US2016233301 A1 US 2016233301A1
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region
nanowire
nanowire structure
diameter
substrate
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En-Chiuan Liou
Yu-Cheng Tung
Chih-Wei Yang
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United Microelectronics Corp
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United Microelectronics Corp
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Assigned to UNITED MICROELECTRONICS CORP. reassignment UNITED MICROELECTRONICS CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: YANG, CHIH-WEI, LIOU, EN-CHIUAN, TUNG, YU-CHENG
Publication of US20160233301A1 publication Critical patent/US20160233301A1/en
Priority to US15/356,671 priority Critical patent/US9875937B2/en
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Definitions

  • the present invention relates to a nanowire structure, and in particular, to a nanowire structure which has different diameters within its gate region and within its source/drain (S/D) region.
  • nanowire field effect transistor FET
  • a gate dielectric and a gate conductor surrounding the nanowire channel also known as a gate-all-around nanowire FET
  • the fabrication of a nanowire field effect transistor (FET) with a gate dielectric and a gate conductor surrounding the nanowire channel includes suspension of the nanowires. Suspension of the nanowires allows for the gate conductor to cover all surfaces of the nanowires.
  • the fabrication of a gate-all-around nanowire FET typically includes the following steps: (1) Definition of the nanowires between source and drain regions by patterning a silicon-on-insulator (SOI) layer. (2) Suspension of the nanowires by isotropic etching that undercuts the insulator on which the nanowires are resting. This etching step also undercuts the insulator at the edge of the source and drain region. (3) A blanket and conformal deposition of the gate dielectric and the gate conductor. The gate dielectric and the gate conductor wraps around the suspended nanowires and fills the undercut at the edge of the source and drain regions. (4) Definition of the gate line which includes the etching of the gate line and removal of the gate dielectric and the gate conductor material from all regions outside the gate line, including gate material deposited in the cavities at the edge of the source and drain regions.
  • the present invention provides a semiconductor structure, comprising a substrate, a first nanowire structure disposed on the substrate, and the first nanowire structure includes a gate region and a source/drain region, wherein the diameter of the first nanowire structure within the gate region is different from the diameter of the first nanowire structure within the source/drain region.
  • the present invention further provides a method for forming a semiconductor structure, comprising: first, a substrate is provided, the substrate comprises an insulating layer and at least one first nano channel structure disposed thereon, a first region and a second region are defined on the substrate, next, a hard mask is formed within the first region, to cover the first nano channel structure and the insulating layer, afterwards, an etching process is performed, to remove parts of the insulating layer within the second region, an epitaxial process is performed, to form an epitaxial layer on the first nano channel structure, wherein the thickness of the epitaxial layer within the first region is different from the thickness of the epitaxial layer within the second region, and an anneal process is performed, to transform the first nano channel structure and the epitaxial layer into a first nanowire structure, wherein the diameter of the first nanowire structure within the first region is different from the diameter of the first nanowire structure within the second region.
  • the present invention provides methods for forming the nanowire structure, and the nanowire structure have different diameters within its gate region and within its S/D region, or in another case, to form different nanowire structures with different diameters. Since the diameter of the nanowire structure will influence the threshold voltage (Vt) of a nanowire filed effect transistor (FET) structure, by using the methods mentioned above, a nanowire structure that has different diameters within different regions (within the gate region and within the S/D region) can be formed, so as to increase the flexibility of the nanowire FET applications.
  • Vt threshold voltage
  • FET nanowire filed effect transistor
  • FIG. 1 is a top-view diagram of the nanowire structure.
  • FIG. 1A is a 3D diagram of the nanowire structure of the first preferred embodiment.
  • FIGS. 2A-2B show the cross section diagrams of the gate region and of the S/D region respectively.
  • FIG. 3 is the schematic diagram showing the nanowire FET structure having a plurality of nanowire structures.
  • FIG. 4 is a 3D diagram of the nanowire structure of the second preferred embodiment.
  • FIGS. 5A-5B show the cross section diagrams of the gate region and of the S/D region respectively.
  • FIG. 6 is the schematic diagram showing a plurality of nanowire structures according to the third preferred embodiment of the present invention.
  • FIGS. 7-8 are cross section diagrams along the cross section line E-E′ of FIG. 6 .
  • FIG. 1 is a top-view diagram of the nanowire structure
  • FIG. 1A is a 3D diagram of the nanowire structure
  • FIGS. 2A-2B show the cross section diagrams of the gate region and of the S/D region respectively.
  • FIG. 2A includes two cross section structures, the left side structure is the cross section diagram along the cross section line C-C′ of FIG. 1A , and the right side structure is the cross section diagram along the cross section line D-D′ of FIG. 1A .
  • a substrate 100 may include a semiconductor substrate such as a silicon substrate or a silicon-on-insulator (SOI) substrate.
  • the substrate 100 is a silicon substrate, but is not limited thereto.
  • the substrate 100 comprises an insulating layer 102 and at least one first channel structure 104 .
  • the insulating layer 102 such as a shallow trench isolation (STI), is preferably made of silicon oxide; and the material of the first channel structure 104 is same as the material of the substrate 100 , such as silicon.
  • the first channel structure 104 and the substrate 100 are connected to each other.
  • STI shallow trench isolation
  • the first channel structure 104 such as a stripe-shaped structure or a fin shaped structure, but not limited thereto, and the first channel structure 104 will be transformed into a nanowire structure through an anneal process in the following processes, the gate and the source/drain (S/D) will also be formed and crossing over the nanowire structure.
  • the manufacturing processes will be described more detail in the following paragraphs.
  • the substrate is an SOI substrate
  • the first channel structure 104 is preferably disposed on an insulating layer (not shown), and does not connect to the substrate.
  • at least two supporting structure 105 may be disposed on two ends of the first channel structure 104 , the material of the supporting structure 105 is same as the material of the first channel structure 104 . To simplify the description, the supporting structure 105 is omitted and not shown in FIG. 1A .
  • an epitaxial layer 106 is then formed, to cover the first channel structure 104 , wherein the epitaxial layer 106 may comprise silicon, silicon-germanium (SiGe), silicon phosphorus, silicon carbide or the combination thereof.
  • the epitaxial layer 106 is a silicon-germanium layer, which can be formed through a selective epitaxial process, due to the growth rate of the epitaxial layer being faster when growing along the specific crystal plane, so as shown in FIG. 1A or in FIG. 2A , the epitaxial layer 106 may have a polygonal cross section.
  • the substrate 100 comprises a first region A and a second region B defined thereon, a gate region 104 A of the first channel structure 104 is disposed within the first region A, and at least one S/D region 104 B of the first channel structure 104 is disposed within the second region B.
  • the first channel structure 104 includes the gate region 104 A and at least one S/D region 104 B, disposed within the first region A and within the second region B respectively.
  • a hard mask 108 is formed within the second region B, such as a photoresist layer, to cover the S/D region 104 B, and so as to expose the gate region 104 A within the first region A.
  • An etching process E 1 is then performed, to etch the insulating layer 102 which is disposed within the first region A and disposed on the two sides of the first channel structure 104 .
  • the insulating layer 102 which is not covered by the epitaxial layer 106 will be removed, so as to form two recesses R on two sides of the first channel structure 104 respectively.
  • the first etching process E 1 mentioned above such as a dry-etching process and/or a wet-etching process, in this embodiment, uses the dilute HF (DHF) to carry out the wet-etching process, but not limited thereto. Afterwards, the hard mask 108 is then removed, and a cleaning process can be selectively performed.
  • DHF dilute HF
  • an anneal process is performed on the epitaxial layer 106 and the first channel structure 104 , the temperature of the anneal process is about between 600-1100° C., and it can be carried out within an oxidation process.
  • the epitaxial layer 106 is a silicon germanium layer
  • the epitaxial layer 106 and the first channel structure 104 will be transformed into a first nanowire structure 110 , wherein the first nanowire structure 110 mainly consists of germanium, and an oxide layer 114 covers the outer surface of the first nanowire structure 110 .
  • the silicon atoms of the epitaxial layer 106 will contact the air and combining with the oxygen atoms, so as to form the oxide layer 114 . Therefore the rest of the germanium atoms will gather toward the center of the first nanowire structure 110 .
  • the germanium containing ratio in the center portion of the first nanowire structure 110 is higher than the germanium containing ratio in oxide layer 114 , and the first nanowire structure 110 preferably has a circular cross section when viewed in a cross section view.
  • the first channel structure 104 will be transformed into the first nanowire structure 110 directly. In other words, the silicon atoms in the first channel structure 104 will be partially consumed. More precisely, in this embodiment, within the first region A, two recesses R are disposed on two sides of the first channel structure 104 respectively. Therefore, the first channel structure 104 within the first region A has larger surface area that contacts surrounding atmosphere than the surface area within the second region B (please also refer to FIG. 2A ) . In this way, after the anneal process is performed, the first nanowire structure 110 within the first region A has larger diameter than the first nanowire structure 110 within the second region B.
  • FIG. 3 is the schematic diagram showing the nanowire FET structure having a plurality of nanowire structures.
  • the oxide layer 114 that surrounds the first nanowire structure 110 is removed through an etching process, and the first nanowire structure 110 is therefore supported by the supporting structure 105 that is disposed on two ends of the substrate 100 .
  • the first nanowire structure 110 can be supported by the remaining first channel structure 104 .
  • a gate dielectric layer 122 and the gate layer 124 are formed sequentially, to cross over the first nanowire structure 110 , and a dielectric layer 126 is entirely covered on the substrate 100 and on the first nanowire structure 110 .
  • a planarization process is then performed to remove the extra dielectric layer 126 , and a plurality of contact plugs 128 are formed within the gate region 104 A and within the S/D region 104 B (please also refer to FIG. 1 ), to electrically connect the first nanowire structure 110 , and complete the nanowire FET structure.
  • the manufacturing processes mentioned above are well known to those skilled in the art, and will not be described redundantly. Besides, the following paragraphs will show some nanowire structures according to other embodiments of the present invention, and they can be applied in the process mentioned here too.
  • the diameter of the nanowire structure including the center part of the nanowire structure or the thickness of the oxide layer, will influence the threshold voltage (Vt) of a nanowire FET structure
  • Vt threshold voltage
  • FIG. 4 is a 3D diagram of the nanowire structure
  • FIGS. 5A-5B show the cross section diagrams of the gate region and of the S/D region respectively.
  • FIGS. 5A-5B show the cross section diagrams of the gate region and of the S/D region respectively.
  • the semiconductor structure includes a substrate 100 , an insulating layer 102 and a first channel structure 104 . Those elements are same as the elements in the first preferred embodiment.
  • the difference with the first preferred embodiment is that the hard mask 108 covers within the first region A (please also refer to the first region A and the second region B shown in the first preferred embodiment) in this embodiment, especially covers the gate region 104 A of the first channel structure 104 , and exposes the S/D region 104 B.
  • the hard mask 108 directly covers the center portion of the fin structure, and an etching process E 1 is then performed, so as to remove parts of the insulating layer 102 within the second region B, and to form two recesses R on two sides of the first channel structure 104 . Afterwards, the hard mask 108 is then removed, and a cleaning process can be selectively carried out. Next, an epitaxial layer 106 is then formed on the first channel structure 104 , since the recesses R are already formed within the second region B, so parts of the epitaxial layer 106 are formed in the recess R, and therefore the thickness of the epitaxial layer 106 within the second region B is thicker than the thickness of the epitaxial layer 106 within the first region A.
  • an anneal process is performed, to transform the epitaxial layer 106 and the first channel structure 104 into the first nanowire structure 110 . Since the epitaxial layer 106 within the second region B is thicker than the epitaxial layer 106 within the first region A, after the anneal process is performed, the nanowire structure 110 within the second region B has larger diameter than the nanowire structure 110 within the first region A.
  • a nanowire structure that has different diameters within different regions can be formed.
  • a nanowire FET structure based on the nanowire structure mentioned above will have different Vt values within the gate region and within the S/D region.
  • the epitaxial layer 106 is formed before the recess R is formed, but in the second preferred embodiment, the epitaxial layer 106 is formed after the recess R is formed, and both flows should be within the scope of the present invention.
  • another embodiment of the present invention provides a method for forming different nanowire structures with different diameters, and it will be detail described in the following paragraphs:
  • FIG. 6 is the schematic diagram showing a plurality of nanowire structures according to the third preferred embodiment of the present invention.
  • FIGS. 7-8 are cross section diagrams along the cross section line E-E′ of FIG. 6 .
  • the material properties of the second channel structure 204 are mostly the same as the material properties of the first channel structure 104 , but the width or the height of the second channel structure 204 may be the same as or different from the width or the height of the first channel structure 104 .
  • the first nanowire structure 110 includes the gate region 104 A and the S/D region 104 B
  • the second nanowire structure 210 also includes a gate region 204 A and at least one S/D region 204 B, the supporting structures 105 being disposed on two ends of the first channel structure 104 and the second channel structure 204 .
  • An epitaxial layer 106 covers the first channel structure 104 and on the second channel structure 204 .
  • the insulating layer is omitted in this embodiment, and not shown in figures.
  • a deposition process is performed, so as to form a material layer 120 on the epitaxial layer 106 which is disposed on the first channel structure 104 and on the second channel structure 204 , and the material layer 120 may include an oxide layer or an epitaxial layer.
  • a hard mask 130 is formed to cover the first channel structure 104 , and an etching process is performed, to remove the material layer 120 on the second channel structure 204 , and the hard mask 130 is then removed. Afterwards, an anneal process is performed.
  • the first channel structure 104 further comprises the material layer 120 disposed thereon before the anneal process is performed, after the anneal process, as shown in FIG. 8 , the first channel structure 104 is transformed into the first nanowire structure 110 and the oxide layer 114 , the second channel structure 204 is transformed into the second nanowire structure 210 and the oxide layer 214 , and the diameter of the first nanowire structure 110 is larger than the second nanowire structure 210 .
  • the third preferred embodiment can be combined with the first or the second preferred embodiments mentioned above. Therefore, except for that the first nanowire structure 110 and the second nanowire structure 210 have different diameters, each one nanowire structure have different diameters within the gate region and within the S/D region.
  • the gate region 104 A of the first nanowire structure 110 may have larger diameter than the gate region 204 A of the second nanowire structure 210 ; and the S/D region 104 B of the first nanowire structure 110 may have larger diameter than the S/D region 204 B of the second nanowire structure 210 .
  • the etching process is performed after the material layer 120 is formed on the first channel structure 104 and on the second channel structure 204 , so as to remove the material layer 120 which is disposed on the second channel structure 204 , but in another embodiment of the present invention, a hard mask can be formed to cover the second channel structure 204 , and the material layer 120 is then formed only on the first channel structure 104 through a deposition process, and this should also be within the scope of the present invention.
  • the present invention provides some methods for forming the nanowire structure, and the nanowire structure have different diameters within its gate region and within its S/D region, or in another case, to form different nanowire structures with different diameters. Since the diameter of the nanowire structure will influence the threshold voltage (Vt) of a nanowire FET structure, by using the method mentioned above, a nanowire structure that has different diameters within different regions (within the gate region and within the S/D region) can be formed, so as to increase the flexibility of the nanowire FET applications.
  • Vt threshold voltage

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US7884004B2 (en) * 2009-02-04 2011-02-08 International Business Machines Corporation Maskless process for suspending and thinning nanowires
US8420455B2 (en) 2010-05-12 2013-04-16 International Business Machines Corporation Generation of multiple diameter nanowire field effect transistors
US9224810B2 (en) * 2011-12-23 2015-12-29 Intel Corporation CMOS nanowire structure
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US7838368B2 (en) * 2004-07-16 2010-11-23 Nxp B.V. Nanoscale fet
US20140210013A1 (en) * 2013-01-25 2014-07-31 Sang-Su Kim Semiconductor devices having a nanowire channel structure

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