CN114792682A - 纳米线晶体管及其制作方法 - Google Patents

纳米线晶体管及其制作方法 Download PDF

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CN114792682A
CN114792682A CN202110101854.9A CN202110101854A CN114792682A CN 114792682 A CN114792682 A CN 114792682A CN 202110101854 A CN202110101854 A CN 202110101854A CN 114792682 A CN114792682 A CN 114792682A
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China
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layer
forming
source
nanowire transistor
graphene
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谢柏光
蔡世鸿
洪庆文
林俊贤
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to US17/185,985 priority patent/US11705498B2/en
Publication of CN114792682A publication Critical patent/CN114792682A/zh
Priority to US18/201,769 priority patent/US20230299166A1/en
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Abstract

本发明公开一种纳米线晶体管及其制作方法，其中该制作纳米线晶体管的方法为，首先形成一通道结构于一基底上，其中该通道结构包含多个第一半导体层及多个第二半导体层交错堆叠，然后形成一栅极结构于该通道结构上，再形成一源极/漏极结构于该栅极结构旁，其中源极/漏极结构包含石墨烯。

Description

纳米线晶体管及其制作方法
技术领域
本发明涉及一种制作纳米线晶体管及其制作方法，尤其是涉及一种以石墨烯为源极/漏极结构或接触插塞的纳米线晶体管及其制作方法。
背景技术
近年来，半导体业界不断微缩金属氧化物半导体场效晶体管(metal-oxide-semiconductor field-effect-transistor，MOSFET)的尺寸，以达到高操作速度、高元件密度的目标。然而，元件尺寸并不可能无止尽地微缩下去，在微缩到30纳米以下时，严重的短通道效应(short channel effects)以及栅极介电层厚度所引起的漏电流会增加元件的静态消耗功率，甚至会使元件完全失去功能。由纳米线或纳米管所建构的一维元件因为具有较低的技术风险，而被认为最有机会取代原有的硅科技。其中，纳米线晶体管具有较高的通道载流子迁移率，且量子效应可以更加提升载流子的迁移率，再配合高介电系数介电层的使用，更可以提高栅极的控制能力，因此是一种相当具有前景的晶体管元件。
发明内容
本发明一实施例揭露一种制作纳米线晶体管的方法。首先形成一通道结构于一基底上，其中该通道结构包含多个第一半导体层及多个第二半导体层交错堆叠，然后形成一栅极结构于该通道结构上，再形成一源极/漏极结构于该栅极结构旁，其中源极/漏极结构包含石墨烯。
本发明另一实施例揭露一种纳米线晶体管，其主要包含通道结构设于基底上，栅极结构设于通道结构上并环绕该通道结构以及源极/漏极结构设于该栅极结构两侧，其中源极/漏极结构包含石墨烯。
本发明又一实施例揭露一种纳米线晶体管，其主要包含通道结构设于基底上，栅极结构设于通道结构上并环绕通道结构，源极/漏极结构设于栅极结构两侧，层间介电层环绕栅极结构以及接触插塞设于层间介电层内并电连接源极/漏极结构，其中接触插塞包含石墨烯。
附图说明
图1至图8为本发明一实施例制作纳米线晶体管的方法示意图；
图9为本发明一实施例的纳米线晶体管的结构示意图；
图10为本发明一实施例的纳米线晶体管的结构示意图。
主要元件符号说明
12:基底
14:通道结构
16:第一半导体层
18:第一半导体层
20:第一半导体层
22:第二半导体层
24:第二半导体层
26:第二半导体层
28:栅极结构
30:介电层
32:硬掩模
34:间隙壁
36:间隙壁
40:源极/漏极结构
44:开口
46:开口
48:高介电常数介电层
50:功函数金属层
52:低阻抗金属层
54:栅极结构
56:第一部分
58:第二部分
60:层间介电层
62:接触插塞
64:阻障层
66:金属层
68:第一阻障层
70:硅化金属层
72:石墨烯层
74:第二阻障层
76:金属层
82:NMOS区域
84:PMOS区域
具体实施方式
请参照图1至图8，图1至图8为本发明一实施例制作一纳米线晶体管的方法示意图。如图1所示，首先提供一基底12，例如一硅基底，然后形成一堆叠结构或通道结构14于基底12上。在本实施例中，通道结构14较佳由多个第一半导体层16、18、20与第二半导体层22、24、26交错堆叠而成。其中第一半导体层16、18、20与第二半导体层22、24、26较佳包含不同材料或不同晶格常数，且第一半导体层16、18、20与第二半导体层22、24、26均可选自由硅、锗、掺杂硅、掺杂锗以及锗化硅所构成的群组。需注意的是，本实施例所揭露的堆叠结构虽以三层第一半导体层16、18、20交错三层第二半导体层22、24、26为例，但第一半导体层16、18、20与第二半导体层22、24、26的数量并不局限于此，而可视制作工艺或产品需求任意调整。
如图2所示，接着进行一光刻暨蚀刻制作工艺，例如利用一图案化光致抗蚀剂(图未示)为掩模去除部分通道结构14与部分的基底12，以于基底12上形成凹槽(图未示)。然后于部分基底12上的凹槽中形成一介电层30用来电性隔绝被图案化的通道结构14，并使介电层30上表面切齐最下层的第一半导体层16下表面。在本实施例中，介电层30可由氧化硅所构成，但不局限于此。
随后如图3所示，形成一栅极结构28及硬掩模32横跨通道结构14，并接着形成一间隙壁34于栅极结构28与硬掩模32侧壁。在本实施例中，栅极结构28可由多晶硅所构成，硬掩模32可包含氮化硅，间隙壁34可选自由二氧化硅、氮化硅、氮氧化硅以及氮碳化硅所构成的群组，但不局限于此。另外需注意的是，本实施例的间隙壁34虽为一单层间隙壁，但又可视制作工艺需求为复合式间隙壁。举例来说，间隙壁34又可细部包含一个或一个以上的间隙壁，且复合式的间隙壁之间可选择为相同或不同材料。依据本发明的一实施例，复合式间隙壁可包含例如一由二氧化硅与氮化硅一同构成的双层复合式间隙壁，或是由氧化硅-氮化硅-氧化硅所构成的三层复合式间隙壁，这些均属本发明所涵盖的范围。
请接着参照图4及图5，其中图5为接续图4沿着切线AA'的剖面示意图。如图4及图5所示，进行一光刻暨蚀刻制作工艺或直接以硬掩模32为掩模去除间隙壁34两侧的部分通道结构14以形成凹槽(图未示)。然后去除硬掩模32与部分第一半导体层16、18、20并形成另一间隙壁36于第一半导体层16、18、20旁，且间隙壁36侧壁较佳切齐第二半导体层22、24、26侧壁以及上方的间隙壁34侧壁。在本实施例中，间隙壁34可与间隙壁36包含相同或不同材料，例如可包含二氧化硅与氮化硅，这些均属本发明所涵盖的范围。
接着形成一源极/漏极结构40于间隙壁36两侧的基底12上，其中源极/漏极结构40较佳由石墨烯所构成。在本实施例中，制备源极/漏极结构40的方式可先利用外延成长方式形成由例如碳化硅所构成的外延层于间隙壁36两侧的基底上，然后进行一加热制作工艺，例用约摄氏700～800度的温度热分解(thermally decompose)或转化(sublimate)外延层中的硅原子以形成由石墨烯所构成的源极/漏极结构40。
随后如图6所示，先进行一蚀刻制作工艺去除硬掩模32与栅极结构28以形成开口44，再进行另一选择性蚀刻制作工艺去除第一半导体层16、18、20以形成多个开口46。由于第一半导体层16、18、20与第二半导体层22、24、26由不同材料所构成且两者之间具有一预定的蚀刻选择比，本实施例较佳以蚀刻去除第一半导体层16、18、20时不损害任何第二半导体层22、24、26。
依据本发明的一实施例，第一半导体层16、18、20与栅极结构28又可由相同材料所构成，例如均包含多晶硅而第二半导体层22、24、26则可选自由单晶硅、锗、掺杂硅、掺杂锗以及锗化硅所构成的群组，如此便可利用一道蚀刻制作工艺同时去除硬掩模32与第一半导体层16、18、20，此实施例也属本发明所涵盖的范围。另外以蚀刻制作工艺去除第一半导体层16、18、20之后，可再选择性利用氧化或另一道蚀刻去除部分第二半导体层22、24、26，将原本约略四方体的第二半导体层22、24、26蚀刻成约略圆弧状而构成纳米线通道结构14，此实施例也属本发明所涵盖的范围。
然后如图7所示，依序形成一高介电常数介电层48、一功函数金属层50以及一低阻抗金属层52于开口44及开口46内，再平坦化以形成一栅极结构54。在本实施例中，栅极结构54较佳包含两部分，其中第一部分56设于第二半导体层22、24、26正上方而第二部分58则与第二半导体层22、24、26交错设置。从另一角度来看，高介电常数介电层48与功函数金属层50包覆第二半导体层22、24、26，而低阻抗金属层52填满于开口44及开口46内。
在本实施例中，高介电常数介电层48包含介电常数大于4的介电材料，例如是选自氧化铪(hafnium oxide，HfO2)、硅酸铪氧化合物(hafnium silicon oxide，HfSiO4)、硅酸铪氮氧化合物(hafnium silicon oxynitride，HfSiON)、氧化铝(aluminum oxide，Al2O3)、氧化镧(lanthanum oxide，La2O3)、氧化钽(tantalum oxide，Ta2O5)、氧化钇(yttrium oxide，Y2O3)、氧化锆(zirconium oxide，ZrO2)、钛酸锶(strontium titanate oxide，SrTiO3)、硅酸锆氧化合物(zirconium silicon oxide，ZrSiO4)、锆酸铪(hafnium zirconium oxide，HfZrO4)、锶铋钽氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、锆钛酸铅(leadzirconate titanate,PbZrxTi1-xO3,PZT)、钛酸钡锶(barium strontium titanate,BaxSr1- xTiO3,BST)、或其组合所组成的群组。
功函数金属层50较佳用以调整形成金属栅极的功函数，使其适用于N型晶体管(NMOS)或P型晶体管(PMOS)。若晶体管为N型晶体管，功函数金属层50可选用功函数为3.9电子伏特(eV)～4.3eV的金属材料，如铝化钛(TiAl)、铝化锆(ZrAl)、铝化钨(WAl)、铝化钽(TaAl)、铝化铪(HfAl)或TiAlC(碳化钛铝)等，但不以此为限；若晶体管为P型晶体管，功函数金属层50可选用功函数为4.8eV～5.2eV的金属材料，如氮化钛(TiN)、氮化钽(TaN)或碳化钽(TaC)等，但不以此为限。功函数金属层50与低阻抗金属层52之间可包含另一阻障层(图未示)，其中阻障层的材料可包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等材料。低阻抗金属层52则可选自铜(Cu)、铝(Al)、钨(W)、钛铝合金(TiAl)、钴钨磷化物(cobalttungsten phosphide，CoWP)等低电阻材料或其组合。由于依据金属栅极置换制作工艺将虚置栅极转换为金属栅极是本领域者所熟知技术，在此不另加赘述。之后可去除部分高介电常数介电层48、部分功函数金属层50与部分低阻抗金属层52形成凹槽(图未示)。
接着如图8所示，形成一层间介电层60于源极/漏极结构40上并填满凹槽。在本实施例中，层间介电层60可由任何包含氧化物的绝缘材料所构成，例如一由四乙氧基硅烷(Tetraethyl orthosilicate,TEOS)所构成的氧化层，但不局限于此。然后进行一接触插塞制作工艺形成接触插塞62电连接源极/漏极结构40。在本实施例中，形成接触插塞62的方式可先利用一蚀刻制作工艺完全去除部分层间介电层60形成接触洞(图未示)并暴露出源极/漏极结构40表面，然后依序沉积一阻障层64与一金属层66于接触洞内并填满接触洞，然后利用一平坦化制作工艺，例如以CMP制作工艺去除部分金属层66与部分阻障层64，以于开口中形成接触插塞62，其中接触插塞62上表面较佳与层间介电层60上表面切齐。在本实施例中，阻障层64较佳选自由钛、钽、氮化钛、氮化钽以及氮化钨所构成的群组，金属层66较佳选自由铝、钛、钽、钨、铌、钼以及铜所构成的群组，但不局限于此。至此即完成本发明较佳实施例的一半导体元件的制作。
请再参照图9，图9揭露本发明一实施例的纳米线晶体管的结构示意图。如图9所示，相较于前述实施例于形成接触洞后便直接填入阻障层64及金属层66形成接触插塞62，本发明又可于形成接触洞之后先沉积一第一阻障层68于接触洞中，其中第一阻障层68较佳共形地(conformally)形成于源极/漏极结构40表面及接触洞的内侧侧壁。在本实施例中，第一阻障层68较佳选自钛、钴、镍及铂等所构成的群组，且最佳为钛。然后依序进行第一热处理制作工艺与第二热处理制作工艺以形成一硅化金属层70于源极/漏极结构40表面。在本实施例中，第一热处理制作工艺包含一常温退火(soak anneal)制作工艺，其温度较佳介于500℃至600℃，且最佳为550℃，而其处理时间则较佳介于10秒至60秒，且最佳为30秒。第二热处理制作工艺包含一峰值退火(spike anneal)制作工艺，其温度较佳介于600℃至950℃，且最佳为600℃，而其处理较佳时间则较佳介于100毫秒至5秒，且最佳为5秒。
之后可比照前述形成源极/漏极结构40的方式形成一石墨烯层72于硅化金属层70表面，再选择性形成一第二阻障层74以及一金属层76于石墨烯层72上并填满接触洞，其中第二阻障层74较佳包含氮化钛、氮化钽等金属化合物，金属层76则较佳包含钨，但不局限于此。最后进行一平坦化制作工艺，例如以CMP制作工艺部分去除部分第金属层76、部分第二阻障层74、部分石墨烯层72及部分第一阻障层68，甚至可视制作工艺需求接着去除部分层间介电层60，以形成接触插塞62电连接源极/漏极结构40。
请再参照图10，图10揭露本发明一实施例的纳米线晶体管的结构示意图。如图10所示，相较于前述实施例中仅制备单一导电型式的晶体管，本发明又可将图8中利用石墨烯来形成源极/漏极结构40的实施例或图9中利用石墨烯来同时形成源极/漏极结构40及接触插塞62的实施例应用至互补型纳米线晶体管元件的制作。举例来说，可先于基底12上定义出一NMOS区域82及PMOS区域84，然后依据前述图1至图8的制作工艺分别于NMOS区域82与PMOS区域84制作出由石墨烯所构成的源极/漏极结构40以及/或接触插塞62。
值得注意的是，相较于前述实施例中纳米线晶体管的最终通道结构可选自由硅、锗、掺杂硅、掺杂锗以及锗化硅所构成的群组，本实施例制备NMOS区域82与PMOS区域84的功函数金属层之前可先去除NMOS区域82的第一半导体层16、18、20以及PMOS区域84的第二半导体层22、24、26但保留NMOS区域82的第二半导体层22、24、26及PMOS区域84的第一半导体层16、18、20作为各区域的通道结构14。换句话说，NMOS区域82的通道结构14与PMOS区域84的通道结构14较佳包含不同材料，例如NMOS区域82的通道结构14较佳包含硅而PMOS区域84的通道结构14则较佳包含锗化硅。
综上所述，本发明主要将石墨烯整合至纳米线晶体管的源极/漏极结构以及/或接触插塞，利用其具有零能带隙(zero bandgap)的特性来降低源极/漏极结构与接触插塞间的阻值进而提升元件效能。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (16)

1.一种制作纳米线晶体管的方法，其特征在于，包含：
形成通道结构于基底上，其中该通道结构包含多个第一半导体层及多个第二半导体层交错堆叠；
形成栅极结构于该通道结构上；以及
形成源极/漏极结构于该栅极结构旁，其中该源极/漏极结构包含石墨烯。
2.如权利要求1所述的方法，另包含：
形成第一间隙壁于该栅极结构旁；
去除部分该多个第一半导体层；
形成第二间隙壁于该多个第一半导体层旁；
形成该源极/漏极结构于该第二间隙壁及该多个第二半导体层旁；
去除该栅极结构以形成第一凹槽；
去除该多个第一半导体层以形成第二凹槽于该多个第二半导体层间；
形成功函数金属层于该第一凹槽及该第二凹槽内；
形成层间介电层环绕该栅极结构；以及
形成接触插塞于该层间介电层内并电连接该源极/漏极结构。
3.如权利要求2所述的方法，其中该第一间隙壁侧壁切齐该第二间隙壁侧壁。
4.如权利要求2所述的方法，其中该第一间隙壁侧壁切齐该多个第二半导体层侧壁。
5.如权利要求2所述的方法，其中该接触插塞包含石墨烯。
6.如权利要求2所述的方法，另包含：
形成接触洞于该层间介电层内；
形成硅化金属层于该接触洞内；
形成石墨烯层于该硅化金属层上；
形成阻障层于该石墨烯层上；
形成金属层于该阻障层上；以及
平坦化该金属层、该阻障层以及该石墨烯层以形成该接触插塞。
7.一种纳米线晶体管，其特征在于，包含：
通道结构，设于基底上；
栅极结构，设于该通道结构上并环绕该通道结构；以及
源极/漏极结构，设于该栅极结构两侧，其中该源极/漏极结构包含石墨烯。
8.如权利要求7所述的纳米线晶体管，其中该通道结构是选自由硅、锗、掺杂硅、掺杂锗以及锗化硅所构成的群组。
9.如权利要求7所述的纳米线晶体管，另包含间隙壁于该栅极结构旁，其中该间隙壁侧壁切齐该通道结构侧壁。
10.如权利要求7所述的纳米线晶体管，另包含：
层间介电层，环绕该栅极结构；以及
接触插塞，在该层间介电层内并电连接该该源极/漏极结构，其中该接触插塞包含石墨烯。
11.如权利要求7所述的纳米线晶体管，其中该接触插塞另包含：
硅化金属层，设于该源极/漏极结构上；
石墨烯层，设于该硅化金属层上；
阻障层，设于该石墨烯层上；以及
金属层，设于该阻障层上。
12.一种纳米线晶体管，其特征在于，包含：
通道结构，设于基底上；
栅极结构，设于该通道结构上并环绕该通道结构；
源极/漏极结构，设于该栅极结构两侧；
层间介电层，环绕该栅极结构；以及
接触插塞，设于该层间介电层内并电连接该源极/漏极结构，其中该接触插塞包含石墨烯。
13.如权利要求12所述的纳米线晶体管，其中该源极/漏极结构包含外延层。
14.如权利要求12所述的纳米线晶体管，其中该通道结构是选自由硅、锗、掺杂硅、掺杂锗以及锗化硅所构成的群组。
15.如权利要求12所述的纳米线晶体管，另包含间隙壁于该栅极结构旁，其中该间隙壁侧壁切齐该通道结构侧壁。
16.如权利要求12所述的纳米线晶体管，其中该接触插塞另包含：
硅化金属层，设于该源极/漏极结构上；
石墨烯层，设于该硅化金属层上；
阻障层，设于该石墨烯层上；以及
金属层，设于该阻障层上。
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