CN114639731A - 一种制作半导体元件的方法 - Google Patents

一种制作半导体元件的方法 Download PDF

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CN114639731A
CN114639731A CN202011477204.6A CN202011477204A CN114639731A CN 114639731 A CN114639731 A CN 114639731A CN 202011477204 A CN202011477204 A CN 202011477204A CN 114639731 A CN114639731 A CN 114639731A
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semiconductor layer
fin structure
fin
forming
semiconductor
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苏士炜
冯皓哲
许轩台
陈俊宇
黄伟豪
蔡滨祥
简廷安
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to CN202011477204.6A priority Critical patent/CN114639731A/zh
Priority to US17/147,477 priority patent/US11462441B2/en
Publication of CN114639731A publication Critical patent/CN114639731A/zh
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Abstract

本发明公开一种制作半导体元件的方法。首先形成一鳍状结构于基底上，然后形成一介电层环绕该鳍状结构，进行一退火制作工艺将该介电层转换为浅沟隔离，去除鳍状结构以形成一凹槽，形成一堆叠结构于该凹槽内，其中该堆叠结构包含一第一半导体层设于该鳍状结构上以及一第二半导体层设于该第一半导体层上，且第一半导体层与第二半导体层包含不同材料。

Description

一种制作半导体元件的方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种先形成浅沟隔离再形成半导体堆叠结构于鳍状结构顶部的方法。
背景技术
近年来，半导体业界不断微缩(downscale)金属氧化物半导体场效晶体管的尺寸，以达到高操作速度、高元件密度的目标。然而，元件尺寸并不可能无止尽地微缩下去，在微缩到30纳米以下时，严重的短通道效应(short channel effects)以及栅极介电层厚度所引起的漏电流会增加元件的静态消耗功率，甚至会使元件完全失去功能。由纳米线或纳米管所建构的一维元件因为具有较低的技术风险，而被认为最有机会取代原有的硅科技。其中，纳米线晶体管具有较高的通道载流子迁移率，且量子效应可以更加提升载流子的迁移率，再配合高介电系数介电层的使用，更可以提高栅极的控制能力，因此是一种相当具有前景的晶体管元件。
发明内容
本发明揭露一种制作半导体元件的方法。首先形成一鳍状结构于基底上，然后形成一介电层环绕该鳍状结构，进行一退火制作工艺将该介电层转换为浅沟隔离，去除鳍状结构以形成一凹槽，形成一堆叠结构于该凹槽内，其中该堆叠结构包含一第一半导体层设于该鳍状结构上以及一第二半导体层设于该第一半导体层上，且第一半导体层与第二半导体层包含不同材料。
附图说明
图1至图5为本发明一实施例制作半导体元件的制作方法示意图；
图6为本发明一实施例制作纳米线晶体管的立体图。
主要元件符号说明
12:基底
14:鳍状结构
16:衬垫层
18:浅沟隔离
20:凹槽
22:堆叠结构
24:第一半导体层
26:第一半导体层
28:第二半导体层
30:第二半导体层
32:退火制作工艺
34:栅极结构
36:纳米线
具体实施方式
请参照图1至图5，图1至图5为本发明一实施例制作半导体元件的制作方法示意图。如图1所示，首先提供一基底12，例如一硅基底或硅覆绝缘(silicon on insulator,SOI)基板，然后形成至少一鳍状结构14于基底12上，并接着形成一浅沟隔离(shallowtrench isolation,STI)16环绕鳍状结构14。在本实施例中，鳍状结构14虽以两根为例，但其数量并不以此为限，可依据产品需求进行调整，例如可形成一根或一根以上的鳍状结构14于基底12上。
依据本发明的优选实施例，鳍状结构14较佳通过侧壁图案转移(sidewall imagetransfer,SIT)技术制得，其程序大致包括：提供一布局图案至计算机系统，并经过适当地运算以将相对应的图案定义于光掩模中。后续可通过光刻及蚀刻制作工艺，以形成多个等距且等宽的图案化牺牲层于基底上，使其个别外观呈现条状。之后依序施行沉积及蚀刻制作工艺，以于图案化牺牲层的各侧壁形成间隙壁。继以去除图案化牺牲层，并在间隙壁的覆盖下施行蚀刻制作工艺，使得间隙壁所构成的图案被转移至基底内，再伴随鳍状结构切割制作工艺(fin cut)而获得所需的图案化结构，例如条状图案化鳍状结构。
除此之外，鳍状结构14的形成方式又可包含先形成一图案化掩模(图未示)于基底12上，再经过一蚀刻制作工艺，将图案化掩模的图案转移至基底12中以形成鳍状结构14。另外，鳍状结构14的形成方式也可以先制作一图案化硬掩模层(图未示)于基底12上，并利用外延制作工艺于暴露出于图案化硬掩模层的基底12上成长出例如包含硅锗的半导体层，而此半导体层即可作为相对应的鳍状结构14。这些形成鳍状结构14的实施例均属本发明所涵盖的范围。需注意的是，在形成鳍状结构14之后鳍状结构14表面可选择性设有一由氧化硅所构成衬垫层16以及一由氮化硅所构成的衬垫层(图未示)。
然后形成一浅沟隔离(shallow trench isolation,STI)18环绕鳍状结构14。在本实施例中，形成浅沟隔离18的方式可先利用一可流动式化学气相沉积(flowable chemicalvapor deposition,FCVD)制作工艺形成一由氧化硅所构成的介电层于基底12上并完全覆盖鳍状结构14，接着搭配进行一退火制作工艺32，例如利用约摄氏1000度的温度将介电层转换为浅沟隔离18。接着可去除氮化硅所构成的衬垫层暴露出由氧化硅所构成的衬垫层16并使衬垫层16顶表面略低于浅沟隔离18顶表面。
随后如图2所示，可在不形成掩模的情况下进行一蚀刻制作工艺，例如利用三氟化碳(NF3)、氨气(NH3)或氢氟酸(HF)去除鳍状结构14顶部的衬垫层16并同时形成凹槽20暴露出鳍状结构14顶部。需注意的是，由于环绕鳍状结构14周围的浅沟隔离18与衬垫层16均由氧化硅所构成，因此本阶段利用蚀刻完全去除衬垫层16的同时可能同时去除部分周围的浅沟隔离18使其高度略微降低，但仍略高于鳍状结构14顶部。
如图3所示，然后可在使用图案化掩模或不使用图案化掩模的情况下进行另一蚀刻制作工艺，例如利用溴化氢(HBr)去除部分鳍状结构14并同时增加各鳍状结构14顶部凹槽20的深度。
如图4所示，接着可利用例如外延成长制作工艺形成一堆叠结构22于各凹槽20内的鳍状结构14顶部。在本实施例中，堆叠结构22较佳由至少一组不同材料的半导体层例如多个第一半导体层24、26与多个第二半导体层28、30交错堆叠而成。其中接触鳍状结构14的第一半导体层24较佳与鳍状结构14包含不同材料，第一半导体层24、26之间包含相同材料，第二半导体层28、30之间包含相同材料，第一半导体层24、26与第二半导体层28、30较佳包含不同材料或不同晶格常数，且第一半导体层24、26与第二半导体层28、30均可选自由硅、锗、掺杂硅、掺杂锗以及锗化硅所构成的群组。需注意的是，本实施例所揭露的堆叠结构虽以两层第一半导体层24、26交错两层第二半导体层28、30为例，但第一半导体层24、26与第二半导体层28、30的数量并不局限于此，而可视制作工艺或产品需求任意调整。
如图5所示，接着利用化学机械研磨(chemical mechanical polishing,CMP)制作工艺以及/或蚀刻制作工艺去除部分浅沟隔离18，使剩余的浅沟隔离18顶表面略低于鳍状结构14表面或更具体而言略低于堆叠结构22中的第一半导体层24底部。
之后如图6的立体图所示，可依据制作工艺需求进行后续纳米线晶体管的制作，例如可先形成一由多晶硅材料或金属所构成的栅极结构34横跨堆叠结构22与鳍状结构14，然后形成间隙壁(图未示)于栅极结构34旁，形成源极/漏极结构(图未示)于间隙壁两侧的基底12上，再去除单数层或偶数层的半导体层例如去除第一半导体层24、26形成凹槽并使剩余的第二半导体层28、30形成纳米线36。由于依据上述制作工艺制备纳米线晶体管为本领域所熟知技艺，在此不另加赘述。至此即完成本发明一半导体元件的制作。
一般而言，现有纳米线晶体管在制作时通常会先形成一整片由前述半导体材料所构成的堆叠结构于硅基底上，利用光刻暨蚀刻制作工艺同时去除部分堆叠结构与硅基底形成图案化的堆叠结构与鳍状结构，再形成浅沟隔离于鳍状结构周围。然而制备浅沟隔离时所使用的高温退火制作工艺容易使堆叠结构中的锗原子扩散至周围的硅层内影响鳍状结构品质及后续的元件表现。为了解决此问题本发明主要将形成浅沟隔离(特别是形成浅沟隔离18时所使用的高温退火制作工艺32)的时间点(例如前述图1)移到形成堆叠结构22(例如前述图4)之前，如此后续形成堆叠结构于鳍状结构顶部时堆叠结构中由的锗原子便不致因退火制作工艺的高温而扩散至周围由硅所构成的鳍状结构14内影响元件效能。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (12)

1.一种制作半导体元件的方法，其特征在于，包含：
形成鳍状结构于基底上；
形成浅沟隔离环绕该鳍状结构；
去除该鳍状结构以形成凹槽；以及
形成堆叠结构于该凹槽内。
2.如权利要求1所述的方法，另包含：
形成介电层环绕该鳍状结构；以及
进行退火制作工艺将该介电层转换为该浅沟隔离。
3.如权利要求1所述的方法，另包含：
在形成该堆叠结构后去除该浅沟隔离；以及
将该堆叠结构转换为栅极结构。
4.如权利要求3所述的方法，其中该浅沟隔离顶表面低于该堆叠结构顶表面。
5.如权利要求1所述的方法，其中该堆叠结构包含：
第一半导体层，设于该鳍状结构上；以及
第二半导体层，设于该第一半导体层上。
6.如权利要求5所述的方法，其中该第一半导体层以及该第二半导体层包含不同材料。
7.如权利要求5所述的方法，其中该第一半导体层以及该鳍状结构包含不同材料。
8.如权利要求5所述的方法，其中该第一半导体层以及该第二半导体层是选自由硅以及锗化硅所构成的群组。
9.如权利要求5所述的方法，其中该堆叠结构包含：
第三半导体层，设于该第二半导体层上；以及
第四半导体层，设于该第三半导体层上。
10.如权利要求9所述的方法，其中该第三半导体层以及该第四半导体层包含不同材料。
11.如权利要求9所述的方法，其中该第三半导体层以及该第二半导体层包含不同材料。
12.如权利要求9所述的方法，其中该第三半导体层以及该第四半导体层是选自由硅以及锗化硅所构成的群组。
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