CN101295585A - 电容器、包含该电容器的电路板及集成电路承载基板 - Google Patents
电容器、包含该电容器的电路板及集成电路承载基板 Download PDFInfo
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Abstract
本发明公开了一种电容器、包含该电容器的电路板及集成电路承载基板,该电容器是为相关于降低电容器的等效串联电感(ESL)的线路结构。该电容器包括多个电极、一沿着该电容器的厚度方向从顶部电极延伸至底部电极的第一连通孔、及一沿着该电容器的厚度方向从顶部电极延伸至底部电极的第二连通孔。该电极包括一组第一电极及一组第二电极。该第一连通孔电性连接至该第一电极,且,该第二连通孔电性连接至该第二电极。该电容器尚包括一介于该第一连通孔及该第二连通孔之间的额外连通孔。该额外连通孔的长度短于第一连通孔及第二连通孔的长度。此外,该额外连通孔电性连接至第一电极及第二电极其中之一。
Description
技术领域
本发明一般是关于电容器,特别是关于电容器的线路结构。
背景技术
多层印刷电路板(PCB)目前已被广泛使用于集成电路(IC)、芯片等电子电路系统及电子组件的内部电子信号传递与连接。近年来,被大量使用于降低印刷电路板(Printed Circuit Board)或IC载板(substrate)上的电源噪声的方法是在电源接脚(power/ground pin)附近放置去耦合电容(decoupling capacitor)或是旁路电容(bypass capacitor),主要功能是将额定的电能储存在电容器中,在电能不足时可以适时补给电能,以达到吸收突波(glitch)、降低RF噪声及稳定电源的效果。一般而言,印刷电路板中常见的去耦合电容组件可分为黏着于电路板表面的分布式电容(如SMD电容器(Surface Mounted Device Capacitor)或叉指式电容器(Inter-Digitated Capacitor,IDC)等以及内埋于电路板内的内埋式电容(如平板电容)。然而,电源传输系统主要是借着电容器的低阻抗特性,提供一个低阻抗路径将噪声滤除,但是当操作频率高于电容器本身的谐振频率点之后,其阻抗特性由电容性转变为电感性,因此,随着频率上升而增加的寄生电感,将会导致原本提供低阻抗路径的去耦合电容逐渐失去滤除高频噪声的作用。
随着电子系统中信号传输速度不断地提升,线路密度不断地增加,信号之间衍生的相互干扰问题也相对严重且不可忽视。目前普遍解决前述问题的方法是在印刷电路板表面黏着去耦合电容,因其形成的电流传输路径无法缩短而使得寄生电感值太大,进而使得此方法无法有效抑制电源传输系统所产生同步切换干扰。然而,若将去耦合电容内埋至印刷电路板或IC载板中,必定比焊接在表面的表面黏着型式电容更靠近电子组件的电源或接地接脚,因此高频时内埋式去耦合电容的电源传输路径所产生的寄生电感值将会比SMD电容低。此外,内埋电容技术降低电路板焊接的被动组件数量,不但可以降低成本,还可以达到缩小电子组件构装体积的市场需求。
一般在电源传输系统设计时会考虑电源的传输阻抗,也就是目标阻抗(target impedance),其指的是电源在符合低噪声规格的前提下,电源传输系统在特定的频带范围内所能容许的最大等效阻抗值。图1所示为电容值为1μF且黏着于电路板表面的分布式电容器在频率范围从0.01MHz到1000MHz的阻抗特性曲线,其中包括0612及1206电容器及低电感叉指式电容器。参考图1,当操作频率达数百MHz,该叉指式电容器的阻抗仍然可以低于系统需求的目标阻抗(约0.5欧姆)。但是,未来集成电路载板设计需求的目标阻抗将会低于0.1欧姆或更小,换言之,当在高频操作时,表面黏着型式的分布式电容器将无法提供电源传输系统足够低的阻抗以抑制不可预期的噪声产生。简言之,内埋电容技术是未来最有可能被实现以降低电容的基板寄生电感值以及增加去耦合电容的低阻抗频宽的方法,但是内嵌式平板电容和一般电容器一样,当操作频率高于其自振频率点之后,依然会由电容性转变为电感性,进而失去滤除高频噪声的作用。因此,本发明揭露一种降低内嵌式平板电容的线路结构,借着减少平板电容的电流回路长度以降低其寄生电感值,使得电子系统即使操作在高频区段时,内埋式平板电容仍能发挥去耦合电容的功效,提供一个低阻抗路径以滤除电源系统产生的噪声。
Howard等人的美国专利号5,161,086描述了如图2所示在印刷电路板多层薄片电容器的结构剖面图。参照图2,该集成电路14’分别藉由第一金属连通孔34’及第二金属连通孔36’与一电容器的电极28’及30’互相电性连接。而且该第一金属连通孔34’藉由绝缘环穿过电极30’而未与电极30’电性连接。同样地,该第二金属连通孔36’藉由绝缘孔穿过电极28’而未与电极30’电性连接。
Naito等人的美国专利号6,678,145提出可降低电容器的寄生电感值的线路连接结构。图3(a)是电容器41的内部一个电极结构的俯视图。图3(b)显示从图3(a)沿着线III-III的横截面图。参照图3(a),多个第一金属连通孔46及第二金属连通孔47分别连接至该电容器的第一内部电极44及第二内部电极45。参照图3(b),每一个第一金属连通孔46皆与第二金属连通孔47相邻摆置,此结构可以减少电流回路面积,以达到降低寄生电感值的目的。
发明内容
根据本发明的一实例提供一电容器,该电容器包括多个电极,该电极包含一顶部电极及一底部电极,一第一连通孔沿该电容器的厚度方向从顶部电极延伸至底部电极,一第二连通孔沿该电容器的厚度方向从顶部电极延伸至底部电极。该电极包含一组第一电极及一组第二电极。该第一连通孔电性连接至第一电极,此外,该第二连通孔电性连接至第二电极。该电容器尚包括了一额外连通孔,该额外连通孔介于该第一连通孔及该第二连通孔之间。而且,该额外连通孔长度较该第一连通孔及该第二连通孔的长度短。此外,该额外连通孔与该第一电极及该第二电极其中之一电性连接。
根据本发明的另一个实例提供一内埋于电路板内的电容器,该电容器包括:多个电极、一第一连通孔沿该电容器的该厚度方向从该顶部电极延伸至该底部电极、及一第二连通孔沿该电容器的该厚度方向从该顶部电极延伸至该底部电极。该电极包括一组第一电极及一组第二电极。该第一连通孔与该第一电极电性连接且该第二连通孔与该第二电极电性连接。该电容器尚包括一额外连通孔,该额外连通孔介于该第一连通孔及该第二连通孔之间。而且,该额外连通孔长度较该第一连通孔及该第二连通孔的长度短。此外,该额外连通孔与该第一电极及该第二电极其中之一电性连接。该电容器还包括了多个绝缘层,该绝缘层位于该第一电极和该第二金属极板之间。该电容器可被使用于各种印刷电路应用中,例如,可内藏至硬式及/或可挠式电路板、印刷电路板或其它微电子组件(如封装芯片等)之中。
在根据本发明的另一个实例中,一集成电路承载基板,其电性连接至一集成电路组件,包括:一线路板,该线路板包含一电源层及一接地层;一电容器,该电容器电性连接至该电源层及该接地层。该电容器包括:多个电极,其包括了一顶部电极及一底部电极,一第一连通孔沿该电容器的厚度方向从该顶部电极延伸至该底部电极;以及一第二连通孔沿该电容器的厚度方向从该顶部电极延伸至该底部电极。该电极包括一组第一电极及一组第二电极。该第一连通孔与该第一电极电性连接,且该第二连通孔与该第二电极电性连接。该电容器也包括一额外连通孔,该额外连通孔介于该第一连通孔与该第二连通孔之间。该额外连通孔长度较该第一连通孔及该第二连通孔的长度短。此外,该额外连通孔与该第一电极及该第二电极其中之一相互电性连接。该电容器还包括了多个绝缘层,该绝缘层位于该第一电极和该第二金属极板之间。
附图说明
结合附图进行阅读将更好地了解前文所述之本发明的发明内容及以下实施方式。然而应了解,本发明不限于所示的精确配置及手段。
图1所示为现有表面黏着电容器示例性阻抗曲线图;
图2所示为现有多层电路板上的传统电容器;
图3(a)所示为现有传统电容器之内部结构的平面图;
图3(b)所示为图3(a)结构的横截面图标;
图4所示为根据本发明的实例中,一电路板的电容器横截面图示;
图5所示为根据本发明的实例中,一电路板的电容器横截面图示;
图6所示为根据本发明的实例中,一电路板的电容器横截面图示;以及
图7所示为根据本发明的实例中,具有电容器的电路板横截面图示;
【主要组件符号说明】
14’集成电路
28’导电金属层
30’导电金属层
34’第一金属连通孔
36’第二金属连通孔
41电容器
44第一内部电极
45第二内部电极
46第一金属连通孔
47第二金属连通孔
400电容器
410第一电极
420第二电极
430绝缘层
430a绝缘层
430b绝缘层
430c绝缘层
440第一连通孔
450第二连通孔
460额外连通孔
460a额外连通孔
460b额外连通孔
500电容器
600电容器
700电子电路系统
710集成电路
720电路板
730电容器
732a第一电极
732b第二电极
734a第一连通孔
734b第二连通孔
736额外连通孔
738绝缘层
740线路层
750a电源层
750b接地层
760锡铅凸块
770焊垫
具体实施方式
本发明提供在电路板中一电容器的线路结构,该电路板的一额外连通孔配置于第二连通孔及第一连通孔之间。该额外连通孔的长度较该第二连通孔或该第一连通孔的长度短。特别在高频时,在电容组件中藉由该额外连通孔缩短该第二连通孔与该第一连通孔所形成的电流回路面积,因此可以减少寄生电感效应(即电容器之ESL)。
图4是根据本发明实例中具有一线路连接结构的电容器横截面图示。参照图4,一电容器400可包括至少一第一电极410及至少一第二电极420,其中该第一电极410与该第二电极420的极性相反。各对第一电极410及第二电极420间具有一绝缘层430,以在电容器400中形成一电容性组件。图4的实例中提供该二对第一电极410及第二电极420,其包含最靠近电容器400顶层表面之顶部电极420-1以及最靠近电容器400底层表面之底部电极410-1。在另一实施例中,电容器亦可包含多对第一电极及第二电极,其配置方式可相似于图4所示之第一电极410及第二电极420。该第一电极410及第二电极420的材料可为任何具有导电性物质所形成。在一实例中,第一电极410及第二420由铜制成。该绝缘层430的材料为不具导电性或低导电性的介电材料所形成,如一实例中的陶瓷介电材料。
在电容器400中,至少一第一连通孔440及至少一第二连通孔450朝着绝缘层430的厚度方向延伸并穿过一特定的绝缘层430。至少有一该第一连通孔440及至少有一该第二连通孔450自电容器400的顶层表面朝向电容器400底层表面的方向延伸。该第一连通孔440及该第二连通孔450可藉由如激光钻孔工艺、蚀刻工艺、孔柱电镀、增层法等工艺,将具有导电性的材料填满该第一连通孔440及该第二连通孔450,或在其孔壁上涂上一具有导电性的材料,使得连通孔具有导电性。在一个实施例中,该第一连通孔440及第二连通孔450的内壁被镀上铜。由于铜具有导电性,第一连通孔440可电性连接至该第一电极410并藉由绝缘环与该第二电极420电性绝缘。相对地,第二连通孔450电性连接至第二电极420并与该第一电极410电性绝缘。因此,藉由第一连通孔440及第二连通孔450以并联方式连接多个第一电极410及第二电极420,可产生多个电容性组件。
再度参考图4,该电容器400也包含至少一个额外连通孔460,该额外连通孔460配置于任何一对该第一连通孔440及该第二连通孔450之间。该额外连通孔460在长度短于第一连通孔440的长度,而且该额外连通孔460长度也短于第二连通孔450的长度。如同该第一连通孔440及第二连通孔450,额外连通孔460可藉由如激光钻孔工艺、增层法、蚀刻、钻孔及电镀等工艺形成。然而,该第一连通孔、第二连通孔及额外连通孔的形状可为圆柱状或其它任何形状的信道及其组合。该额外连通孔460被填满或涂上一导电材料以形成导体。在一个实例中,该额外连通孔460的内壁被镀上铜。如图4所示,当该额外连通孔460被配置相对接近于一第二连通孔450时,该额外连通孔460电性连接至第一电极410,且与第一连通孔440电性导通。相反地,当额外连通孔460配置于相对接近一第一连通孔440时,该额外连通孔460电性连接至第二电极420,且与第二连通孔450电性导通。该额外连通孔460配置的目的是减少由第一连通孔440及第二连通孔450流入电容组件的电流回路面积,以降低寄生电感效应。
图5所示为根据本发明的一实例的电容器。参照图5,该电容器500类似于图4的电容器400,除了在电容器500的绝缘层430a、430b及430c分别由具有不同介电常数的绝缘材料所形成。
图6所示为根据本发明的一实例中的一电容器。参照图6,该电容器600类似于图4的电容器400,除了该电容器600可包含两个额外连通孔460a及460b,每个额外连通孔配置于一对该第一连通孔440及该第二连通孔450之间。
图7所示为根据本发明的电容器线路结构的实例,应用于一电子电路系统,当作去耦合电容器的功效。该电子电路系统700可包含一集成电路710,其藉由锡铅凸块760及焊垫770电性连接至电路板720。该电路板720包含一电容器730及线路层740。该电容器730乃根据本发明的一结构,该电容器730的第一电极732a及第二电极732b分别电性连接至一第一连通孔734a及一第二连通孔734b。一额外连通孔736在该第一连通孔734a及该第二连通孔734b之间,在本实例中,该额外连通孔736相对接近该第二连通孔734b,该额外连通孔736电性连接至第一电极732a并与第一连通孔734a电性导通。该电容器730有多个绝缘层738,其中每个绝缘层被夹在毗邻的两个金属电极之间。参照图7,该第二连通孔734b电性连接至接地层750b,其中接地层750b位于线路层740之中,然而,该额外连通孔736电性连接至电源层750a,其中电源层750a位于线路层740之中。该第一连通孔734a和第二连通孔734b透过锡铅凸块760及焊垫770电性连接至集成电路710,以作为该集成电路710的电源系统去耦合之用。依据前述线路结构,当该电路操作在一高频中,电流会流经额外连通孔736并经由第二连通孔734b流回集成电路710,进而缩小电流回路面积。该电容器可使用在多种印刷电路的应用。例如,电容器可被电性耦接或内埋于硬式及/或可挠性电子电路、印刷电路板或其它微电子器件,如芯片封装等。
虽然本发明已以较佳实施例揭露如上,然其并非用以限定本发明,在不背离本发明精神及其实质的情况下,熟悉本领域的技术人员当可根据本发明作出各种相应的改变和变形,但这些相应的改变和变形都应属于本发明所附的权利要求的保护范围。
Claims (19)
1.一电容器,其特征在于,该电容器包括:
多个电极,该电极包含一顶部电极及一底部电极,该等电极包含一组第一电极及一组第二电极;
一第一连通孔,该第一连通孔沿该电容器的厚度方向从该顶部电极延伸至该底部电极,该第一连通孔电性连接至第一电极;
一第二连通孔,该第二连通孔沿该电容器的厚度方向从该顶部电极延伸至该底部电极,该第二连通孔电性连接至第二电极;以及
一额外连通孔,该额外连通孔的位置介于该第一连通孔及该第二连通孔之间,该额外连通孔长度较该第一连通孔及该第二连通孔的长度短,而且该额外连通孔与该第一电极及该第二电极其中之一电性连接。
2.如权利要求1所述的电容器,其特征在于,该第一连通孔、该第二连通孔及该额外连通孔的形状为圆柱状或其它任何形状及其组合。
3.如权利要求1所述的电容器,其特征在于,该额外连通孔电性连接至该第一电极及该第二电极之一是取决于第一连通孔及第二连通孔何者的配置位置相对较靠近该额外连通孔。
4.如权利要求1所述的电容器,其特征在于,当该额外连通孔配置于相对靠近于该第二连通孔,该额外连通孔电性连接至该第一电极。
5.如权利要求1所述的电容器,其特征在于,当该额外连通孔配置于相对靠近于该第一连通孔时,该额外连通孔电性连接至该第二电极。
6.一内埋于一电路板的电容器,其特征在于,该电容器包括:
多个电极,其包括了一顶部电极及一底部电极,该电极包括一组第一电极及一组第二电极;
一第一连通孔,该第一连通孔沿该电容器的厚度方向从该顶部电极延伸至该底部电极,该第一连通孔电性连接至该第一电极;
一第二连通孔,该第二连通孔沿该电容器的厚度方向从该顶部电极延伸至该底部电极,该第二连通孔电性连接至该第二电极;
一额外连通孔,该额外连通孔的位置介于该第一连通孔及该第二连通孔之间,该额外连通孔长度较该第一连通孔及该第二连通孔的长度短,该额外连通孔与该第一电极及该第二电极其中之一电性连接;以及
多个绝缘层,各绝缘层被配置在两个相邻的电极之间。
7.如权利要求6所述的电容器,其特征在于,该绝缘层由相同或不同介电常数的绝缘材料所形成。
8.如权利要求6所述的电容器,其特征在于,该第一连通孔、该第二连通孔及该额外连通孔的形状为圆柱状或其它任何形状及其组合。
9.如权利要求6所述的电容器,其特征在于,该额外连通孔电性连接至该第一电极及该第二电极之一取决于第一连通孔及第二连通孔何者的配置位置相对较靠近该额外连通孔。
10.如权利要求6所述的电容器,其特征在于,当该额外连通孔配置于相对靠近该第一连通孔时,该额外连通孔电性连接至该第二电极。
11.如权利要求6所述的电容器,其特征在于,当该额外连通孔配置于相对靠近该第二连通孔时,该额外连通孔电性连接至该第一电极。
12.一集成电路承载基板,其电性连接至一集成电路芯片,其特征在于,该集成电路承载基板包括:
一包含一电源层及一接地层的线路层;以及
一电容器,该电容器电性连接至该电源层及该接地层,其中该电容器包括:
多个电极,其包括了一顶部电极及一底部电极,该电极包括一组第一电极及一组第二电极;
一第一连通孔,该第一连通孔沿该电容器的厚度方向从该顶部电极延伸至该底部电极,该第一连通孔电性连接至该第一电极;
一第二连通孔,该第二连通孔沿该电容器的厚度方向从该顶部电极延伸至该底部电极,该第二连通孔电性连接至该第二电极;
一额外连通孔,该额外连通孔的位置介于该第一连通孔及该第二连通孔之间,该额外连通孔长度较该第一连通孔及该第二连通孔的长度短,该额外连通孔与该第一电极及该第二电极其中之一电性连接;以及
多个绝缘层,各绝缘层被配置在两个相邻的电极之间。
13.如权利要求12所述的集成电路承载基板,其特征在于,该第二连通孔电性连接至该接地层,该额外连通孔及第二连通孔皆电性连接至该电源层。
14.如权利要求12所述的集成电路承载基板,其特征在于,该第一连通孔电性连接至该接地层,该额外连通孔及第二连通孔皆电性连接至该电源层。
15.如权利要求12所述的集成电路承载基板,其特征在于,该绝缘层由相同或不同介电常数的绝缘材料所形成。
16.如权利要求12所述的集成电路承载基板,其特征在于,该第一连通孔、该第二连通孔及该额外连通孔的形状为圆柱状或其它任何形状及其组合。
17.如权利要求12所述的集成电路承载基板,其特征在于,该额外连通孔电性连接至该第一电极及该第二电极之一取决于第一连通孔及第二连通孔何者的配置位置相对较靠近该额外连通孔。
18.如权利要求12所述的集成电路承载基板,其特征在于,当该额外连通孔配置于相对靠近该第一连通孔时,该额外连通孔电性连接至该第二电极。
19.如权利要求12所述的集成电路承载基板,其特征在于,当该额外连通孔配置于相对靠近该第二连通孔时,该额外连通孔电性连接至该第一电极。
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US8094429B2 (en) | 2009-06-22 | 2012-01-10 | Industrial Technology Research Institute | Multilayer capacitors and methods for making the same |
CN101930846B (zh) * | 2009-06-22 | 2012-07-04 | 财团法人工业技术研究院 | 多层电容器及其制造方法 |
CN103456495A (zh) * | 2012-05-30 | 2013-12-18 | 三星电机株式会社 | 片式层压电子元件、用于安装该元件的板及其封装单元 |
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CN103456495B (zh) * | 2012-05-30 | 2017-04-12 | 三星电机株式会社 | 片式层压电子元件、用于安装该元件的板及其封装单元 |
CN104282441A (zh) * | 2013-07-10 | 2015-01-14 | 财团法人工业技术研究院 | 内藏电容模块 |
CN108471681A (zh) * | 2018-03-16 | 2018-08-31 | 深圳市景旺电子股份有限公司 | 一种内埋电容线路板的制作方法 |
CN108471681B (zh) * | 2018-03-16 | 2020-05-05 | 深圳市景旺电子股份有限公司 | 一种内埋电容线路板的制作方法 |
Also Published As
Publication number | Publication date |
---|---|
JP2008258619A (ja) | 2008-10-23 |
CN101295585B (zh) | 2012-01-11 |
KR101013537B1 (ko) | 2011-02-14 |
US7742276B2 (en) | 2010-06-22 |
TW200839812A (en) | 2008-10-01 |
KR20080089276A (ko) | 2008-10-06 |
TWI397089B (zh) | 2013-05-21 |
US20080239622A1 (en) | 2008-10-02 |
JP5339384B2 (ja) | 2013-11-13 |
JP2011211210A (ja) | 2011-10-20 |
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