CN101154596A - 制造具有finfet的半导体器件的方法 - Google Patents

制造具有finfet的半导体器件的方法 Download PDF

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CN101154596A
CN101154596A CNA2007100909118A CN200710090911A CN101154596A CN 101154596 A CN101154596 A CN 101154596A CN A2007100909118 A CNA2007100909118 A CN A2007100909118A CN 200710090911 A CN200710090911 A CN 200710090911A CN 101154596 A CN101154596 A CN 101154596A
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张世亿
梁洪善
安台恒
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SK Hynix Inc
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Abstract

一种制造半导体器件的方法，包括：在衬底中形成器件隔离结构以限定有源区；形成硬掩模图案以开放限定有源区图案的区域以及覆盖该器件隔离结构；利用硬掩模图案作为蚀刻阻挡层通过选择使在开放区域中所形成的器件隔离结构凹陷以形成有源区图案；移除硬掩模图案；在衬底上形成栅极绝缘层以覆盖至少有源区图案；以及在栅极绝缘层上形成栅极电极以覆盖至少有源区图案。

Description

制造具有FINFET的半导体器件的方法
相关申请
本申请要求享有于2006年9月29日所提出的韩国专利申请No.10-2006-0096463的优先权，在此将该专利全文并入参考。
背景技术
本发明一般涉及制造半导体器件的方法，更具体而言涉及一种用以制造具有FinFET的半导体器件的方法。
技术领域
因为半导体器件高度集成，所以二维晶体管结构在许多方面受到限制。具体地，二维晶体管结构无法满足高速半导体器件的电流驱动能力的需求。要解决这些局限，已经提出一种鳍式场效晶体管(FinFET)。因为FinFET包括三面通道，所以FinFET具有非常高的电流驱动能力和改良的反偏压相关性。
图1A～1C描述一种用以制造传统FinFET的方法。图1A～1C中每一个的上部图示描述FinFET的平面图布局，图1A～1C中每一个的下部图示描述沿着线I-I′的剖面图。
参照图1A，在半导体衬底11上实施浅沟槽隔离(STI)工艺以形成限定有源区13的场氧化物层12。参照图1B，然后在半导体衬底11上形成具有多条直线和间隔图案的鳍式掩模14。接着利用鳍式掩模14作为蚀刻阻挡层使场氧化物层12凹陷(15A)至预定厚度以形成鳍式有源区图案15B。
参考图1C，然后移除鳍式掩模14及在鳍式有源区图案15B上形成栅极绝缘层16，接着，在栅极绝缘层16上形成栅极电极17。然后，在图1C中以符号“P”所表示的区域中形成通过栅极(passing gate)。该通过栅极为在没有形成通道的区域中所形成的栅极。该通过栅极可影响DRAM的存储节点SN，以及可降低如数据保留时间的器件特性。因此，优选在FinFET的制造期间不蚀刻在区域P中所形成的场氧化物层12。
图2A描述沿着图1C的线II-II′的剖面图。如图所示，使用鳍式有源区图案15B的3个侧面用作通道。然而，因为用作通道的鳍式有源区图案15B的3个侧面容易开放，所以难于将临界电压增加至预定水平以上。
因此，为了增加临界电压，可以在BF2、60KeV、2.0×1013原子/cm3以及30°倾斜的条件下使用离子注入工艺以在鳍式有源区图案15B的侧壁上实施侧面掺杂18，以及可以在BF2、20KeV、0～2.0×1013原子/cm3以及7°倾斜的条件下在鳍式有源区图案15B的顶部实施顶部掺杂19，从而形成磷-掺杂多晶硅栅极电极。同时，在单元区域中使用浓掺杂N-型(N+)多晶硅栅极电极。例如：可使用原位磷-掺杂多晶硅栅极电极用作N+多晶硅栅极电极。
图2B描述了在1000个单元阵列的单元晶体管的临界电压的测量结果。具体地，图2B描述了相对于在顶部掺杂期间的顶部剂量的单元临界电压(1K单元Vtsat)。即使在顶部掺杂期间分多次给予剂量，仍然很难使临界电压增加至约0.5V以上。因此，传统FinFET不能被用作需要约0.8V或更大的高临界电压的DRAM的单元晶体管。如果不能增加临界电压至预定水平以上，则可能在DRAM中大大地降低关闭漏电流特性(off leakage characteristics)。
发明内容
因此，本发明的实施方案提供一种用以制造FinFET的方法，该方法可防止在区域中所形成的场氧化物层的损失而影响存储节点。
本发明的其它实施方案提供一种用以制造具有电流驱动能力的FinFET的方法，即使容易开放鳍式有源区图案的3个侧面，该方法也不会降低关闭漏电流特性。
依据本发明的实施方案，提供一种用以制造半导体器件的方法，该方法包括：在衬底中形成器件隔离结构以限定有源区；形成硬掩模图案以开放限定有源区图案的区域并覆盖器件隔离结构；通过利用硬掩模图案作为蚀刻阻挡层选择性使在开放区域中所形成的器件隔离结构凹陷以形成有源区图案；移除该硬掩模图案；在衬底上形成栅极绝缘层以至少覆盖有源区图案；以及在栅极绝缘层上形成栅极电极以至少覆盖有源区图案。
附图说明
图1A～1C图示说明一种用以制造传统FinFET的方法。
图2A图示说明沿着图1C的线II-II′的剖面图。
图2B图示说明在1000个单元阵列中单元晶体管的临界电压的测量结果。
图3A～3I图示说明一种依据本发明的实施方案制造FinFET的方法。
图4A图示说明沿着图3F的线II-II′的剖面图。
图4B图示说明沿着图3G的线II-II′的剖面图。
图4C图示说明沿着图3H的线II-II′的剖面图。
图5A～5D图示说明一种用以依据本发明的实施方案制造具有FinFET的半导体器件的方法。
具体实施方式
本发明的实施方案提供一种用以制造具有FinFET的半导体器件的方法。该方法可防止在区域中所形成的场氧化物层的损失而影响存储节点，以及即使鳍式有源区图案的3个侧面是容易开放的，该方法也可确保高电流驱动能力而不会降低关闭漏电流特性。
图3A～3I图示说明一种依据本发明的实施方案制造FinFET的方法。在图3A～3I中，上面图示说明FinFET的平面图布局，下面图示说明沿着线I-I′的剖面图。
参考图3A，在半导体衬底21上实施浅沟槽隔离(STI)工艺以形成限定有源区23的场氧化物层22。该场氧化物层22作为器件隔离结构。有源区23具有岛状图案，该岛状图案具有长轴和短轴。线I-I′沿着有源区23的长轴方向延伸。在沿着有源区23的短轴方向形成凹式栅极。
参考图3B，在半导体衬底21上形成碳基硬掩模24。可以由非晶碳层形成碳基硬掩模24及可以具有约1000～约2000的厚度。可以在碳基硬掩模24下面形成具有小于约100厚度的氧化硅层(SiO2)。在蚀刻场氧化物层时将利用碳基硬掩模24作为硬掩模以形成鳍式有源区图案。
然后，在碳基硬掩模24上形成氧化物基硬掩模25。氧化物基硬掩模25可以由氧氮化硅层(SiON)或氧化硅层所形成并可以具有约200～约600的厚度。接着，在氧化物基硬掩模25上形成硅基硬掩模26。硅基硬掩模26可以由非晶硅或多晶硅所形成并可以具有约200～约400的厚度。利用氧化物基硬掩模25及硅基硬掩模26作为硬掩模以蚀刻碳基硬掩模24。依据本发明的实施方案，FinFET的硬掩模具有三重结构硬掩模图案。
参考图3C，沉积、曝光及显影光刻胶以形成第一光刻胶图案27。第一光刻胶图案27可以形成具有数条直线，而在所述直线间具有间隔图案。然后，利用第一光刻胶图案27选择性干蚀刻硅基硬掩模26以形成硅基硬掩模图案26A。由于相对于氧化硬掩模25的干蚀刻选择性，可容易地使硅基硬掩模26图案化。类似于第一光刻胶图案27，硅基硬掩模图案26A可以形成具有数条直线，而在直线间具有间隔图案。因而，通过硅基硬掩模图案26A部分暴露氧化物基硬掩模25的表面。参考图3D，移除第一光刻胶图案27以暴露硅基硬掩模图案26A。
参考图3E，沉积、曝光及显影光刻胶以形成第二光刻胶图案28。第二光刻胶图案28至少覆盖场氧化物层22的通过栅极区域。也就是，第二光刻胶图案28为岛状图案，该岛状图案覆盖沿着长轴方向的相邻有源区23的相互面对的末端及在相邻有源区23间所形成的场氧化物层22。
更具体地，第二光刻胶图案28覆盖在相邻有源区23间所形成的场氧化物层22以及第二光刻胶图案28的两端部分与相邻有源区23的相互面对的末端重叠。结果，第二光刻胶图案28部分暴露将形成鳍式有源区图案的有源区23的上部分及相邻于有源区23的场氧化物层22。此外，第二光刻胶图案28覆盖在有源区中的通过栅极区域的一部分，而在所述有源区中将形成鳍式有源区图案。
参考图3F，利用第二光刻胶图案28作为蚀刻掩模以干蚀刻由硅基硬掩模26A所暴露的氧化物基硬掩模25。随后干蚀刻在氧化物基硬掩模25下方所形成的碳基硬掩模24。在干式蚀刻碳基硬掩模24后，蚀刻并移除第二光刻胶图案28。
当完成上述蚀刻工艺后，在有源区23上形成堆叠硬掩模图案100。堆叠硬掩模图案100包括碳基硬掩模图案24A、氧化物基硬掩模图案25A以及硅基硬掩模图案26A。堆叠硬掩模图案100的碳基硬掩模图案24A开放鳍式有源区图案所要形成的区域。然而，堆叠硬掩模图案100的碳基硬掩模图案24A和氧化物基硬掩模图案25A保留在通过栅极区域中。
参考图3G，利用堆叠硬掩模图案100作为蚀刻阻挡层、通过干蚀刻工艺选择性地使在开放区域中所配置的场氧化物层22凹陷(29A)。因此，使有源区突出以形成有源区图案29B。该有源区图案29B为鳍式有源区图案，并且此后被称为鳍式有源区图案29B。当蚀刻场氧化物层22时，也蚀刻并移除硅基硬掩模图案26A及氧化物基硬掩模图案25A。以图3G中的虚线来表示所移除的硅基硬掩模图案26A及氧化物基硬掩模图案25A。
在形成有源区图案29B后，只保留碳基硬掩模图案24A。这意味着在形成鳍式有源区图案29B中使用碳基硬掩模图案24A作为硬掩模。此外，在通过栅极区域上也保留碳基硬掩模图案24A。因此，碳基硬掩模图案24A可防止对应于通过栅极区域的场氧化物层的损失。由于保留碳基硬掩模图案24A，因此只在相邻于鳍式有源区图案29B的场氧化物层中形成凹陷29A(见第4B图)。
参考图3H，移除碳基硬掩模图案24A。可以通过使用氧气电浆的剥离工艺以移除碳基硬掩模图案24A。
参考图3I，在鳍式有源区图案29B上形成栅极绝缘层30。可以使用氮化绝缘层来形成栅极绝缘层30，以防止掺入多晶硅中的硼的渗透。可以由SiON或HfSiON形成栅极绝缘层30。接着，在栅极绝缘层30上形成栅极电极31。可以由原位硼-掺杂多晶硅(以下称为p-型多晶硅)形成栅极电极31。硼的浓度可以为约1019原子/cm3～约1021原子/cm3，以及多晶硅的沉积厚度可以为约500～约1500。如果FinFET的栅极电极31由p-型多晶硅所形成，则硼的浓度在所有位置上都是均匀的。因此，增加临界电压不会降低关闭漏电流特性。
图4A图示说明沿着图3F的线II-II′的剖面图。图4A显示在场氧化物层22的通过栅极区域P上形成碳基硬掩模图案24A和氧化物基硬掩模图案25A。
图4B图示说明沿着图3G的线II-II′的剖面图。在场氧化物层22的通过栅极区域P上形成碳基硬掩模图案24A。因此，只在相邻鳍式有源区图案29B的场氧化物层22中形成凹陷29A。防止碳基硬掩模图案24A所覆盖的场氧化物层22的余留区域，以免损失。碳基硬掩模图案24A所覆盖的场氧化物层22的一部分影响将连接存储节点的有源区。
图4C图示说明沿着图3H的线II-II′的剖面图。参考图3H和4C，当剥离碳基硬掩模图案24A时，在有源区23中形成鳍式有源区图案29B。此外，在场氧化物层22的通过栅极区域P中没有发生蚀刻损失，以及只在相邻于鳍式有源区图案29B的区域中形成凹陷29A。在形成鳍式有源区图案中，部分蚀刻场氧化物层，从而防止对将连接存储节点的有源区的影响。
图5A～5D图示说明一种用以依据本发明的实施方案制造具有FinFET的半导体器件的方法。半导体衬底21限定单元区域和周边区域。单元区域为NMOS区域，周边区域被分成为NMOS区域和PMOS区域。
参考图5A，在具有鳍式有源区图案29B的半导体衬底21上形成栅极绝缘层30。在形成栅极绝缘层30前，在单元区域中形成鳍式有源区图案29B，此时周边区域具有二维平面结构。通过图3A～3H中所述工艺形成鳍式有源区图案29B。可以由氮化绝缘层形成栅极绝缘层30，以防止掺入多晶硅中的硼的渗透。可以由SiON或HfSiON形成栅极绝缘层30。
参考图5B，在栅极绝缘层30上形成用于栅极电极的浓掺杂P型(P+)多晶硅31。该P-型多晶硅31可以是原位硼-掺杂多晶硅。硼的浓度可以为约1019原子/cm3～约1021原子/cm3，以及多晶硅的沉积厚度可以为约500～约1500。
参考图5C，通过使用覆盖单元区域和PMOS区域的离子注入阻挡层32将磷离子Ph注入NMOS区域的P-型多晶硅31中。调整磷离子Ph的剂量以将P-型多晶硅31改变为N-型多晶硅。例如：当P-型多晶硅内的硼浓度为1020原子/cm3时，通过以1016原子/cm3的剂量注入磷离子来将P-型多晶硅改变为浓掺杂N-型(N+)多晶硅31A。可以在场氧化物层22上方延伸离子注入阻挡层32的侧面。离子注入阻挡层32可以是光刻胶图案。参考图5D，移除离子注入阻挡层32。
因为将磷离子只植入该NMOS区域中，所以浓掺杂P-型(P+)多晶硅31保留在该单元区域及该PMOS区域中，然而在NMOS区域中形成浓掺杂N-型(N+)多晶硅31A。结果，由掺杂有该P-型杂质的P-型多晶硅31形成单元区域的FinFET和PMOS区域的栅极电极，以及由掺杂有N-型杂质的N-型多晶硅31A形成NMOS区域的栅极电极。
如上所述，当使用P-型多晶硅31作为在单元区域中的FinFET的栅极电极时，在所有位置上硼浓度是均匀的。因此，临界电压增加而不会降低关闭漏电流特性。
在使用鳍式掩模蚀刻场氧化物层中，部分蚀刻场氧化物层，抑制对将连接存储节点的有源区的影响，并改善诸如数据保留时间的器件特性。此外，因为使用P-型多晶硅做该FinFET的栅极电极，其中在P-型多晶硅中的所有位置上均匀地掺杂P-型掺杂例如硼，所以可改善电流驱动能力而不降低关闭漏电流特性。
虽然已关于几个实施方案详细说明了本发明，但是可以在不偏离由所附权利要求所限定的本发明精神和范围内做出各种变化和修改，这对本领域技术人员而言是显而易见的。

Claims (24)

1.一种制造半导体器件的方法，所述方法包括：
在衬底中形成器件隔离结构以限定有源区；
形成硬掩模图案以开放限定有源区图案的区域和覆盖所述器件隔离结构；
利用所述硬掩模图案作为蚀刻阻挡层、通过选择性使在所述开放区域中形成的所述器件隔离结构凹陷从而形成所述有源区图案；
移除所述硬掩模图案；
在所述衬底上形成栅极绝缘层以至少覆盖所述有源区图案；和
在所述栅极绝缘层上形成栅极电极以至少覆盖所述有源区图案。
2.根据权利要求1所述的方法，其中所述有源区图案包含鳍式有源区图案。
3.根据权利要求1所述的方法，其中形成部分所述硬掩模图案以覆盖相邻有源区的相互面对的末端和在所述相邻有源区之间形成的所述器件隔离结构。
4.根据权利要求3所述的方法，其中所述硬掩模图案形成为具有三重结构硬掩模图案。
5.根据权利要求4所述的方法，其中形成所述三重结构硬掩模图案包括：
形成碳基硬掩模及氧化物基硬掩模；
在所述氧化物基硬掩模图案上形成硅基硬掩模图案，所述硅基硬掩模图案具有形成为具有直线的图案，在所述直线间具有间隔图案；
在所述硅基硬掩模图案上形成岛状掩模图案以覆盖相邻有源区的相互面对的末端和在所述相邻有源区之间配置的所述器件隔离结构；和
利用所述掩模图案以及所述硅基硬掩模作为蚀刻阻挡层以蚀刻所述氧化物基硬掩模和所述碳基硬掩模。
6.根据权利要求5所述的方法，其中形成所述硅基硬掩模图案包括：
在所述氧化物基硬掩模上形成硅基硬掩模；
在所述硅基硬掩模的上形成凹陷掩模，所述凹陷掩模具有形成为具有直线的图案，在所述直线间具有间隔图案；
利用所述凹陷掩模作为蚀刻阻挡层蚀刻所述硅基硬掩模以形成所述硅基硬掩模图案；和
移除所述硅基硬掩模。
7.根据权利要求5所述的方法，其中所述碳基硬掩模包括非晶碳层。
8.根据权利要求7所述的方法，其中所述碳基硬掩模形成的厚度为约1000～约2000。
9.根据权利要求5所述的方法，还包括：
在所述碳基硬掩模和所述衬底之间形成厚度为约100或更小的氧化物层。
10.根据权利要求5所述的方法，其中利用氧氮化硅层或氧化硅层以形成氧化物基硬掩模。
11.根据权利要求10所述的方法，其中所述氧化物基硬掩模形成的厚度为约200～约600。
12.根据权利要求5所述的方法，其中所述硅基硬掩模包括非晶硅或多晶硅。
13.根据权利要求12所述的方法，其中所述硅基硬掩模形成的厚度为约200～约400。
14.根据权利要求1所述的方法，其中所述栅极绝缘层包括氮化绝缘层。
15.根据权利要求14所述的方法，其中所述氮化绝缘层包括SiON或HfSiON。
16.根据权利要求1所述的方法，其中所述栅极电极包括掺杂有P-型杂质的多晶硅。
17.根据权利要求16所述的方法，其中所述P-型杂质为硼。
18.根据权利要求17所述的方法，其中所述硼的浓度为约1019原子/cm3～约1021原子/cm3。
19.根据权利要求16所述的方法，其中所述多晶硅形成的厚度为约500～1500。
20.根据权利要求1所述的方法，其中所述衬底限定形成有鳍式有源区图案的单元区域和形成有平面有源区的周边区域，以及所述栅极电极的形成包括：
形成掺杂有P-型杂质的P-型多晶硅；和
将N-型杂质掺杂到在周边区域中所形成的部分P-型多晶硅中。
21.根据权利要求20所述的方法，其中将所述周边区域分成NMOS区域和PMOS区域，和所述单元区域为NMOS区域，将N-型杂质掺杂至NMOS区域的P-型多晶硅中。
22.根据权利要求21所述的方法，其中所述P-型杂质为硼，所述N-型杂质为磷。
23.根据权利要求22所述的方法，其中所述硼的浓度为约1019原子/cm3～约1021原子/cm3。
24.根据权利要求20所述的方法，其中所述P-型多晶硅形成的厚度为约500～约1500。
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