CN101084579A - 形成介电膜的方法和利用该方法在半导体器件中形成电容器的方法 - Google Patents
形成介电膜的方法和利用该方法在半导体器件中形成电容器的方法 Download PDFInfo
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- CN101084579A CN101084579A CNA2005800439855A CN200580043985A CN101084579A CN 101084579 A CN101084579 A CN 101084579A CN A2005800439855 A CNA2005800439855 A CN A2005800439855A CN 200580043985 A CN200580043985 A CN 200580043985A CN 101084579 A CN101084579 A CN 101084579A
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Abstract
提供一种在半导体器件中形成介电膜的方法,其中所述方法可以改善介电特性和漏电流特性。依照本发明的具体实施方案,形成介电膜的方法包括:在晶片上形成预定厚度的二氧化锆(ZrO2)层,该厚度不允许形成的ZrO2层连续;在没有形成ZrO2层的晶片部分上形成预定厚度的氧化铝(Al2O3)层,该厚度不允许形成的Al2O3层连续。
Description
技术领域
本发明涉及在半导体器件中形成介电膜的方法和利用该方法形成电容器的方法。更具体而言,涉及使用原子层沉积(ALD)方法在半导体器件中形成介电膜的方法以及利用该方法形成电容器的方法。
背景技术
最近,随着动态随机存储器(DRAM)设计规则(design rule)的减小,单元区域减小,电容器的存储节点深宽比大幅增加。因此,保证每个单位单元所需的介质电容(dielectric capacity)变得困难。
传统上,介电膜形成为氧化物/氮化物/氧化物(ONO)层结构以保证介质电容。然而,最近已经对具有氧化铝(Al2O3)层(ε=9)、二氧化铪(HfO2)层(ε=25)、或者HfO2/Al2O3叠层的介电膜进行了积极的研究,试图获得较大的介质电容,其中所述的Al2O3层与HfO2层都具有高的介电常数。而且,这种介电膜的形成使用的是原子层沉积(ALD)方法而非传统的化学气相沉积(CVD)方法,以应对大的深宽比。
然而,对于用HfO2/Al2O3叠层形成的介电膜,整个介电膜的介电特性和漏电流特性取决于每种材料的相应的介电常数ε和带隙能Eg。也就是说,由传统叠层HfO2/Al2O3形成的介电膜显示出的电特性是由每个层特性的组合而形成,如下文所述。
通常,Al2O3层的介电常数ε和带隙能Eg分别为9和9eV。另一方面,HfO2层的介电常数和带隙能Eg通常认为分别是25和5.6eV。也就是说,整个介电膜的介电特性受HfO2层的影响,漏电流特性受Al2O3层带隙能Eg的影响。相反,整个介电膜的漏电流特性由于HfO2层的低带隙能Eg而变差,整个介电膜的绝缘特性由于Al2O3层的低介电常数而变差。因此,如果介电膜用于DRAM器件的电容器中,在降低介电膜厚度方面存在大的局限。
然而,Al2O3层起降低HfO2层结晶温度的作用,所述HfO2层是构成介电膜的另一层,而且通过这种作用,减小介电膜的漏电流。因此,为了改善介电膜的特性,通常需要控制与Al2O3层一起形成介电膜的氧化物材料的介电常数和带隙能。
发明内容
技术问题
本发明的一个目的是提供一种在半导体器件中形成介电膜的方法,此方法可改善介电特性以及漏电流特性。
本发明的另一个目的是提供一种使用所述形成介电膜的方法在半导体器件中形成电容器的方法。
技术解决方案
依照本发明的一个方面,提供一种形成介电膜的方法,包括:在晶片上形成预定厚度的二氧化锆(ZrO2)层,此厚度不允许形成的ZrO2层连续。接着在没有形成ZrO2层的晶片部分上形成预定厚度的氧化铝(Al2O3)层,此厚度不允许形成的Al2O3层连续。
依照本发明的另一个方面,提供一种形成介电膜的方法,包括:在晶片上形成预定厚度的Al2O3层,此厚度不允许形成的Al2O3层连续。接着在没有形成Al2O3层的晶片部分上形成预定厚度的ZrO2层,此厚度不允许形成的ZrO2层连续。
依照本发明的又一个方面,提供的一种形成介电膜的方法,包括:使用Zr原子和Al原子形成为一个分子的源气体,在晶片上形成ZrO2与Al2O3相混合的[ZrO2]x[Al2O3]y层,其中x和y各自代表0或正数。
依照本发明的又一个方面,提供一种形成电容器的方法,包括:制备其上形成有接触塞的衬底结构;以一定的方式在衬底结构上形成图案化绝缘层以暴露接触塞。在图案化绝缘层和衬底结构上形成下电极;利用权利要求1到权利要求27中之一的方法在下电极上形成介电膜;在介电膜上形成上电极。
有利效果
依照本发明的具体实施方案,在半导体器件中使用的电容器的介电特性和漏电流特性可以通过使用[ZrO2]x[Al2O3]y层形成介电膜而得以改善,其中x和y各自代表0或正数。其中,ZrO2和Al2O3在[ZrO2]x[Al2O3]y层中均匀地混合。
附图说明
本发明的上述和其他目的、以及特征将可通过下面结合附图给出的对示例性实施方案的描述变得明显。
图1是图示说明依照本发明第一实施方案形成介电膜方法的流程图;
图2是图示说明形成图1中所述二氧化锆(ZrO2)层的方法的图。
图3是图示说明形成图1中所述氧化铝(Al2O3)层的方法的图。
图4A与图4B表示图示说明通过图1描述的方法形成的介电膜的图。
图5是图示说明依照本发明第二实施方案形成介电膜的方法的流程图。
图6是图示说明依照本发明第三实施方案形成介电膜的方法的流程图。
图7是图示说明形成图6中所述[ZrO2]x[Al2O3]y层的方法的图。
图8到图10是图示说明依照本发明具体实施方案形成电容器方法的截面图。
具体实施方式
通过下面参考附图对实施方案的描述,本发明的其他目的和方面将变得明显。
第一实施方案
图1是图示说明依照本发明第一实施方案在半导体器件中形成介电膜的方法的工艺流程图。图2是图示说明二氧化锆(ZrO2)层形成过程次序的图。图3是图示说明氧化铝(Al2O3)形成过程次序的图。
参照图1到图3,依照本发明第一实施方案,在半导体器件中形成介电膜的方法包括利用原子层沉积(ALD)的方法形成ZrO2层,然后形成Al2O3层。
ZrO2层的形成过程如下。虽然没有图示说明,但是在步骤S10中将选自Zr(OtBu)4、Zr[N(CH3)2]4、Zr[N(C2H5)(CH3)]4、Zr[N(C2H5)2]4、Zr(TMHD)4、Zr(OiC3H7)3(TMTD)以及Zr(OtBu)4的一种源气体供应到ALD设备腔体内以在晶片上吸附锆(Zr)。在此,在腔室内部保持大约200℃~大约350℃的温度。随后,在步骤S11中,在腔室内供应氮气(N2),以将未被吸附的残留Zr源气体清洗出腔室。接着,在步骤S12中,在腔室内供应O3,以氧化在晶片上吸附的Zr,由此氧化形成ZrO2层。然后,在步骤S13中,在腔室内供应N2,清洗未反应的O3。实施步骤S10到S13作为一个循环Tzr,重复实施Tzr直到ZrO2层的厚度T1达到大约10。在这里,将ZrO2层的厚度T1限制在大约10的原因是在晶片W上非连续性地形成ZrO2层,如图4A所示。在一个循环Tzr期间,ZrO2层的厚度T1达到小于约1。因此,重复循环Tzr约10次可形成厚度接近大约10的ZrO2层。
随后,实施Al2O3层的形成。Al2O3层的形成如下。在步骤S15中,在腔室内供应Al(CH3)3源气体,以在晶片上原位吸附Al。接着,在步骤S16中,在腔室内供应N2气体,以将未被吸附的残留Al源气体清洗出腔室。接下来,在步骤S17中,在腔室内供应O3,以在未形成ZrO2层的晶片部分上形成Al2O3层。如上面所述,当ZrO2层的厚度T1被限制在小于大约10(也就是厚度大约1~大约10)时,在晶片W上非连续性地形成ZrO2层,如图4B所示。因此,在未形成ZrO2层1的晶片部分上即在ZrO2层1之间形成Al2O3层2。随后,在步骤S18中,在腔室内供应N2气体,以清洗所有未反应的O3气体。实施步骤S15到S18作为一个循环TAl,重复实施TAl直到Al2O3层的厚度T2达到小于大约10。在一个循环TAl期间,Al2O3层的厚度T2达到约小于1。因此,重复循环TAl约10次可形成厚度TAl接近大约10的Al2O3层。
此外,如果包括ZrO2层与Al2O3层的混合层厚度T最终小于目标厚度T目标,那么,ZrO2层形成循环Tzr和Al2O3层形成循环TAl在步骤S21和S22中各重复实施一次。步骤S21和S22重复实施直至厚度T最终与目标厚度T目标变得基本上等同。在这里,包括ZrO2层与Al2O3层的混合层的厚度T最终可以形成为约30~约500。
通过上述工程,利用[ZrO2]x[Al2O3]y形成介电膜,其中x和y各代表0或正数。
第二实施方案
图5是图示说明依照本发明第二实施方案形成介电膜方法的流程图。
如图5所示,依照本发明的第二实施方案形成介电膜的方法使用ALD方法,如同本发明第一实施方案。然而,在第二实施方案中,在晶片上非连续性地形成Al2O3层,之后形成ZrO2层,而不是先形成ZrO2层。除此区别之外,本发明的第二实施方案与本发明的第一实施方案的实施过程是基本上一致的。因此,为描述的方便,这里简化了关于第二方案的详细描述。
第三实施方案
图6是图示说明依照本发明的第三实施方案形成介电膜方法的流程图,图7是图示说明同时形成[ZrO2]x[Al2O3]y层的形成过程的图。
参照图6和图7,依照本发明第三实施方案在半导体器件中形成介电膜的方法使用ALD方法,以同时形成[ZrO2]x[Al2O3]y层。
虽然没有示出,但是在步骤S210中在ALD设备的腔室内供应其中Zr和Al形成一个分子的源气体如ZrAl(MMP)2(OiPr)5,以在晶片上吸附Zr和Al。在此,腔室里的温度保持在大约200℃~大约350℃。随后,在步骤S211中,在腔室内供应氮气(N2),以将未被吸附的残留源气体清洗出腔室。接着,在步骤S212中,在腔室内供应O3,以氧化吸附在晶片上的Zr和Al,从而形成[ZrO2]x[Al2O3]y层。这里,x与y之和可以小于大约10。
然后,在步骤S213中,在腔室内供应N2,以清洗所有未反应的O3。实施步骤S210到S213作为一个循环TZr/Al。如果[ZrO2]x[Al2O3]y层的厚度T3小于目标厚度T目标,那么循环TZr/Al(步骤S210到S213)重复实施直到[ZrO2]x[Al2O3]y层的厚度T3与目标厚度T目标变得基本相同。这里,[ZrO2]x[Al2O3]y层的厚度T3可以形成在大约30到大约500的范围内。
另一方面,虽然本发明的第一到第三实施方案在氧化过程使用O3,但O3只是一个例子,H2O或者氧等离子体都可用来代替O3。同样,在本发明第一到第三实施方案中的清洗过程使用N2气体,N2也是一个例子,清洗过程可以通过使用真空泵或氩(Ar)气来进行。
[37]下面的表1和表2是用以比较HfO2与ZrO2特性的对比表格。
表1
材料 | 介电常数(ε) | 带隙能Eg(eV) | 对Si的ΔEc(eV) | 晶体结构 |
SiO2 | 3.9 | 8.9 | 3.2 | 非晶 |
Si3N4 | 7 | 5.1 | 2 | 非晶 |
Al2O3 | 9 | 8.7 | 2.8a | 非晶 |
Y2O3 | 15 | 5.6 | 2.3a | 立方 |
La2O3 | 30 | 4.3 | 2.3a | 六方,立方 |
Ta2O5 | 26 | 4.5 | 1-1.5 | 正交 |
TiO2 | 80 | 3.5 | 1.2 | 四方a(金红石,锐钛矿) |
HfO2 | 25 | 5.7 | 1.5a | 单斜b,四方c,立方 |
ZrO2 | 25 | 7.8 | 1.4a | 单斜b,四方c,立方 |
表2
元素 | 名称 | 分子量(g/mol) | 温度(1Torr) | 源分解温度(℃) |
Hf | Hf[N(C2H5)2]4 | 466.49 | 126 | 150 |
Hf[N(CH3)2]4 | 354.49 | 75 | 90 | |
Hf[N(C2H5)(CH3)]4 | 410.49 | 113 | 140 | |
Zr | Zr[N(C2H5)2]4 | 379.74 | 108 | 140 |
Zr [N(CH3)2]4 | 267.22 | 77 | 80 | |
Zr[N(C2H5)(CH3)]4 | 323.22 | 106 | 130 |
如上面表1所示,ZrO2的介电常数与HfO2类似,然而,ZrO2的带隙能相对大于HfO2的带隙能。也就是说,以叠层或混合层结构使用Al2O3-ZrO2,整个薄膜的带隙能增加,改善了介电膜的漏电流特性。这样,减小介电膜的厚度变得容易。此外,如果使用ZrO2代替HfO2,更有利于介电膜应用于大规模生产的工艺中,这是由于可商用的Zr源与Hf源相比具有极小的饱和蒸汽压与分子量,因而具有更容易处理的巨大优点。
在下文中,参照图8到图10描述形成电容器的方法,利用在本发明第一到第三实施方案中形成介电膜的方法。图8到图10是图示说明在动态随机存储器(DRAM)中形成凹型电容器方法的截面图。
参照图8,提供衬底10,在衬底10上形成有包括存储节点接触塞18的底层。这里,底层10还包括:导电层12,第一到第三层间绝缘层11、13和17,位线14,硬掩膜15和隔离物16。这里,导电层12通过使用多晶硅形成,第一到第三层间绝缘层11、13和17各自通过使用氧化物基的材料形成。而且,位线14通过使用多晶硅(或氮化钛(TiN))和钨(或硅化钨)形成,硬掩膜15通过使用氮化物基的材料形成。
随后,用于存储节点图案的绝缘层19在上述得到的衬底结构上形成,暴露出存储节点接触塞18的顶部。这里,绝缘层19通过使用氧化物基的材料或多晶硅形成。
此外,在上述整个所得结构上形成存储节点20。这里,存储节点20是电容器的下电极,它是通过使用选自掺杂有杂质例如磷(P)和砷(As)的多晶硅、TiN、钌(Ru)、二氧化钌(RuO2)、铂(Pt)、铱(Ir)以及二氧化铱(IrO2)中的一种而形成的。
而且,如图9所示,介电膜21在存储节点20上形成。这里,通过使用本发明第一到第三实施方案中的一个,使用[ZrO2]x[Al2O3]y形成介电膜21,其中ZrO2与Al2O3均匀地混合。这里,x和y各自代表0或正数。例如,x与y之和可以保持在小于大约10。
接着,对介电膜21实施热处理工程。这里,热处理过程通过使用选自下面方法中的一种进行:炉法,快速温度处理(RTP),以及快速温度退火(RTA)方法。这里,热处理过程在包含少量Ar、N2或氧气(O2)的气氛中,在大约450℃到850℃的温度下进行。
随后,如图10所示,在介电膜21上形成上电极22。这里,上电极22通过采用与存储节点20基本相同的材料形成。例如,上电极22是通过使用选自掺杂有杂质例如P和As的多晶硅、TiN、Ru、RuO2、Pt、Ir以及IrO2中的一种形成。
本发明的具体实施方案仅描述了应用于凹型结构的电容器的实施方案。然而,凹型结构的电容器只是一个例子,本发明的实施方案也能被应用到平板和圆柱结构的电容器中。同样,该实施方案可以用作射频(RF)器件中电容器的介电膜用。此外,该实施方案可以在包括闪存、电可擦除可编程只读存储器(EEPROM)以及可擦除可编程只读存储器(EPROM)的存储器件中,应用于置于浮栅与控制棚之间的介电膜。
本申请包含涉及韩国专利申请2004-0110920的主题,该专利申请于2004年12月23日提交至韩国知识产权局,其全部内容通过引用全部并入本文。
尽管已经对本发明关于一些优选实施方案进行了描述,然而对于本领域技术人员来说,显然可以进行各种变化和修改,而并不脱离在所附权利要求中限定的发明范围。
Claims (29)
1.一种形成介电膜的方法,包括:
在晶片上形成预定厚度的二氧化锆(ZrO2)层,所述厚度不允许形成的ZrO2层连续;
在没有形成所述ZrO2层的晶片部分上形成预定厚度的氧化铝(Al2O3)层,所述厚度不允许形成的Al2O3层连续。
2.根据权利要求1所述的方法,其中所述ZrO2层的形成包括形成厚度为约1~约10的ZrO2层,所述厚度不允许形成ZrO2层连续。
3.根据权利要求1所述的方法,其中所述Al2O3层的形成包括形成厚度为约1~约10的Al2O3层,所述厚度不允许形成的Al2O3层连续。
4.根据权利要求1所述的方法,其中作为所述ZrO2层与所述Al2O3层的混合层的所述介电膜形成为约30~约500的厚度。
5.根据权利要求1所述的方法,其中所述ZrO2层的形成包括:
在原子层沉积(ALD)设备的腔室内供应锆(Zr)源气体,以在所述晶片上吸附所述Zr源气体;
在所述腔室内供应惰性气体或使用真空泵,以清洗未被吸附的Zr源气体;
在所述腔室内供应氧化气体,以氧化吸附的Zr源气体,从而形成ZrO2层;和
在所述腔室内供应惰性气体或使用真空泵,以清洗所有未反应的氧化气体。
6.根据权利要求5所述的方法,其中在将所述ZrO2层形成至预定厚度的范围内来重复进行所述ZrO2层的形成,所述厚度不允许在所述晶片上形成的ZrO2层连续。
7.根据权利要求5所述的方法,其中所述ZrO2层的形成包括使用Zr源气体、惰性气体和氧化气体,所述Zr源气体包括选自Zr(O-tBu)4、Zr[N(CH3)2]4、Zr[N(C2H5)(CH3)]4、Zr[N(C2H5)2]4、Zr(TMHD)4、Zr(OiC3H7)3(TMTD)以及Zr(OtBu)4中的一种,所述惰性气体包括氩(Ar)和氮(N2)的一种,所述氧化气体包括选自水(H2O),臭氧(O3)以及氧等离子体中的一种。
8.根据权利要求5所述的方法,其中在约200℃~约350℃的温度下进行所述ZrO2层的形成。
9.根据权利要求1所述的方法,其中所述Al2O3层的形成包括:
在ALD设备的腔室内供应铝(Al)源气体,以在所述晶片上吸附所述Al源气体;
在所述腔室内供应惰性气体或使用真空泵,以清洗未被吸附的Al源气体;
在所述腔室内供应氧化气体,以氧化吸附的Al源气体,从而形成Al2O3层;和
在所述腔室内供应惰性气体或使用真空泵,以清洗所有未反应的氧化气体。
10.根据权利要求9所述的方法,其中在将Al2O3层形成至预定厚度的范围内来重复进行所述Al2O3层的形成,所述厚度不允许在所述晶片上形成的Al2O3层连续。
11.根据权利要求9所述的方法,其中所述Al2O3层的形成包括使用包括Al(CH3)3的Al源气体、包括氩(Ar)和氮(N2)中的一种的惰性气体以及包括选自H2O、O3和氧等离子体中的一种的氧化气体。
12.一种形成介电膜的方法,包括:
在晶片上形成预定厚度的Al2O3层,所述厚度不允许形成的Al2O3层连续;
在没有形成所述Al2O3层的晶片部分上形成预定厚度的ZrO2层,所述厚度不允许形成的ZrO2层连续。
13.根据权利要求12所述的方法,其中所述ZrO2层的形成包括形成厚度为约1~约10的ZrO2层,所述厚度不允许形成的ZrO2层连续。
14.根据权利要求12所述的方法,其中所述Al2O3层的形成包括形成厚度为约1~约10的Al2O3层,所述厚度不允许形成的Al2O3层连续。
15.根据权利要求12所述的方法,其中作为所述ZrO2层与所述Al2O3层的混合层的所述介电膜形成为约30~约500的厚度。
16.根据权利要求12中所述的方法,其中所述ZrO2层的形成包括:
在ALD设备的的腔室内供应Zr源气体,以在所述晶片上吸附所述Zr源气体;
在所述腔室内供应惰性气体或使用真空泵,以清洗未被吸附的Zr源气体;
在所述腔室内供应氧化气体,以氧化吸附的Zr源气体,从而形成ZrO2层;和
在所述腔室内供应惰性气体或使用真空泵,以清洗所有未反应的氧化气体。
17.根据权利要求16所述的方法,其中在将所述ZrO2层形成至预定厚度的范围内来重复进行所述ZrO2层的形成,所述厚度不允许在晶片上形成的ZrO2层连续。
18.根据权利要求16所述的方法,其中所述ZrO2层的形成包括使用Zr源气体、惰性气体和氧化气体,所述Zr源气体包括选自Zr(O-tBu)4、Zr[N(CH3)2]4、Zr[N(C2H5)(CH3)]4、Zr[N(C2H5)2]4、Zr(TMHD)4、Zr(OiC3H7)3(TMTD)以及Zr(OtBu)4中的一种,所述惰性气体包括氩(Ar)和氮(N2)中的一种,所述氧化气体包括选自水(H2O)、臭氧(O3)以及氧等离子体中的一种。
19.根据权利要求16所述的方法,其中在约200℃~约350℃的温度下进行所述ZrO2层的形成。
20.根据权利要求12所述的方法,其中所述Al2O3层的形成包括:
在ALD设备的腔室内供应Al源气体,以在所述晶片上吸附所述Al源气体;
在所述腔室内供应惰性气体或使用真空泵,以清洗未被吸附的Al源气体;
在所述腔室内供应氧化气体,以氧化吸附的Al源气体,从而形成Al2O3层;和
在所述腔室内供应惰性气体或使用真空泵,以清洗所有未反应的氧化气体。
21.根据权利要求20所述的方法,其中是将Al2O3层形成至预定厚度的范围内来重复进行所述Al2O3层的形成,所述厚度不允许在晶片上形成的Al2O3层连续。
22.根据权利要求20所述的方法,其中所述Al2O3层的形成包括使用包括Al(CH3)3的Al源气体、包括氩(Ar)和氮(N2)中的一种的惰性气体以及包括选自H2O、O3和氧等离子体中的一种的氧化气体。
23.一种形成介电膜的方法,包括使用源气体在晶片上形成ZrO2与Al2O3混合的[ZrO2]x[Al2O3]y层,其中x和y各自代表0或正数3在所述源气体中Zr原子和Al原子形成为一个分子。
24.根据权利要求23所述的方法,其中所述[ZrO2]x[Al2O3]y层的形成包括使x与y之和小于约10。
25.根据权利要求23所述的方法,其中作为所述ZrO2层与所述Al2O3层的混合层的所述介电膜形成为约30~约500的厚度。
26.根据权利要求23所述的方法,其中所述[ZrO2]x[Al2O3]y层的形成包括使用包括ZrAl(MMP)2(OiPr)5的源气体。
27.根据权利要求23所述的方法,其中所述[ZrO2]x[Al2O3]y层的形成包括:
在ALD设备的腔室内供应源气体,以在所述晶片上吸附所述源气体,在所述源气体中Zr原子和Al原子形成为一个分子;
在所述腔室内供应惰性气体或使用真空泵,以清洗未被吸附的源气体;
在所述腔室内供应氧化气体,以氧化吸附的源气体,从而形成[ZrO2]x[Al2O3]y层;和
在所述腔室内供应惰性气体或使用真空泵,以清洗所有未反应的氧化气体。
28.一种形成电容器的方法,包括:
制备在其上形成有接触塞的衬底结构;
在所述衬底结构上以暴露所述接触塞的方式形成图案化绝缘层;
在所述图案化绝缘层和所述衬底结构上形成下电极;和
利用权利要求1到权利要求27中一项所述的方法在所述下电极上形成介电膜;和
在所述介电膜上形成上电极。
29.根据权利要求28所述的方法,还包括在所述介电膜形成之后,对所述介电膜实施热处理过程,其中所述热处理过程在Ar、N2或氧(O2)的气氛中,在约450℃~约850℃的温度下实施。
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KR100772101B1 (ko) | 2005-06-30 | 2007-11-01 | 주식회사 하이닉스반도체 | 반도체 소자의 캐패시터 형성방법 |
KR100728959B1 (ko) | 2005-08-18 | 2007-06-15 | 주식회사 하이닉스반도체 | 반도체 소자의 캐패시터 형성방법 |
KR100717824B1 (ko) | 2005-08-29 | 2007-05-11 | 주식회사 하이닉스반도체 | 캐패시터 및 그의 제조방법 |
KR20070045661A (ko) | 2005-10-28 | 2007-05-02 | 주식회사 하이닉스반도체 | 캐패시터 제조 방법 |
KR100798735B1 (ko) | 2005-10-31 | 2008-01-29 | 주식회사 하이닉스반도체 | 캐패시터 및 그 제조 방법 |
KR100655139B1 (ko) | 2005-11-03 | 2006-12-08 | 주식회사 하이닉스반도체 | 캐패시터 제조 방법 |
KR100722989B1 (ko) | 2005-11-10 | 2007-05-30 | 주식회사 하이닉스반도체 | 캐패시터 및 그 제조 방법 |
KR100655140B1 (ko) | 2005-11-10 | 2006-12-08 | 주식회사 하이닉스반도체 | 캐패시터 및 그 제조 방법 |
KR100656283B1 (ko) | 2005-12-14 | 2006-12-11 | 주식회사 하이닉스반도체 | 반도체 소자의 캐패시터 제조 방법 |
KR100672766B1 (ko) | 2005-12-27 | 2007-01-22 | 주식회사 하이닉스반도체 | 반도체 소자의 캐패시터 제조 방법 |
-
2004
- 2004-12-23 KR KR1020040110920A patent/KR20060072338A/ko active Search and Examination
-
2005
- 2005-12-23 JP JP2007548093A patent/JP2008526017A/ja active Pending
- 2005-12-23 WO PCT/KR2005/004508 patent/WO2006068453A1/en active Application Filing
- 2005-12-23 CN CNB2005800439855A patent/CN100550387C/zh not_active Expired - Fee Related
- 2005-12-23 US US11/722,680 patent/US20080138503A1/en not_active Abandoned
-
2010
- 2010-09-30 US US12/895,678 patent/US8092862B2/en not_active Expired - Fee Related
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2012
- 2012-02-22 JP JP2012035989A patent/JP2012142587A/ja active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103545316A (zh) * | 2012-12-31 | 2014-01-29 | 安阳师范学院 | 基于带隙调控的新型电荷陷阱型存储器、其制备方法及应用 |
CN103545316B (zh) * | 2012-12-31 | 2016-06-15 | 安阳师范学院 | 基于带隙调控的新型电荷陷阱型存储器、其制备方法及应用 |
CN106716561A (zh) * | 2014-09-17 | 2017-05-24 | Arm 有限公司 | 具有随机电气特性的电气部件 |
CN106716561B (zh) * | 2014-09-17 | 2019-11-22 | Arm 有限公司 | 具有随机电气特性的电气部件 |
Also Published As
Publication number | Publication date |
---|---|
US20080138503A1 (en) | 2008-06-12 |
WO2006068453A1 (en) | 2006-06-29 |
US8092862B2 (en) | 2012-01-10 |
CN100550387C (zh) | 2009-10-14 |
JP2008526017A (ja) | 2008-07-17 |
JP2012142587A (ja) | 2012-07-26 |
KR20060072338A (ko) | 2006-06-28 |
US20110027465A1 (en) | 2011-02-03 |
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