CN100578774C - 具有降低的功率分配阻抗的互连模块及其制造方法 - Google Patents
具有降低的功率分配阻抗的互连模块及其制造方法 Download PDFInfo
- Publication number
- CN100578774C CN100578774C CN02816537A CN02816537A CN100578774C CN 100578774 C CN100578774 C CN 100578774C CN 02816537 A CN02816537 A CN 02816537A CN 02816537 A CN02816537 A CN 02816537A CN 100578774 C CN100578774 C CN 100578774C
- Authority
- CN
- China
- Prior art keywords
- layer
- conductive
- conductive layer
- dielectric layer
- dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
- H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/8121—Applying energy for connecting using a reflow oven
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00013—Fully indexed content
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01068—Erbium [Er]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01084—Polonium [Po]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/113—Via provided in pad; Pad over filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0104—Properties and characteristics in general
- H05K2201/0112—Absorbing light, e.g. dielectric layer with carbon filler for laser processing
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
- H05K2201/0203—Fillers and particles
- H05K2201/0206—Materials
- H05K2201/0209—Inorganic, non-metallic particles
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0355—Metal foils
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/04—Assemblies of printed circuits
- H05K2201/049—PCB for one component, e.g. for mounting onto mother PCB
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/0929—Conductive planes
- H05K2201/09309—Core having two or more power planes; Capacitive laminate of two power planes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09509—Blind vias, i.e. vias having one side closed
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/0959—Plated through-holes or plated blind vias filled with insulating material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09672—Superposed layout, i.e. in different planes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09718—Clearance holes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
- H05K2203/1377—Protective layers
- H05K2203/1383—Temporary protective insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
- H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
- H05K3/0035—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Emergency Protection Circuit Devices (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Structure Of Printed Boards (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US31490501P | 2001-08-24 | 2001-08-24 | |
| US60/314,905 | 2001-08-24 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1547772A CN1547772A (zh) | 2004-11-17 |
| CN100578774C true CN100578774C (zh) | 2010-01-06 |
Family
ID=23221997
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN02816537A Expired - Fee Related CN100578774C (zh) | 2001-08-24 | 2002-08-22 | 具有降低的功率分配阻抗的互连模块及其制造方法 |
Country Status (12)
| Country | Link |
|---|---|
| US (1) | US6847527B2 (enExample) |
| EP (1) | EP1419528B1 (enExample) |
| JP (1) | JP2005501415A (enExample) |
| KR (1) | KR100896548B1 (enExample) |
| CN (1) | CN100578774C (enExample) |
| AT (1) | ATE343222T1 (enExample) |
| AU (1) | AU2002326733A1 (enExample) |
| CA (1) | CA2456769A1 (enExample) |
| DE (1) | DE60215518T2 (enExample) |
| DK (1) | DK1419528T3 (enExample) |
| TW (1) | TW559955B (enExample) |
| WO (1) | WO2003019656A2 (enExample) |
Families Citing this family (123)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW586205B (en) * | 2001-06-26 | 2004-05-01 | Intel Corp | Electronic assembly with vertically connected capacitors and manufacturing method |
| US7064447B2 (en) * | 2001-08-10 | 2006-06-20 | Micron Technology, Inc. | Bond pad structure comprising multiple bond pads with metal overlap |
| US7323767B2 (en) * | 2002-04-25 | 2008-01-29 | Micron Technology, Inc. | Standoffs for centralizing internals in packaging process |
| ATE321349T1 (de) * | 2002-05-24 | 2006-04-15 | Koninkl Philips Electronics Nv | Modul zur entkopplung von hochfrequenz-signalen von einer versorgungsleitung |
| US7438969B2 (en) * | 2002-07-10 | 2008-10-21 | Ngk Spark Plug Co., Ltd. | Filling material, multilayer wiring board, and process of producing multilayer wiring board |
| TW200404484A (en) * | 2002-09-02 | 2004-03-16 | Furukawa Circuit Foil | Copper foil for soft circuit board package module, for plasma display, or for radio-frequency printed circuit board |
| US20040104463A1 (en) * | 2002-09-27 | 2004-06-03 | Gorrell Robin E. | Crack resistant interconnect module |
| US7522886B2 (en) * | 2002-10-03 | 2009-04-21 | Amplus Communication Pte. Ltd. | Radio frequency transceivers |
| US7023707B2 (en) * | 2003-01-30 | 2006-04-04 | Endicott Interconnect Technologies, Inc. | Information handling system |
| US7035113B2 (en) * | 2003-01-30 | 2006-04-25 | Endicott Interconnect Technologies, Inc. | Multi-chip electronic package having laminate carrier and method of making same |
| US7476813B2 (en) * | 2003-05-14 | 2009-01-13 | Rambus Inc. | Multilayer flip-chip substrate interconnect layout |
| JP2007535123A (ja) * | 2003-07-14 | 2007-11-29 | エイブイエックス コーポレイション | モジュール式電子アッセンブリーおよび製造方法 |
| US7791210B2 (en) * | 2003-11-05 | 2010-09-07 | Lsi Corporation | Semiconductor package having discrete non-active electrical components incorporated into the package |
| US6867124B1 (en) * | 2003-12-04 | 2005-03-15 | Intel Corporation | Integrated circuit packaging design and method |
| JP4700332B2 (ja) | 2003-12-05 | 2011-06-15 | イビデン株式会社 | 多層プリント配線板 |
| EP1538640B1 (en) | 2003-12-05 | 2016-11-16 | NGK Spark Plug Co., Ltd. | Capacitor and method for manufacturing the same |
| KR20080088670A (ko) * | 2004-02-04 | 2008-10-02 | 이비덴 가부시키가이샤 | 다층프린트배선판 |
| US7478472B2 (en) * | 2004-03-03 | 2009-01-20 | Endicott Interconnect Technologies, Inc. | Method of making circuitized substrate with signal wire shielding |
| EP1578179A3 (en) * | 2004-03-16 | 2006-05-03 | E.I. du Pont de Nemours and Company | Thick-film dielectric and conductive compositions |
| US7489517B2 (en) * | 2004-04-05 | 2009-02-10 | Thomas Joel Massingill | Die down semiconductor package |
| CN100544558C (zh) * | 2004-04-28 | 2009-09-23 | 揖斐电株式会社 | 多层印刷配线板 |
| US7064427B2 (en) * | 2004-06-07 | 2006-06-20 | Industrial Technology Research Institute | Buried array capacitor and microelectronic structure incorporating the same |
| US7721238B2 (en) * | 2004-09-22 | 2010-05-18 | Digi International Inc. | Method and apparatus for configurable printed circuit board circuit layout pattern |
| US7335608B2 (en) * | 2004-09-22 | 2008-02-26 | Intel Corporation | Materials, structures and methods for microelectronic packaging |
| DE102004049485B3 (de) * | 2004-10-11 | 2005-12-01 | Siemens Ag | Elektrische Schaltung mit einer Mehrlagen-Leiterplatte |
| ATE524121T1 (de) | 2004-11-24 | 2011-09-15 | Abdou Samy | Vorrichtungen zur platzierung eines orthopädischen intervertebralen implantats |
| US20060131616A1 (en) * | 2004-12-21 | 2006-06-22 | Devaney Douglas E | Copperless flexible circuit |
| US7495887B2 (en) * | 2004-12-21 | 2009-02-24 | E.I. Du Pont De Nemours And Company | Capacitive devices, organic dielectric laminates, and printed wiring boards incorporating such devices, and methods of making thereof |
| US7541265B2 (en) * | 2005-01-10 | 2009-06-02 | Endicott Interconnect Technologies, Inc. | Capacitor material for use in circuitized substrates, circuitized substrate utilizing same, method of making said circuitized substrate, and information handling system utilizing said circuitized substrate |
| US7548432B2 (en) * | 2005-03-24 | 2009-06-16 | Agency For Science, Technology And Research | Embedded capacitor structure |
| JP4745697B2 (ja) * | 2005-03-29 | 2011-08-10 | 富士通セミコンダクター株式会社 | 複数の配線層を有する半導体回路の端子層設定方法、端子層設定プログラム、配線端子延長処理プログラム、および、その端子層を設定に用いられる端子延長用コンポーネント |
| US20060289976A1 (en) * | 2005-06-23 | 2006-12-28 | Intel Corporation | Pre-patterned thin film capacitor and method for embedding same in a package substrate |
| US7429510B2 (en) * | 2005-07-05 | 2008-09-30 | Endicott Interconnect Technologies, Inc. | Method of making a capacitive substrate using photoimageable dielectric for use as part of a larger circuitized substrate, method of making said circuitized substrate and method of making an information handling system including said circuitized substrate |
| US7485968B2 (en) | 2005-08-11 | 2009-02-03 | Ziptronix, Inc. | 3D IC method and device |
| TWI295098B (en) * | 2005-08-19 | 2008-03-21 | Via Tech Inc | Method for analyzing power distribution system and related techniques |
| US8870920B2 (en) * | 2005-10-07 | 2014-10-28 | M. Samy Abdou | Devices and methods for inter-vertebral orthopedic device placement |
| JP2007109825A (ja) * | 2005-10-12 | 2007-04-26 | Nec Corp | 多層配線基板、多層配線基板を用いた半導体装置及びそれらの製造方法 |
| TW200746940A (en) * | 2005-10-14 | 2007-12-16 | Ibiden Co Ltd | Printed wiring board |
| US7504706B2 (en) * | 2005-10-21 | 2009-03-17 | E. I. Du Pont De Nemours | Packaging having an array of embedded capacitors for power delivery and decoupling in the mid-frequency range and methods of forming thereof |
| US7705423B2 (en) | 2005-10-21 | 2010-04-27 | Georgia Tech Research Corporation | Device having an array of embedded capacitors for power delivery and decoupling of high speed input/output circuitry of an integrated circuit |
| US7576995B2 (en) * | 2005-11-04 | 2009-08-18 | Entorian Technologies, Lp | Flex circuit apparatus and method for adding capacitance while conserving circuit board surface area |
| US7919804B2 (en) * | 2005-11-08 | 2011-04-05 | Oracle America, Inc. | Power distribution for high-speed integrated circuits |
| US7670919B2 (en) * | 2005-12-30 | 2010-03-02 | Intel Corporation | Integrated capacitors in package-level structures, processes of making same, and systems containing same |
| TWI286049B (en) * | 2006-04-04 | 2007-08-21 | Advanced Semiconductor Eng | Circuit substrate |
| US20080068818A1 (en) * | 2006-09-19 | 2008-03-20 | Jinwoo Choi | Method and apparatus for providing ultra-wide band noise isolation in printed circuit boards |
| CN101166401B (zh) * | 2006-10-16 | 2011-11-30 | 辉达公司 | 用于在高速系统中放置多个负载的方法和系统 |
| US20080157267A1 (en) * | 2006-12-29 | 2008-07-03 | Texas Instruments | Stacked Printed Devices on a Carrier Substrate |
| US7646082B2 (en) * | 2007-05-22 | 2010-01-12 | International Business Machines Corporation | Multi-layer circuit substrate and method having improved transmission line integrity and increased routing density |
| TW200919676A (en) * | 2007-10-17 | 2009-05-01 | Phoenix Prec Technology Corp | Packaging substrate structure having capacitor embedded therein and method for manufacturing the same |
| US8564967B2 (en) * | 2007-12-03 | 2013-10-22 | Cda Processing Limited Liability Company | Device and method for reducing impedance |
| US20090156715A1 (en) * | 2007-12-14 | 2009-06-18 | Thomas Eugene Dueber | Epoxy compositions comprising at least one elastomer and methods relating thereto |
| US8395902B2 (en) * | 2008-05-21 | 2013-03-12 | International Business Machines Corporation | Modular chip stack and packaging technology with voltage segmentation, regulation, integrated decoupling capacitance and cooling structure and process |
| US20090296310A1 (en) * | 2008-06-03 | 2009-12-03 | Azuma Chikara | Chip capacitor precursors, packaged semiconductors, and assembly method for converting the precursors to capacitors |
| US8125766B2 (en) | 2008-06-13 | 2012-02-28 | Kemet Electronics Corporation | Concentrated capacitor assembly |
| KR20100002596A (ko) * | 2008-06-30 | 2010-01-07 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
| US20100012354A1 (en) * | 2008-07-14 | 2010-01-21 | Logan Brook Hedin | Thermally conductive polymer based printed circuit board |
| US7958789B2 (en) * | 2008-08-08 | 2011-06-14 | Tokai Rubber Industries, Ltd. | Capacitive sensor |
| US9893004B2 (en) | 2011-07-27 | 2018-02-13 | Broadpak Corporation | Semiconductor interposer integration |
| US10026720B2 (en) | 2015-05-20 | 2018-07-17 | Broadpak Corporation | Semiconductor structure and a method of making thereof |
| US8014166B2 (en) * | 2008-09-06 | 2011-09-06 | Broadpak Corporation | Stacking integrated circuits containing serializer and deserializer blocks using through silicon via |
| US9818680B2 (en) | 2011-07-27 | 2017-11-14 | Broadpak Corporation | Scalable semiconductor interposer integration |
| TWI347810B (en) * | 2008-10-03 | 2011-08-21 | Po Ju Chou | A method for manufacturing a flexible pcb and the structure of the flexible pcb |
| JP5304185B2 (ja) * | 2008-11-10 | 2013-10-02 | 富士通株式会社 | プリント配線板および電子装置 |
| TWI389279B (zh) * | 2009-01-23 | 2013-03-11 | 欣興電子股份有限公司 | 電路板結構及其製法 |
| KR101679896B1 (ko) | 2009-05-01 | 2016-11-25 | 쓰리엠 이노베이티브 프로퍼티즈 컴파니 | 수동 전기 물품 |
| US8764806B2 (en) | 2009-12-07 | 2014-07-01 | Samy Abdou | Devices and methods for minimally invasive spinal stabilization and instrumentation |
| US20110248283A1 (en) * | 2010-04-07 | 2011-10-13 | Jianjun Cao | Via structure of a semiconductor device and method for fabricating the same |
| US8572840B2 (en) | 2010-09-30 | 2013-11-05 | International Business Machines Corporation | Method of attaching an electronic module power supply |
| US8845728B1 (en) | 2011-09-23 | 2014-09-30 | Samy Abdou | Spinal fixation devices and methods of use |
| US8982577B1 (en) * | 2012-02-17 | 2015-03-17 | Amkor Technology, Inc. | Electronic component package having bleed channel structure and method |
| US20130226240A1 (en) | 2012-02-22 | 2013-08-29 | Samy Abdou | Spinous process fixation devices and methods of use |
| US9198767B2 (en) | 2012-08-28 | 2015-12-01 | Samy Abdou | Devices and methods for spinal stabilization and instrumentation |
| US9320617B2 (en) | 2012-10-22 | 2016-04-26 | Cogent Spine, LLC | Devices and methods for spinal stabilization and instrumentation |
| JP2014086651A (ja) * | 2012-10-26 | 2014-05-12 | Ibiden Co Ltd | プリント配線板及びプリント配線板の製造方法 |
| US20150001732A1 (en) * | 2013-06-27 | 2015-01-01 | Debendra Mallik | Silicon space transformer for ic packaging |
| US9565762B1 (en) * | 2013-12-06 | 2017-02-07 | Marvell Israel (M.I.S.L) Ltd. | Power delivery network in a printed circuit board structure |
| KR102071763B1 (ko) | 2014-02-21 | 2020-01-30 | 미쓰이금속광업주식회사 | 내장 캐패시터층 형성용 동장 적층판, 다층 프린트 배선판 및 다층 프린트 배선판의 제조 방법 |
| CN106257661B (zh) * | 2015-06-16 | 2019-03-05 | 华为技术有限公司 | 芯片封装载板、芯片和电路板 |
| US9953941B2 (en) | 2015-08-25 | 2018-04-24 | Invensas Bonding Technologies, Inc. | Conductive barrier direct hybrid bonding |
| US10857003B1 (en) | 2015-10-14 | 2020-12-08 | Samy Abdou | Devices and methods for vertebral stabilization |
| CN106658964A (zh) * | 2015-10-28 | 2017-05-10 | 碁鼎科技秦皇岛有限公司 | 电路板及其制作方法 |
| CN106658965A (zh) * | 2015-10-30 | 2017-05-10 | 碁鼎科技秦皇岛有限公司 | 载板及其制作方法 |
| WO2017134761A1 (ja) * | 2016-02-03 | 2017-08-10 | 富士通株式会社 | キャパシタ内蔵多層配線基板及びその製造方法 |
| US10225922B2 (en) | 2016-02-18 | 2019-03-05 | Cree, Inc. | PCB based semiconductor package with impedance matching network elements integrated therein |
| CN107665879A (zh) * | 2016-07-29 | 2018-02-06 | 奥特斯奥地利科技与系统技术有限公司 | 器件载体及包括所述器件载体的电子系统 |
| US10559476B2 (en) * | 2016-09-02 | 2020-02-11 | R&D Circuits, Inc. | Method and structure for a 3D wire block |
| US10973648B1 (en) | 2016-10-25 | 2021-04-13 | Samy Abdou | Devices and methods for vertebral bone realignment |
| US10744000B1 (en) | 2016-10-25 | 2020-08-18 | Samy Abdou | Devices and methods for vertebral bone realignment |
| US11521785B2 (en) | 2016-11-18 | 2022-12-06 | Hutchinson Technology Incorporated | High density coil design and process |
| WO2018094280A1 (en) | 2016-11-18 | 2018-05-24 | Hutchinson Technology Incorporated | High aspect ratio electroplated structures and anisotropic electroplating processes |
| WO2018100922A1 (ja) * | 2016-12-02 | 2018-06-07 | 株式会社村田製作所 | 多層配線基板 |
| FR3060255B1 (fr) * | 2016-12-12 | 2019-07-19 | Institut Vedecom | Procede d’integration de puces de puissance parallelisable et modules electroniques de puissance |
| KR200485246Y1 (ko) | 2017-03-09 | 2017-12-13 | (주) 고송이엔지 | 기판 필름 접착용 습식 자동 커팅 라미네이팅 장치 |
| KR102410197B1 (ko) * | 2017-06-13 | 2022-06-17 | 삼성전자주식회사 | 전송 손실을 줄이기 위한 회로 기판 및 이를 구비한 전자 장치 |
| US11172580B2 (en) * | 2017-07-24 | 2021-11-09 | Rosemount Aerospace Inc. | BGA component masking dam and a method of manufacturing with the BGA component masking dam |
| US10840205B2 (en) | 2017-09-24 | 2020-11-17 | Invensas Bonding Technologies, Inc. | Chemical mechanical polishing for hybrid bonding |
| US10217708B1 (en) * | 2017-12-18 | 2019-02-26 | Apple Inc. | High bandwidth routing for die to die interposer and on-chip applications |
| US11056348B2 (en) | 2018-04-05 | 2021-07-06 | Invensas Bonding Technologies, Inc. | Bonding surfaces for microelectronics |
| US11393779B2 (en) | 2018-06-13 | 2022-07-19 | Invensas Bonding Technologies, Inc. | Large metal pads over TSV |
| EP3807927A4 (en) | 2018-06-13 | 2022-02-23 | Invensas Bonding Technologies, Inc. | TSV AS PAD |
| US11011494B2 (en) | 2018-08-31 | 2021-05-18 | Invensas Bonding Technologies, Inc. | Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics |
| US11179248B2 (en) | 2018-10-02 | 2021-11-23 | Samy Abdou | Devices and methods for spinal implantation |
| US11158573B2 (en) | 2018-10-22 | 2021-10-26 | Invensas Bonding Technologies, Inc. | Interconnect structures |
| CN113396246B (zh) * | 2018-11-26 | 2025-08-26 | 哈钦森技术股份有限公司 | 电气装置和线圈 |
| TWI713984B (zh) * | 2019-01-28 | 2020-12-21 | 和碩聯合科技股份有限公司 | 計算導體阻抗的方法 |
| CN111799242A (zh) * | 2019-04-09 | 2020-10-20 | 矽品精密工业股份有限公司 | 封装堆叠结构及其制法与载板组件 |
| CN111799182A (zh) * | 2019-04-09 | 2020-10-20 | 矽品精密工业股份有限公司 | 封装堆叠结构及其制法 |
| CN110600440B (zh) * | 2019-05-13 | 2021-12-14 | 华为技术有限公司 | 一种埋入式封装结构及其制备方法、终端 |
| US20200395283A1 (en) * | 2019-06-17 | 2020-12-17 | Western Digital Technologies, Inc. | Return path cavity for single ended signal via |
| US11134575B2 (en) | 2019-09-30 | 2021-09-28 | Gentherm Gmbh | Dual conductor laminated substrate |
| CN110729265B (zh) * | 2019-10-21 | 2021-08-24 | 青岛海信宽带多媒体技术有限公司 | 一种光模块及光网络装置 |
| EP3855483A1 (en) * | 2020-01-21 | 2021-07-28 | Murata Manufacturing Co., Ltd. | Through-interposer connections using blind vias |
| US11264357B1 (en) | 2020-10-20 | 2022-03-01 | Invensas Corporation | Mixed exposure for large die |
| CN112672490B (zh) * | 2020-12-01 | 2022-09-30 | 吉安满坤科技股份有限公司 | 用于5g终端网卡的多层电路板制备方法及其5g网卡 |
| US12120811B2 (en) * | 2020-12-23 | 2024-10-15 | Intel Corporation | Multi-dielectric printed circuit board |
| EP4268273A4 (en) | 2020-12-28 | 2024-10-23 | Adeia Semiconductor Bonding Technologies Inc. | Structures with through-substrate vias and methods for forming the same |
| WO2022147430A1 (en) | 2020-12-28 | 2022-07-07 | Invensas Bonding Technologies, Inc. | Structures with through-substrate vias and methods for forming the same |
| KR102798570B1 (ko) * | 2021-02-03 | 2025-04-18 | 에스케이하이닉스 주식회사 | Dram용 커패시터, 이를 포함하는 dram 및 이들의 제조 방법 |
| EP4081005A1 (en) | 2021-04-23 | 2022-10-26 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Component carrier |
| US11764077B2 (en) * | 2021-07-23 | 2023-09-19 | Innolux Corporation | Composite layer circuit element and manufacturing method thereof |
| WO2023074484A1 (ja) * | 2021-10-26 | 2023-05-04 | 三菱瓦斯化学株式会社 | 樹脂組成物、プリプレグ、樹脂シート、積層板、金属箔張積層板、及びプリント配線板 |
| CN114980498B (zh) * | 2022-05-09 | 2024-04-02 | 江西福昌发电路科技有限公司 | 一种高密度互连印制板及其加工方法 |
| WO2024233047A1 (en) * | 2023-05-10 | 2024-11-14 | KYOCERA AVX Components Corporation | Thick film single layer capacitor |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5635767A (en) * | 1995-06-02 | 1997-06-03 | Motorola, Inc. | Semiconductor device having built-in high frequency bypass capacitor |
| US5912809A (en) * | 1997-01-21 | 1999-06-15 | Dell Usa, L.P. | Printed circuit board (PCB) including channeled capacitive plane structure |
| US6143401A (en) * | 1996-11-08 | 2000-11-07 | W. L. Gore & Associates, Inc. | Electronic chip package |
| US6203891B1 (en) * | 1996-11-08 | 2001-03-20 | W. L. Gore & Associates, Inc. | Multiple frequency processing to minimize manufacturing variability of high aspect ratio micro through-vias |
Family Cites Families (28)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5261153A (en) * | 1992-04-06 | 1993-11-16 | Zycon Corporation | In situ method for forming a capacitive PCB |
| US5633785A (en) * | 1994-12-30 | 1997-05-27 | University Of Southern California | Integrated circuit component package with integral passive component |
| DE19602822C2 (de) * | 1996-01-26 | 1998-02-19 | Siemens Ag | Kontaktfeder |
| US5831935A (en) * | 1996-03-05 | 1998-11-03 | Chevron U.S.A. Inc. | Method for geophysical processing and interpretation using seismic trace difference for analysis and display |
| EP0797084B1 (de) * | 1996-03-23 | 2001-01-17 | Endress + Hauser GmbH + Co. | Verfahren zum Herstellen von kapazitiven, in Nullpunkt-Langzeit-Fehlerklassen sortierten Keramik-Absolutdruck-Sensoren |
| US5745334A (en) * | 1996-03-25 | 1998-04-28 | International Business Machines Corporation | Capacitor formed within printed circuit board |
| US5731047A (en) * | 1996-11-08 | 1998-03-24 | W.L. Gore & Associates, Inc. | Multiple frequency processing to improve electrical resistivity of blind micro-vias |
| WO1998020557A1 (en) * | 1996-11-08 | 1998-05-14 | W.L. Gore & Associates, Inc. | Method for reducing via inductance in an electronic assembly and device |
| US5900312A (en) * | 1996-11-08 | 1999-05-04 | W. L. Gore & Associates, Inc. | Integrated circuit chip package assembly |
| US5879786A (en) * | 1996-11-08 | 1999-03-09 | W. L. Gore & Associates, Inc. | Constraining ring for use in electronic packaging |
| US5888631A (en) * | 1996-11-08 | 1999-03-30 | W. L. Gore & Associates, Inc. | Method for minimizing warp in the production of electronic assemblies |
| US5879787A (en) * | 1996-11-08 | 1999-03-09 | W. L. Gore & Associates, Inc. | Method and apparatus for improving wireability in chip modules |
| US5838063A (en) * | 1996-11-08 | 1998-11-17 | W. L. Gore & Associates | Method of increasing package reliability using package lids with plane CTE gradients |
| WO1998020533A2 (en) * | 1996-11-08 | 1998-05-14 | W.L. Gore & Associates, Inc. | Method for using photoabsorptive coatings to enhance both blind and through micro-via entrance quality |
| US5888630A (en) * | 1996-11-08 | 1999-03-30 | W. L. Gore & Associates, Inc. | Apparatus and method for unit area composition control to minimize warp in an integrated circuit chip package assembly |
| EP0889096B1 (en) | 1997-07-04 | 2002-09-11 | Hitachi Chemical Company, Ltd. | Modified cyanate ester group curable resin composition, and varnish, prepreg, metal clad laminated board, film, printed circuit board, and multilayered circuit board using the same |
| WO1999021224A1 (en) * | 1997-10-17 | 1999-04-29 | Ibiden Co., Ltd. | Package substrate |
| US5972231A (en) * | 1997-10-31 | 1999-10-26 | Ncr Corporation | Imbedded PCB AC coupling capacitors for high data rate signal transfer |
| US6608760B2 (en) | 1998-05-04 | 2003-08-19 | Tpl, Inc. | Dielectric material including particulate filler |
| US6215649B1 (en) * | 1998-11-05 | 2001-04-10 | International Business Machines Corporation | Printed circuit board capacitor structure and method |
| US6333857B1 (en) * | 1998-12-25 | 2001-12-25 | Ngk Spark Plug Co., Ltd. | Printing wiring board, core substrate, and method for fabricating the core substrate |
| JP3635219B2 (ja) * | 1999-03-11 | 2005-04-06 | 新光電気工業株式会社 | 半導体装置用多層基板及びその製造方法 |
| EP1771050B1 (en) * | 1999-09-02 | 2011-06-15 | Ibiden Co., Ltd. | Printed circuit board and method of manufacturing printed circuit board |
| JP3489729B2 (ja) | 1999-11-19 | 2004-01-26 | 株式会社村田製作所 | 積層コンデンサ、配線基板、デカップリング回路および高周波回路 |
| US6370013B1 (en) * | 1999-11-30 | 2002-04-09 | Kyocera Corporation | Electric element incorporating wiring board |
| JP3585796B2 (ja) * | 1999-12-17 | 2004-11-04 | 新光電気工業株式会社 | 多層配線基板の製造方法、及び半導体装置 |
| US6407929B1 (en) * | 2000-06-29 | 2002-06-18 | Intel Corporation | Electronic package having embedded capacitors and method of fabrication therefor |
| US6388207B1 (en) * | 2000-12-29 | 2002-05-14 | Intel Corporation | Electronic assembly with trench structures and methods of manufacture |
-
2002
- 2002-07-19 US US10/199,926 patent/US6847527B2/en not_active Expired - Lifetime
- 2002-08-22 EP EP02761469A patent/EP1419528B1/en not_active Expired - Lifetime
- 2002-08-22 DK DK02761469T patent/DK1419528T3/da active
- 2002-08-22 JP JP2003523005A patent/JP2005501415A/ja active Pending
- 2002-08-22 CN CN02816537A patent/CN100578774C/zh not_active Expired - Fee Related
- 2002-08-22 WO PCT/US2002/026756 patent/WO2003019656A2/en not_active Ceased
- 2002-08-22 AU AU2002326733A patent/AU2002326733A1/en not_active Abandoned
- 2002-08-22 AT AT02761469T patent/ATE343222T1/de not_active IP Right Cessation
- 2002-08-22 CA CA002456769A patent/CA2456769A1/en not_active Abandoned
- 2002-08-22 DE DE60215518T patent/DE60215518T2/de not_active Expired - Fee Related
- 2002-08-22 KR KR1020047002631A patent/KR100896548B1/ko not_active Expired - Fee Related
- 2002-08-23 TW TW091119135A patent/TW559955B/zh not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5635767A (en) * | 1995-06-02 | 1997-06-03 | Motorola, Inc. | Semiconductor device having built-in high frequency bypass capacitor |
| US6143401A (en) * | 1996-11-08 | 2000-11-07 | W. L. Gore & Associates, Inc. | Electronic chip package |
| US6203891B1 (en) * | 1996-11-08 | 2001-03-20 | W. L. Gore & Associates, Inc. | Multiple frequency processing to minimize manufacturing variability of high aspect ratio micro through-vias |
| US5912809A (en) * | 1997-01-21 | 1999-06-15 | Dell Usa, L.P. | Printed circuit board (PCB) including channeled capacitive plane structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1547772A (zh) | 2004-11-17 |
| EP1419528B1 (en) | 2006-10-18 |
| AU2002326733A1 (en) | 2003-03-10 |
| CA2456769A1 (en) | 2003-03-06 |
| EP1419528A2 (en) | 2004-05-19 |
| US6847527B2 (en) | 2005-01-25 |
| US20040170006A9 (en) | 2004-09-02 |
| DE60215518D1 (de) | 2006-11-30 |
| TW559955B (en) | 2003-11-01 |
| WO2003019656A3 (en) | 2003-11-20 |
| DE60215518T2 (de) | 2007-08-30 |
| DK1419528T3 (da) | 2007-02-19 |
| JP2005501415A (ja) | 2005-01-13 |
| KR100896548B1 (ko) | 2009-05-07 |
| WO2003019656A2 (en) | 2003-03-06 |
| ATE343222T1 (de) | 2006-11-15 |
| US20040012938A1 (en) | 2004-01-22 |
| KR20040040443A (ko) | 2004-05-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100578774C (zh) | 具有降低的功率分配阻抗的互连模块及其制造方法 | |
| CN1096222C (zh) | 印刷电路多层组件及其制作方法 | |
| JP4079699B2 (ja) | 多層配線回路基板 | |
| US6281448B1 (en) | Printed circuit board and electronic components | |
| JP4392157B2 (ja) | 配線板用シート材及びその製造方法、並びに多層板及びその製造方法 | |
| US5628852A (en) | Method for manufacturing a polyimide multilayer wiring substrate | |
| US8736064B2 (en) | Structure and method of making interconnect element having metal traces embedded in surface of dielectric | |
| JPH1154927A (ja) | 複合配線基板、フレキシブル基板、半導体装置、および複合配線基板の製造方法 | |
| JP2002261449A (ja) | 部品内蔵モジュール及びその製造方法 | |
| KR20030088357A (ko) | 금속 코어 기판 및 그 제조 방법 | |
| JP3956851B2 (ja) | 受動素子内蔵基板及びその製造方法 | |
| WO2000032021A1 (en) | Printed circuit assembly having locally enhanced wiring density | |
| US7757394B2 (en) | Multilayer wiring board | |
| JPH07263828A (ja) | プリント配線基板及びその製造方法 | |
| US6586687B2 (en) | Printed wiring board with high density inner layer structure | |
| JPH0794868A (ja) | 多層配線基板及びその製造方法 | |
| KR20070068445A (ko) | 유전체의 표면에 매입된 금속 트레이스들을 갖는 상호접속소자를 제조하는 구조와 방법 | |
| JP2751678B2 (ja) | ポリイミド多層配線基板およびその製造方法 | |
| EP1755161A2 (en) | Interconnect module with reduced power distribution impedance | |
| JP2003229661A (ja) | 配線基板およびその製造方法 | |
| JP2712936B2 (ja) | ポリイミド多層配線基板およびその製造方法 | |
| JP2008529283A (ja) | 誘電体の表面に埋め込まれた金属トレースを有する相互接続要素を作る構成および方法 | |
| JPWO1997019579A1 (ja) | 多層配線基板、多層配線基板のプレハブ素材、多層配線基板の製造方法、電子部品、電子部品パッケージおよび導電性ピラーの形成方法 | |
| JPH1126052A (ja) | 厚さ方向導電シート及びその製造方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100106 Termination date: 20180822 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |