CN100479161C - 半导体器件以及制造半导体器件的方法 - Google Patents

半导体器件以及制造半导体器件的方法 Download PDF

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CN100479161C
CN100479161C CN200610002411.XA CN200610002411A CN100479161C CN 100479161 C CN100479161 C CN 100479161C CN 200610002411 A CN200610002411 A CN 200610002411A CN 100479161 C CN100479161 C CN 100479161C
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semiconductor
crystal orientation
semiconductor layer
transistor
insulating barrier
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CN1848431A (zh
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宋均镛
阎江
丹尼·P-C.·舒姆
阿洛艾斯·古特曼
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Infineon Technologies North America Corp
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Abstract

一种半导体器件，包括半导体主体，其包含具有第一晶向的半导体材料。第一晶体管在具有第一晶向的半导体材料中形成。绝缘层覆盖半导体主体的部分并且半导体层覆盖绝缘层。该半导体层具有第二晶向。第二晶体管在具有第二晶向的半导体层中形成。在优选实施方案中，半导体主体是(100)硅，第一晶体管是NMOS晶体管，半导体层是(110)硅并且第二晶体管是PMOS晶体管。

Description

半导体器件以及制造半导体器件的方法
技术领域
本发明一般地涉及半导体器件，尤其涉及一种具有混合取向衬底的半导体方法和器件。
背景技术
互补金属氧化物半导体(CMOS)是半导体器件制造方面的主导技术。CMOS器件包括n沟道(NMOS)和p沟道(PMOS)晶体管。在CMOS技术中，两种晶体管以互补的方式使用以形成电流门，其形成电气控制的有效方法。有利地，当不从一种状态切换到另一种状态时，CMOS晶体管使用非常少的功率。
已经知道载流子的迁移率依赖于许多因素，特别是晶片的表面。常规硅衬底典型地具有在(100)晶面上取向的表面。在该平面中，电子的迁移率高于其它晶面中，因此，在具有(100)平面的半导体衬底上形成的n沟道FET的源极-漏极电流提供最大的电流。但是，空穴的迁移率在(100)平面中不是最优的，因此，在具有(100)平面的半导体衬底上形成的p沟道FET的源极-漏极电流不可避免地小。因此，p沟道FET不能具有期望的特性，即使n沟道FET表现出良好的特性。空穴迁移率可以增强，特别是在高强度电场处，如果p沟道FET在(110)平面上形成。
美国专利No.5,384,473公开一种包含具有不同取向的元件形成表面的半导体主体。半导体主体以这种方式构造，即(100)平面的第一半导体衬底层压到(110)平面的第二半导体衬底。至少一个开口制造在第一半导体衬底中以暴露第二半导体衬底。n沟道晶体管可以在第一半导体衬底中形成，同时p沟道晶体管在第二半导体衬底中形成。
美国专利No.6,815,277公开在同一衬底上形成的FinFET，其对于FET电流通道使用各种晶面以优化迁移率和/或减小迁移率。衬底具有在使得通道的随后晶面可以利用的第一晶面上取向的表面。第一晶体管也提供有第一鳍体(fin body)。第一鳍体具有形成第一通道的侧壁，该侧壁在第二晶面上取向以提供第一载流子迁移率。第二晶体管也提供有第二鳍体。第二鳍体具有形成第二通道的侧壁，该侧壁在第三晶面上取向以提供不同于第一载流子迁移率的第二载流子迁移率。
Yang等人标题为“High Performance CMOS Fabricated onHybrid Substrate With Different Crystal Orientations(在具有不同晶向的混合衬底上制造的高性能CMOS)”，2003 IEDM，pp.18.7.1-18.7.4的论文公开一种通过晶片压焊和选择性外延使用具有不同晶向的混合硅衬底的高性能CMOS的结构和技术。该类型的混合取向衬底(MOS)是一种通过使用(110)衬底增强PMOS性能同时通过使用(100)衬底维持NMOS性能的新的优秀技术。混合取向衬底的一个挑战在于使得衬底的(110)部分与衬底的(100)部分隔离同时形成与随后浅槽隔离(STI)的良好对齐，特别是对于45nm以下的技术。
发明内容
这些和其它问题通常由本发明的优选实施方案解决或防止其发生，并且技术优点通常实现，其提供一种在同一过程模组中形成混合取向衬底和隔离的方法。
根据本发明的优选实施方案，一种半导体器件包括具有第一晶向的半导体材料的半导体主体。第一晶体管在具有第一晶向的半导体材料中形成。绝缘层覆盖半导体主体的部分且半导体层覆盖绝缘层。半导体层具有第二晶向。第二晶体管在具有第二晶向的半导体层中形成。在优选实施方案中，半导体主体是(100)硅，第一晶体管是NMOS晶体管，半导体层是(110)硅并且第二晶体管是PMOS晶体管。
根据本发明的另一种实施方案，一种制造半导体器件的方法包括提供包括用具有第一晶向的半导体材料制成的半导体主体的晶片。绝缘层覆盖半导体衬底并且用具有第二晶向的半导体材料制成的半导体层覆盖绝缘层。半导体层和绝缘层的部分被去除以暴露半导体主体的一部分。第一导电型(例如n沟道)的第一晶体管在具有第一晶向的半导体材料中形成，而第二导电型(例如p沟道)的第二晶体管在具有第二晶向的半导体材料中形成。
在另一种实施方案中，一种形成半导体器件的方法再次包括提供包括具有第一晶向的半导体衬底，半导体衬底上的绝缘层，以及绝缘层上具有第二晶向的半导体层的晶片。半导体层的一部分被去除以暴露绝缘层的一部分。绝缘材料在晶片上形成。绝缘材料的部分被去除以暴露半导体层的部分，并且绝缘材料和绝缘层的部分被去除以暴露半导体衬底的部分。具有第一晶向的半导体材料在半导体衬底的暴露部分上外延地生长，并且具有第二晶向的半导体材料在半导体层的暴露部分上外延地生长。
本发明提供一种半导体器件，包括：半导体主体，包含具有第一晶向的半导体材料；第一晶体管，在具有第一晶向的半导体材料中形成；绝缘层，覆盖半导体主体的多个部分；覆盖绝缘层的半导体层，该半导体层具有第二晶向；外延生长的半导体区域，覆盖半导体层，该半导体区域具有第二晶向；第二晶体管，在所述半导体区域中形成；以及隔离区域，其位于半导体主体上并且横向地位于第一晶体管与第二晶体管之间；其中所述半导体区域具有小于半导体层横向尺寸的横向尺寸，使得半导体层的一部分延伸到半导体区域外部，其中隔离区域覆盖延伸到半导体区域外部的半导体层的部分。
本发明还提供一种半导体器件，包括：半导体主体，包含具有第一晶向的半导体材料；第一晶体管，在具有第一晶向的半导体材料中形成；绝缘层，覆盖半导体主体的多个部分；覆盖绝缘层的半导体层，该半导体层具有第二晶向；第二晶体管，在具有第二晶向的外延生长半导体区域中形成；以及隔离区域，位于第一晶体管与第二晶体管之间的绝缘层上，其中横向定位隔离区域，使得整个隔离区域位于绝缘层之上。
本发明还提供一种制造半导体器件的方法，该方法包括：提供晶片，该晶片包括用具有第一晶向的半导体材料制成的半导体主体、半导体衬底上的绝缘层、以及绝缘层上用具有第二晶向的半导体材料制成的半导体层；去除半导体层和绝缘层的多个部分以暴露半导体主体的多个部分；在半导体主体的暴露各部分上外延地生长具有第一晶向的半导体材料，并且在半导体层的各部分上外延地生长具有第二晶向的半导体材料；在具有第一晶向的半导体材料中形成第一导电型的第一晶体管；在具有第二晶向的半导体材料中形成第二导电型的第二晶体管；在半导体主体上在第一晶体管与第二晶体管之间形成隔离区域；其中外延生长的半导体材料具有小于半导体层横向尺寸的横向尺寸，使得半导体层的一部分延伸到半导体区域外部，其中隔离区域覆盖延伸到半导体区域外部的半导体层的部分。
本发明还提供一种形成半导体器件的方法，该方法包括：提供包括具有第一晶向的半导体衬底、半导体衬底上的绝缘层、以及绝缘层上具有第二晶向的半导体层的晶片；去除半导体层的一部分以暴露绝缘层的一部分；在晶片上形成绝缘材料；去除绝缘材料的多个部分以暴露半导体层的多个部分；去除绝缘材料和绝缘层的多个部分以暴露半导体衬底的多个部分；以及在半导体衬底的暴露部分上外延地生长具有第一晶向的半导体材料，并且在半导体层的暴露部分上外延地生长具有第二晶向的半导体材料。
本发明优选实施方案的优点是包括沟槽填补的典型浅槽隔离过程模组的消除。因为有效半导体区域使用外延过程形成，该过程模组消除。换句话说，在优选实施方案中，隔离区域在有效半导体区域形成之前形成。
本发明优选实施方案的另一个优点是仅需要两个掩模并且STI沟槽定义掩模被免除。因为有效区域典型地大于STI，该掩模的临界尺寸放松。此外，总体过程步骤从常规过程中显著减少。过程步骤和复杂度的任何减少将导致成本减少。
附图说明
为了更完整地理解本发明及其优点，现在参考结合附随附图而进行的下面的描述，其中：
图1是优选实施方案半导体器件；
图2-16是显示优选实施方案器件的制造的各个阶段的横截面；以及
图17是备选实施方案器件。
具体实施方式
当前优选实施方案的创造和使用在下面详细讨论。但是，应当理解，本发明提供许多可适用的发明概念，其可以在各种具体环境中实施。讨论的具体实施方案仅说明创造和使用本发明的具体方法，而不限制本发明的范围。
本发明将在具体环境，也就是用来优化CMOS器件性能的混合晶向硅衬底中关于优选实施方案来描述。但是，本发明也可以适用于其它半导体器件例如双极型和BiCMOS以及其它半导体例如硅锗。
本发明的典型结构将关于图1来描述。制造该结构的工艺流程然后将参考图2-16来描述。备选结构在图17中显示。
首先参考图1，半导体器件10包括第一导电型的第一晶体管12和第二导电型的第二晶体管14，16。为了增强性能，第一晶体管在具有第一晶向的半导体材料中形成，而第二晶体管14和16在具有第二晶向的半导体材料中形成。在优选实施方案中，第一晶体管12是在(100)硅中形成的n沟道场效应晶体管(FET)，而第二晶体管14和16是在(110)硅中形成的p沟道FET。在备选实施方案中，(100)取向半导体和(110)取向半导体的位置可以彼此转换。换句话说，主体衬底18取向可以是(100)或(110)。
为了实现不同的晶向，n沟道晶体管12在衬底18的部分20中形成。如下面将描述的，所述部分20优选地是外延生长的半导体材料，该材料具有与衬底18的晶向对齐的晶向。在优选实施方案中，衬底18是(100)单晶硅衬底。因此，半导体20也是(100)单晶硅并且可以看作衬底18的一部分。
晶体管14和16在半导体层22的部分中形成。半导体层22优选地(虽然不一定)具有与半导体材料20不同的晶向。在优选实施方案中，半导体层是(110)硅(而半导体主体20是(100)硅)。在另一种实施方案中，半导体层是(100)硅而半导体主体20是(110)硅。
半导体层22由绝缘层24与衬底18隔离。绝缘24优选地是氧化物层，有时称作隐埋氧化物。在其它实施方案中，其它绝缘材料例如氮化物、氮氧化合物和高k介电材料可以备选地使用。在说明的实施方案中，绝缘层24具有半导体材料20延伸通过的开口。
半导体区域20由隔离区域26与半导体区域22隔离。隔离区域26优选地由氧化物(例如二氧化硅)形成，但是其它材料可以备选地使用。因为用来形成隔离区域26的过程，其将在下面更详细地描述，隔离区域可以具有与器件的最小光刻尺寸一样小的水平尺寸。
形成本发明结构的一种优选实施方案过程现在将参考图2-16来描述。这些图说明一种具体的过程。但是，应当理解，许多变化和更改可以引入工艺流程中。虽然图参考具体的材料(例如(100)Si和(110)Si)，同样应当理解，这里讨论或另外由本领域技术人员认可的其它材料可以备选地使用。
首先参考图2，绝缘体上硅(SOI)晶片8被提供。SOI晶片8包括衬底18，覆盖衬底18和半导体层22的绝缘层24。在优选实施方案中，衬底18包括(100)体硅衬底。在其它实施方案中，衬底18可以包括具有不同晶向，例如(110)或(111)的硅，或者不同的半导体材料，例如硅锗，砷化镓。
绝缘层24和半导体层22可以各种方法形成。例如，绝缘层24可以在衬底18的表面上沉积或生长，并且半导体层22可以使用特定接合技术与绝缘层24接合。例如，半导体层22(以及可能地绝缘层24)接合或层压到衬底18。例如，包括硅层22的供体晶片可以接合到包括绝缘体24的目标晶片18。在晶片隔离过程，例如SmartcutTM过程期间，一个氧化硅晶片中的分割面由紧靠氧化物层下面的氢注入确定。供体晶片到目标晶片的接合以及预确定平面处的随后隔离导致在绝缘层24以及下面硅衬底18的上面剩余的一薄层单晶硅22。
图2中说明的衬底也可以例如购买。例如，具有两种不同取向的接合晶片可以从公司例如SEH America of Vancouver，Washington购买。
参考图3，硬掩模层28在半导体层22上形成。在优选实施方案中，硬掩模层28是由四乙基原硅酸盐的分解形成的氧化物层，因此经常称作TEOS层。TEOS层28优选地形成为大约50nm～500nm的厚度，优选地大约200nm。其它材料可以用于硬掩模。例如，硬掩模可以是氮化硅，氮氧化硅，硼掺杂氧化物(BSG)或硼磷掺杂氧化物(BPSG)。硬掩模28可以是一个单层或多层。
接下来参考图4，抗蚀剂层30在硬掩模层28上形成。抗蚀剂层30可以是在标准光刻处理中使用的任何光致抗蚀剂。同样如图中所示，抗蚀剂30构成图案以暴露硬掩模层28的一部分。硬掩模层28的暴露部分然后可以去除以暴露半导体层22的一部分。
图5说明光致抗蚀剂30已经除去之后的晶片。
参考图6，半导体层22的暴露部分使用硬掩模层28的剩余部分作为掩模来去除。该去除可以通过各向异性蚀刻来进行。在没有说明的实施方案中，硬掩模层28可以用光致抗蚀剂取代。
如图6中所示，硬掩模层28可以在硅层22的部分去除期间变薄。图7显示硬掩模层28的任何剩余部分可以去除。该去除可以例如通过等离子蚀刻来执行。
接下来参考图8和9，绝缘材料34在半导体层22的部分去除的位置形成。在优选实施方案中，绝缘层32沉积(图8)并且平面化以基本上与半导体层22的顶面共面。例如，氧化物层可以使用高密度等离子(HDP)过程继之以化学机械抛光(CMP)步骤来沉积。在备选实施方案中，绝缘材料32可以是由不同的过程形成的氧化物或者不同的材料例如氮化物或掺杂玻璃(例如氟化石英玻璃)。
现在参考图10，绝缘层36在晶片上沉积。在优选实施方案中，绝缘层36是与绝缘体34相同的材料，例如绝缘体34和36可以都是二氧化硅。作为实例，绝缘层36可以是HDP氧化物层(也就是使用高密度等离子过程沉积的氧化物)。其它氧化物沉积过程可以备选地使用。在其它实施方案中，两层可以是不同的材料，例如上面列出的材料的组合。
图11-14说明隔离区域26的形成。(隔离区域26从绝缘区域34和36中形成，其重新编号以与图1相对应)。如图11中所示，抗蚀剂38在晶片上形成并构成图案以暴露覆盖半导体绝缘区22的隔离区域26的部分。隔离区域26的暴露部分然后可以去除，如图12中所示。
在抗蚀剂层38除去之后，第二抗蚀剂层40形成并构成图案以暴露衬底18上绝缘层24已经去除的位置处隔离区域26的部分。使用构成图案的抗蚀剂层40作为掩模，半导体衬底18被暴露，如图13中所示。图14说明抗蚀剂40已经除去的结构。
在备选实施方案中，单个抗蚀剂层可以构成图案以创造图11和13中所示的开口。该修改将节省一个掩模步骤。在该情况下，蚀刻停止层(没有显示)，例如氮化硅当隔离区域26是氧化物时，优选地在层22上形成以保护半导体，当蚀刻过程继续通过覆盖衬底18的隔离区域26的较厚部分时。一旦抗蚀剂被去除，图14的结构将获得。
接下来参考图15，半导体区域42和44分别使用半导体区域18和22作为种子层外延地生长。在优选实施方案中，硅区域42和44分别在硅主体18和22上生长。在该情况下，主体18和22的半导体材料与生长层42和44的半导体材料相同。但是，在其它实施方案中，并不需要这样。例如，为了形成应变半导体层，一层硅可以在硅锗主体18和/或22上生长，例如硅锗衬底或衬底上的硅锗层。在其它实例中，材料的其它组合是可能的。
在优选实施方案中，绝缘层36(参看图10；该层在图15中标记为26)形成为大约100nm～500nm的厚度，优选地大约350nm。在其它实施方案中，厚度可以更大(例如高达大于2000nm)或更薄(例如降至大约10nm)。硅区域42和44优选地生长到大约该相同的厚度。在次优实施方案中，硅42/44可以生长到隔离区域26的水平之上，另外的绝缘体沉积(没有显示)可以执行以填补隔离区域26上的区域。
现在参考图16，硅区域42和44的顶面被平面化以基本上与隔离区域26的顶面成为平面。保持在隔离区域26之间的硅层20和22的部分可以用作有效区域。虽然优选地，有效区域20/22和隔离区域26共面，但是这并不是必需的。平面化步骤优选地使用化学机械抛光(CMP)执行。其它平面化技术，例如回蚀，可以备选地使用。在备选实施方案中，热氧化物(没有显示)可以在有效区域20/22上生长，然后去除以获得新鲜的硅表面。其它备选方案包括后热退火以去除瑕疵并提高顶部硅层质量。
图16的结构现在可以用作器件制造的开始点。例如，晶体管12和14可以如图1中所示形成。其它组件例如二极管，电阻器，电容器也可以制造以形成期望电路。注意，图16的结构与图1的结构不同。这些差异被认为说明本发明可以在多种环境中适用。
备选实施方案在图17中说明。在图17中，有效区域的一个20由SOI晶片形成，而其它区域22在覆盖SOI的半导体层上形成。该实施方案作为可以由本发明包括的许多备选方案的实例而呈现。
虽然本发明已经参考说明实施方案来描述，该描述并不打算在限制的意义上构造。说明实施方案的各种修改和组合，以及本发明的其它实施方案，当参考描述时对本领域技术人员显然。因此，意图附加权利要求包括任何这种修改或实施方案。

Claims (21)

1.一种半导体器件，包括：
半导体主体，包含具有第一晶向的半导体材料；
第一晶体管，在具有第一晶向的半导体材料中形成；
绝缘层，覆盖半导体主体的多个部分；
覆盖绝缘层的半导体层，该半导体层具有第二晶向；
外延生长的半导体区域，覆盖半导体层，该半导体区域具有第二晶向；
第二晶体管，在所述半导体区域中形成；以及
隔离区域，其位于半导体主体上并且横向地位于第一晶体管与第二晶体管之间；
其中所述半导体区域具有小于半导体层横向尺寸的横向尺寸，使得半导体层的一部分延伸到半导体区域外部，其中隔离区域覆盖延伸到半导体区域外部的半导体层的部分。
2.根据权利要求1的器件，其中半导体主体包括体单晶硅衬底。
3.根据权利要求2的器件，其中硅衬底包括(100)硅，并且其中半导体层包括(110)硅。
4.根据权利要求1的器件，其中：
半导体主体包括(100)硅；
第一晶体管包括n沟道场效应晶体管；
半导体层包括(110)硅；以及
第二晶体管包括p沟道场效应晶体管。
5.根据权利要求1的器件，其中隔离区域具有与器件的最小光刻尺寸一样小的水平尺寸。
6.一种半导体器件，包括：
半导体主体，包含具有第一晶向的半导体材料；
第一晶体管，在具有第一晶向的半导体材料中形成；
绝缘层，覆盖半导体主体的多个部分；
覆盖绝缘层的半导体层，该半导体层具有第二晶向；
第二晶体管，在具有第二晶向的外延生长半导体区域中形成；以及
隔离区域，位于第一晶体管与第二晶体管之间的绝缘层上，其中横向定位隔离区域，使得整个隔离区域位于绝缘层之上。
7.根据权利要求6的器件，其中第一晶体管在半导体主体的外延生长部分中形成，并且其中第二晶体管在半导体层的外延生长部分中形成。
8.根据权利要求7的器件，其中隔离区域的一部分覆盖半导体层的一部分。
9.根据权利要求6的器件，其中：
半导体主体包括(100)硅；
第一晶体管包括n沟道场效应晶体管；
半导体层包括(110)硅；以及
第二晶体管包括p沟道场效应晶体管。
10.根据权利要求6的器件，其中隔离区域具有与器件的最小光刻尺寸一样小的水平尺寸。
11.一种制造半导体器件的方法，该方法包括：
提供晶片，该晶片包括用具有第一晶向的半导体材料制成的半导体主体、半导体主体上的绝缘层、以及绝缘层上用具有第二晶向的半导体材料制成的半导体层；
去除半导体层和绝缘层的多个部分以暴露半导体主体的多个部分；
在半导体主体的暴露各部分上外延地生长具有第一晶向的半导体材料，并且在半导体层的各部分上外延地生长具有第二晶向的半导体材料而形成具有第二晶向的半导体区域；
在具有第一晶向的半导体材料中形成第一导电型的第一晶体管；
在具有第二晶向的半导体区域中形成第二导电型的第二晶体管；
在半导体主体上在第一晶体管与第二晶体管之间形成隔离区域；
其中半导体区域具有小于半导体层横向尺寸的横向尺寸，使得半导体层的一部分延伸到半导体区域外部，其中隔离区域覆盖延伸到半导体区域外部的半导体层的部分。
12.根据权利要求11的方法，其中：
具有第一晶向的半导体材料包括(100)硅；
形成第一晶体管包括形成n沟道场效应晶体管；
具有第二晶向的材料包括(110)硅；以及
形成第二晶体管包括形成p沟道场效应晶体管。
13.根据权利要求12的方法，其中隔离区域在外延生长具有第一晶向的半导体材料和形成具有第二晶向的半导体区域之前形成。
14.根据权利要求11的方法，其中提供晶片包括：
提供半导体主体，该半导体主体包含具有第一晶向的半导体材料；
在半导体主体上形成绝缘层；
在绝缘层上形成半导体层，该半导体层包含具有第二晶向的半导体材料。
15.根据权利要求14的方法，其中绝缘层和半导体层由晶片接合工艺形成。
16.一种形成半导体器件的方法，该方法包括：
提供包括具有第一晶向的半导体衬底、半导体衬底上的绝缘层、以及绝缘层上具有第二晶向的半导体层的晶片；
去除半导体层的一部分以暴露绝缘层的一部分；
在晶片上形成绝缘材料；
去除绝缘材料的多个部分以暴露半导体层的多个部分；
去除绝缘材料和绝缘层的多个部分以暴露半导体衬底的多个部分；以及
在半导体衬底的暴露部分上外延地生长具有第一晶向的半导体材料，并且在半导体层的暴露部分上外延地生长具有第二晶向的半导体材料。
17.根据权利要求16的方法，其中形成绝缘材料包括在绝缘层的暴露部分上形成第一绝缘材料，该绝缘材料具有与半导体层的顶面共面的顶面，以及在第一绝缘材料上形成第二绝缘材料，该第二绝缘材料与第一绝缘材料相同或不同。
18.根据权利要求16的方法，其中去除绝缘材料的多个部分以暴露半导体层的多个部分包括执行第一掩模步骤，并且其中去除绝缘材料和绝缘层的多个部分以暴露半导体衬底的多个部分包括执行第二掩模步骤。
19.根据权利要求16的方法，其中具有第一晶向的半导体衬底包括(100)硅衬底，并且其中具有第二晶向的半导体层包括(110)硅层。
20.根据权利要求19的方法，还包括在(100)硅中形成n沟道晶体管以及在(110)硅中形成p沟道晶体管。
21.根据权利要求16的方法，其中具有第一晶向的半导体衬底包括(110)硅衬底，并且其中具有第二晶向的半导体层包括(100)硅层。
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