CN100399506C - 具有低标准偏差的高值分裂多晶p电阻器 - Google Patents
具有低标准偏差的高值分裂多晶p电阻器 Download PDFInfo
- Publication number
- CN100399506C CN100399506C CNB2003801093855A CN200380109385A CN100399506C CN 100399506 C CN100399506 C CN 100399506C CN B2003801093855 A CNB2003801093855 A CN B2003801093855A CN 200380109385 A CN200380109385 A CN 200380109385A CN 100399506 C CN100399506 C CN 100399506C
- Authority
- CN
- China
- Prior art keywords
- resistor
- polysilicon
- high value
- layer
- polysilicon layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 93
- 229920005591 polysilicon Polymers 0.000 claims abstract description 91
- 238000000034 method Methods 0.000 claims abstract description 30
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 17
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 14
- 238000005516 engineering process Methods 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 10
- 238000000059 patterning Methods 0.000 claims description 10
- 230000007797 corrosion Effects 0.000 claims description 9
- 238000005260 corrosion Methods 0.000 claims description 9
- 238000005452 bending Methods 0.000 claims description 8
- 239000011248 coating agent Substances 0.000 claims description 7
- 238000000576 coating method Methods 0.000 claims description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 238000002347 injection Methods 0.000 claims description 5
- 239000007924 injection Substances 0.000 claims description 5
- 238000011065 in-situ storage Methods 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 claims 33
- 238000005137 deposition process Methods 0.000 claims 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 239000011241 protective layer Substances 0.000 claims 1
- 230000008021 deposition Effects 0.000 abstract description 5
- 239000007943 implant Substances 0.000 abstract 2
- 238000010276 construction Methods 0.000 description 6
- 239000000428 dust Substances 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 238000003475 lamination Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000009977 dual effect Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0635—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors and diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0802—Resistors only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
公开了一种由两层多晶硅构成的电阻器结构。该内禀器件采用顶层制成,该顶层或者是专门沉积的,或者作为已有工艺步骤如BiCMOS流程中的基体外延生长的一部分形成。该多晶层可以通过合适地设置注入剂量、或者通过原位掺杂方法而使其表面电阻较高(大于2000欧姆每平方)而制成。在本发明中,该层被设置成大约1000埃或更小的厚度。与较厚的层制成的电阻器相比,采用这样的厚度形成的这种电阻器已经表现出较好的电阻标准偏差。此外,按细长形式制成的实际的电阻器当在该形式中结合5段弯曲时表现出更好的电阻标准偏差。该电阻器端部由附加的底部多晶层以自对准的方式由已经是处理工序中一部分的沉积形成。最终的结果是内禀的电阻器本体由单个多晶层形成,而端部由两层产生。这些端部足够厚,使得可以向该结构中加入标准的硅化物和接触腐蚀处理,而不需特殊的处理。此外,可以向电阻器端部结合专门或已有的注入,以确保实现从多晶硅到硅化物或触点金属的欧姆接触。这些步骤可以产生一致的、低电阻的、欧姆端部接触的、以及大于2000欧姆每平方的内禀电阻的、容易制作的电阻器结构。
Description
技术领域
本发明涉及在半导体衬底上形成多晶硅电阻器的结构和工艺,并且,更具体地涉及双层多晶硅高值电阻器结构。
背景技术
与其它电路器件一起在同一晶片上形成高值多晶硅电阻器是困难的。一个原因是多晶硅层或多层的厚度由其它器件所需的特性来决定。例如,所沉积的多晶硅必须也形成有源器件的栅和/或发射极、低值电阻器和电容器极板。这需要典型地大于200纳米(nm)的厚度。
如图1所示,多晶硅电阻率是掺杂的非线性函数,其中电阻率在掺杂浓度增加时快速减小。注入的掺杂剂的浓度控制使得很难实现大于大约0.060欧姆厘米的电阻率。因为,随着掺杂浓度减小(比较图1中的点a和点b),电阻率随掺杂浓度的变化速率急剧增加,使得电阻率以及最终的电阻难以控制。这两方面的局限将实际的表面电阻限制成不高于2000欧姆每平方太多。因此,兆欧姆电阻器将消耗很多空间,并且将极大地增加管芯尺寸。
形成高值多晶硅电阻器的尝试已经使用离子注入和减小的多晶硅厚度,但成功有限。其它结构已经使用多层多晶硅。但是这些结构常常要求除对于同一晶片上的核心器件所需的那些步骤和工艺之外的许多额外的步骤和工艺,并且所得到的电阻器具有器件和工艺控制的限制。
在授予Dah-Chih Lin等人的美国专利6,211,031中描述了一种这样的尝试。该发明描述了一种使用两层的分裂或双值多晶硅工艺。第一层被沉积并图案化,以露出下面的电介质衬底。第二多晶硅层被沉积在第一层和电介质的上方。形成两个平行的电阻器。如果多晶硅电阻率太高,则电阻器端部接触结构将形成整流接触。其中没有建议或公开提供低欧姆端部结构的处理。腐蚀在薄多晶硅层上终止而不穿透的接触孔的工艺也是困难的。
在授予Yu-MingTsui等人的美国专利6,054,359中可发现另一种方法。该专利描述了薄多晶硅层,在该较薄层上有较厚多晶硅层。薄层被原位掺杂,而较厚层未被掺杂。两层的组合形成了电阻器。这种特殊的发明尤其受到形成所形成的电阻器的端部结构一部分的未掺杂层的损害。结果是电阻器的较高欧姆端部接触。
现有技术没有涉及向薄多晶硅电阻器中集成硅化物或金属接触部的技术问题。在硅化物的情形中,形成反应将消耗薄多晶层的大部分,如果不是全部的话。对于接触腐蚀,所需的过度腐蚀可以完全穿透多晶层。上述问题的每一个可使电阻器不能工作或不可靠。由于这些原因,现有技术常常被迫接受高阻抗的端部结构甚至是非欧姆连接。
因此,仍然需要提供高值多晶硅集成电路电阻器,该电阻器具有对现有工艺的兼容性,采用很少的(如果有的话)附加的工艺步骤,采用很好控制的对于金属化层具有较低欧姆电阻的电阻器端部结构。
发明内容
本发明的一个目的是提供一种对于典型的CMOS、双极或BiCMOS工艺流程需要一个附加的单一掩模步骤的高值多晶硅电阻器。另一个目的是改善电阻器值的控制,同时提高多晶硅电阻(在特定情形下)大于一个数量级的水平。
在上面引用的Steven Leibiger的相关申请中,一个较厚的多晶硅层被沉积在硅衬底上形成的场氧化物上。该较厚的层最终可以用于形成高值电阻器的端部,采用一个第二多晶硅层形成栅、发射极、低值电阻器和电容器极板。
在Leibiger申请中,本发明的第二个目的是从两个分别沉积的多晶硅层构造高值电阻器,其方式是由仅一层形成内禀电阻器,而由两个自对准的叠层形成电阻器端部。这使得内禀电阻器更薄,并且更轻微地被掺杂,以实现高表面电阻值(大于2000欧姆每平方),而端部多晶硅叠层可以厚到容易地承受正常的处理,如接触腐蚀、硅化物形成、或其它已有的步骤。端部也可以相反地被注入比电阻器本体更重掺杂,使得可以实现多晶层和硅化物或接触材料之间的欧姆连接。
发现第二多晶硅层的厚度减小到小于1000埃正如可以预见到的那样提高电阻,该第二多晶硅层的厚度减小主要决定了Leibeiger申请中的电阻值,然而更薄的层也可以显著减小电阻自身的标准偏差。也已经发现第二层的宽度减小正如可以预见的那样可以提高电阻,但也增加了电阻的标准偏差。然而,即使采用减小的第二层宽度,较薄的厚度仍然减小电阻的标准偏差。
对于较薄的多晶硅电阻器所实现的变化上的减小的原因与几何形状和材料性质的平衡有关。多晶硅电阻器的电阻由下式表示
R=(ρ*L)/A 等式1
其中R是结构的电阻,ρ是电阻率(材料性质),L是电阻器的长度,A是电阻器的截面积。截面积(A)是电阻器的厚度与宽度之积。正如上面讨论的那样,该结构的电阻率可以通过改变掺杂剂浓度来提高。然而,随着掺杂浓度减小,电阻率随掺杂浓度的变化率急剧增加,使得难以控制电阻率(以及最终的电阻)。通过减小该结构的厚度,电阻可以与掺杂剂浓度无关地提高(上述等式1中的A减小)。对于相同的注入剂量,薄多晶层具有较高的掺杂浓度(掺杂剂物质/单位体积)。同样,该层的电阻率比厚多晶层低。由这种低电阻率材料产生的结构具有小得多的变化,因为电阻率斜率减小(图1),并且电阻器本体和端部之间的浓度驱动的扩散减少。
本领域的技术人员应当理解,尽管以下的详细描述将参照示例性的实施方式、附图、以及所用的方法来进行,但本发明不只限于这些实施方式和所用的方法。本发明具有宽的范围,并且希望只由所附权利要求来限定。
附图说明
图1是表面电阻率与掺杂浓度关系的曲线;
图2是表示由叠层覆盖的晶片区域的截面图,其顶层是多晶硅;
图3是图1中多晶硅被腐蚀以露出下面的场氧化物的结构;
图4是由图3得到的结构,第二多晶硅层被沉积在叠层上。该层可以或可以不使用原位或离子注入技术而掺杂;
图5表示两层多晶硅都被腐蚀和图案化的图4的结构;
图6是电阻器的端部接触被选择性地注入或相反被掺杂的图5的结构;
图7是硅化物层已经被形成在双多晶硅端部结构上的图6的结构;
图8是电介质和金属连接已经被施加以形成最终的电阻器的图7的结构,以及
图9是具有端部以及包含5段弯曲的细长本体的电阻器22的形貌图。
具体实施方式
按照Leibiger申请构建表面电阻率在2K欧姆每平方和23K欧姆每平方之间的高值电阻器。一些电阻器被构建成具有决定电阻率的多晶层,如下面讨论的那样,多晶层的厚度为3700埃另一些电阻器被构建成具有1000埃的厚度。较厚的多晶硅支柱(leg)是300埃的α-Si以及3400埃的多晶硅,构成3700埃的厚度。
对于具有1000埃或3700埃的层的电阻器观察到另外的反常。如果电阻器被制作成宽度2微米、长度100微米的50个方块,则具有5段弯曲的电阻器具有一致地比没有弯曲或有10段弯曲的相同电阻器更低的电阻标准偏差。
采用示例性的1000埃层以及大约4%的表面电阻标准偏差构建12K欧姆每平方的电阻器。相反,除了3700埃的层之外以同样方式制成的6K欧姆每平方电阻器具有从11%到高至43%范围内的标准偏差。对于1000埃的层,1M欧姆数量级的电阻器具有+/-5%的标准偏差,与之相比,采用3700埃层的0.3M欧姆电阻器为+/-121%。这些电阻器具有上面讨论的相同形状参数(2×100微米),没有弯曲。
采用1000埃层的12K欧姆电阻器具有-2700ppm的电阻温度系数(TCR)。然而,与3700埃层相比,对于1000埃层随电阻提高的变化率较低。
图2表示来自工艺流程的包括隔离场氧化物4和场氧化物8顶部上沉积的多晶硅层6的叠层2。尽管不同于图2中的情形,但在多晶硅下面可以有超过一层的氧化物。该多晶硅层将是所形成的高值电阻器的最终端部接触结构的底部,并且该层也可以被用于其它结构的其它部分中,如CMOS晶体管的栅或NPN晶体管的发射极。也可以作为外延沉积的一部分而形成该层。
图3表示经腐蚀或图案化以露出下面的氧化物层10的图2的结构。该图案化包括采用抗蚀剂遮蔽该结构的一些部分,对抗蚀剂的一部分进行照相曝光,然后腐蚀掉未受保护的多晶硅区域。这样的材料以及光学加工(例如步进和重复等)在本领域是公知的。该步骤中的腐蚀工艺可以另外用在工艺流程中,或者可以专用于高值电阻器形成。例如,可以是同一工序,该工序用于对双极器件有源区开口以允许在单晶基底区上外延生长。在该情形中,不需要额外的处理。
图4表示在沉积顶部多晶硅层14之后图3的结构。注意该层覆盖了第一多晶硅层的水平和垂直表面,以及所有的露出的氧化物。该第二多晶层可以比第一层薄很多,并且当厚度为1000埃或更小时,该第二多晶层表现出如上面讨论的那样未预见到的所得电阻器电阻的标准偏差的改善。它可以在标准的多晶硅系统中沉积,或者可以被设置为外延生长步骤的一部分。在该工序中,可以使用或不使用锗。如果第二层没有在沉积工艺中被原位掺杂,则该第二多晶硅层可以采用离子注入步骤来掺杂。注入可以被选择性地应用,或者可以在整个晶片上以覆盖方式应用。覆盖不需要图案化。与掺杂方法无关,厚度和杂质浓度将设置成使得第二多晶硅层的最终表面电阻将超过2000欧姆每平方。
图4的结构被遮蔽和图案化,如图5所示。这里使用的多晶硅限定和腐蚀步骤是已有的工艺流程的一部分,即使该工艺流程未使用电阻器,因此没有额外的复杂性。在图5中可以看到两个多晶电阻器端部和单个的多晶内禀电阻器14。在端部结构12A和12B已经被遮蔽并且采用在工艺中较早使用的相同n或p型材料在较高剂量下注入之后,将成为电阻器的接触点的端部结构如图6所示。也可不需要该注入步骤,并且也可以与已有的工艺步骤相同,如CMOS源和漏注入。
图7表示选择性图案化的硅化物层16和17,该硅化物层可以在电阻器端部结构上形成。该硅化物层是可选的,并且可以覆盖整个双多晶硅层,或者如所示的那样覆盖仅一部分。重要的是,如果使用,则硅化物层被构建在较厚(相对于现有技术)的多晶双层上。这排除了与直接位于薄多晶层上的硅化物层相关的问题。该硅化物层可以采用钛、钨、钴、铂或其它金属、使用熟悉硅处理技术的那些技术人员能够很好理解的方法而制成。
图8表示完成的电阻器结构,具有电介质绝缘层18和选择性设置的金属化阱20,该金属化阱将电阻器端部互连接到与芯片电路的其余部分互连接的金属化区22。注意接触部在双多晶硅电阻器端部而不是单一的多晶硅内禀电阻器上方被腐蚀。这允许已有的接触腐蚀工艺步骤不需要修改就可用于该结构,并具有充分的工艺裕度。这些阱可以由钨、铜、铝或钛或其组合或本领域已知的其它这样的金属来填充。
图9从顶表面表示电阻器,其中电阻器从端部到端部22沿其长度有5段弯曲24或回转。
应当理解,上述实施方式是作为例子而在本文中给出,可以有许多变化和替代。因此,本发明应当被更宽地看成仅由所附权利要求书中提及的那样来限定。
Claims (21)
1.一种形成在半导体晶片上的高值多晶硅电阻器,该高值多晶硅电阻器包括:
至少一个氧化物层,
制作在所述至少一个氧化物层上的第一多晶硅层,所述第一多晶硅层具有露出至少一个氧化物层的图案化且被腐蚀的开口,该被腐蚀的开口的外围限定了垂直侧壁,
整个覆盖所述第一多晶硅层表面、垂直侧壁以及被腐蚀的开口中任何露出的氧化物而沉积的厚度约1000埃的第二多晶硅层,在露出的氧化物上的所述第二多晶硅层以及垂直侧壁被图案化且被腐蚀以限定高值多晶硅电阻器的外边缘和长度,并且在第一多晶硅层上的所述第二多晶硅层被图案化且被腐蚀以限定高值多晶硅电阻器的端部,
覆盖该高值多晶硅电阻器和端部的电介质,以及
穿过电介质到达每个端部从而电连接该高值多晶硅电阻器的金属接触部。
2.根据权利要求1的高值多晶硅电阻器,还包括:
向第二多晶硅层中的注入,其中具有注入的所述第二多晶硅层的表面电阻超过2000欧姆每平方。
3.根据权利要求1的高值多晶硅电阻器,其中所述第二多晶硅层包括掺杂的多晶硅层,其中该第二多晶硅层在外延沉积工艺期间被原位掺杂以形成所述掺杂的多晶硅层,并且被掺杂的第二多晶硅层的表面电阻超过2000欧姆每平方。
4.根据权利要求1的高值多晶硅电阻器,还包括向高值多晶硅电阻器的端部的注入,以提高端部的掺杂水平。
5.根据权利要求1的高值多晶硅电阻器,还包括:
在至少一个端部上制作的自对准硅化物层。
6.根据权利要求5的高值多晶硅电阻器,其中所述硅化物层由选自以下材料构成的组之中的一种材料组成,包括:钛、钨、钴、铂。
7.根据权利要求1的高值多晶硅电阻器,其中:所述金属接触部是金属柱塞。
8.根据权利要求7的高值多晶硅电阻器,其中所述金属柱塞是钨、铜、铝或钛或其组合。
9.根据权利要求1的高值多晶硅电阻器,其中所述电阻器被设置成细长的形式,沿电阻器的长度具有至少一段弯曲。
10.根据权利要求1的高值多晶硅电阻器,其中所述第二多晶硅层的厚度小于1000埃。
11.一种用于在半导体晶片上制作高值多晶硅电阻器的方法,该方法包括以下步骤:
形成至少一个氧化物层,
在所述至少一个氧化物层上制作第一多晶硅层,
在所述第一多晶硅层中图案化且腐蚀一个开口,露出至少一个氧化物层,该开口具有垂直侧壁,
整个覆盖所述第一多晶硅层表面、垂直侧壁以及腐蚀的开口中任何露出的氧化物而制作厚度约1000埃的第二多晶硅层,
图案化且腐蚀露出的氧化物上的所述第二多晶硅层以及垂直侧壁,以限定高值多晶硅电阻器的外边缘和长度,
图案化且腐蚀第一多晶硅层上的所述第二多晶硅层,以限定高值多晶硅电阻器的端部,
采用电介质覆盖该高值多晶硅电阻器和端部,以及
形成穿过电介质到达每个端部从而电连接该高值多晶硅电阻器的金属接触部。
12.根据权利要求11的方法,还包括将电阻器制作成细长形式的步骤,其中沿电阻器的长度具有至少一段弯曲。
13.根据权利要求11的方法,还包括以下步骤:
向所述第二多晶硅层中注入,其中具有注入的所述第二多晶硅层的表面电阻超过2000欧姆每平方。
14.根据权利要求11的方法,还包括在外延沉积工艺期间对所述第二多晶硅层原位掺杂的步骤,从而形成表面电阻率超过2000欧姆每平方的掺杂第二多晶硅层。
15.根据权利要求11的方法,其中制作第一多晶硅层是外延基底BiCMOS工艺的一部分,其中第一多晶硅层为CMOS或其它有源或无源电器件结构形成保护层。
16.根据权利要求11的方法,还包括向高值多晶硅电阻器的端部中注入以提高端部中的掺杂水平的步骤。
17.根据权利要求11的方法,还包括以下步骤:
在至少一个端部上制作自对准的硅化物层。
18.根据权利要求17的方法,其中所述硅化物层由选自以下材料构成的组之中的一种材料组成,包括:钛、钨、钴、铂。
19.根据权利要求11的方法,其中所述金属接触部是金属柱塞。
20.根据权利要求19的方法,其中所述金属柱塞是钨、铜、铝或钛或其组合。
21.根据权利要求11的方法,其中所述第二多晶硅层的厚度小于1000埃。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/355,317 US6885280B2 (en) | 2003-01-31 | 2003-01-31 | High value split poly p-resistor with low standard deviation |
US10/355,317 | 2003-01-31 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1879194A CN1879194A (zh) | 2006-12-13 |
CN100399506C true CN100399506C (zh) | 2008-07-02 |
Family
ID=32770503
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2003801093855A Expired - Fee Related CN100399506C (zh) | 2003-01-31 | 2003-12-17 | 具有低标准偏差的高值分裂多晶p电阻器 |
Country Status (7)
Country | Link |
---|---|
US (2) | US6885280B2 (zh) |
JP (1) | JP2006515466A (zh) |
KR (1) | KR101050867B1 (zh) |
CN (1) | CN100399506C (zh) |
AU (1) | AU2003297987A1 (zh) |
DE (1) | DE10394085T5 (zh) |
WO (1) | WO2004070777A2 (zh) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7314786B1 (en) * | 2006-06-16 | 2008-01-01 | International Business Machines Corporation | Metal resistor, resistor material and method |
US7691717B2 (en) * | 2006-07-19 | 2010-04-06 | International Business Machines Corporation | Polysilicon containing resistor with enhanced sheet resistance precision and method for fabrication thereof |
KR20100076256A (ko) * | 2008-12-26 | 2010-07-06 | 주식회사 동부하이텍 | Pip 커패시터의 제조 방법 |
KR101616972B1 (ko) * | 2009-09-15 | 2016-04-29 | 삼성전자주식회사 | 저항 소자를 갖는 반도체 장치 및 그 형성 방법 |
CN102129977B (zh) * | 2010-01-20 | 2012-07-11 | 上海华虹Nec电子有限公司 | 电阻实现方法及电阻 |
US8470682B2 (en) * | 2010-12-14 | 2013-06-25 | International Business Machines Corporation | Methods and structures for increased thermal dissipation of thin film resistors |
US8298904B2 (en) * | 2011-01-18 | 2012-10-30 | International Business Machines Corporation | Compact thermally controlled thin film resistors utilizing substrate contacts and methods of manufacture |
US8652922B2 (en) * | 2011-01-18 | 2014-02-18 | International Business Machines Corporation | Compact thermally controlled thin film resistors utilizing substrate contacts and methods of manufacture |
US8569127B2 (en) * | 2012-03-13 | 2013-10-29 | United Microelectronics Corp. | Semiconductor device and method for fabricating the same |
US9117845B2 (en) | 2013-01-25 | 2015-08-25 | Fairchild Semiconductor Corporation | Production of laterally diffused oxide semiconductor (LDMOS) device and a bipolar junction transistor (BJT) device using a semiconductor process |
US8987107B2 (en) | 2013-02-19 | 2015-03-24 | Fairchild Semiconductor Corporation | Production of high-performance passive devices using existing operations of a semiconductor process |
US10229966B2 (en) * | 2016-12-30 | 2019-03-12 | Texas Instruments Incorporated | Semiconductor resistor structure and method for making |
JP6962866B2 (ja) * | 2018-06-04 | 2021-11-05 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
CN109904117B (zh) * | 2019-03-26 | 2019-10-08 | 武汉新芯集成电路制造有限公司 | 一种互连结构及其制造方法 |
CN112820715B (zh) * | 2020-12-28 | 2022-12-06 | 中国电子科技集团公司第十三研究所 | 校准用晶圆级在片电阻标准样片及制备方法 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4785342A (en) * | 1986-01-29 | 1988-11-15 | Hitachi, Ltd. | Static random access memory having structure of first-, second- and third-level conductive films |
US5200733A (en) * | 1991-10-01 | 1993-04-06 | Harris Semiconductor Corporation | Resistor structure and method of fabrication |
US5587696A (en) * | 1995-06-28 | 1996-12-24 | Taiwan Semiconductor Manufacturing Company Ltd. | High resistance polysilicon resistor for integrated circuits and method of fabrication thereof |
US5959343A (en) * | 1997-04-21 | 1999-09-28 | Seiko Instruments R&D Center Inc. | Semiconductor device |
US6054359A (en) * | 1999-06-14 | 2000-04-25 | Taiwan Semiconductor Manufacturing Company | Method for making high-sheet-resistance polysilicon resistors for integrated circuits |
US6211031B1 (en) * | 1998-10-01 | 2001-04-03 | Taiwan Semiconductor Manufacturing Company | Method to produce dual polysilicon resistance in an integrated circuit |
CN1326591A (zh) * | 1998-11-13 | 2001-12-12 | 艾利森电话股份有限公司 | 多晶硅电阻器及其制造方法 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4523582A (en) * | 1982-06-07 | 1985-06-18 | Barber S Morgan | Device for suspending the human body in an inverted position |
US4528582A (en) | 1983-09-21 | 1985-07-09 | General Electric Company | Interconnection structure for polycrystalline silicon resistor and methods of making same |
JPS62285462A (ja) * | 1986-06-03 | 1987-12-11 | Sony Corp | 半導体装置 |
JPS6350054A (ja) * | 1986-08-19 | 1988-03-02 | Nec Corp | 半導体集積回路装置 |
JPH01199462A (ja) * | 1988-02-04 | 1989-08-10 | Seiko Epson Corp | 半導体装置 |
JPH0812926B2 (ja) * | 1988-12-06 | 1996-02-07 | 財団法人工業技術研究院 | 薄膜電界効果トランジスタの製造方法 |
JPH0555215A (ja) * | 1991-08-23 | 1993-03-05 | Fuji Xerox Co Ltd | 半導体装置の製造方法 |
JPH0555520A (ja) * | 1991-08-26 | 1993-03-05 | Sharp Corp | 半導体装置の製造方法 |
JP3013628B2 (ja) * | 1992-08-19 | 2000-02-28 | 日本電気株式会社 | 半導体装置 |
JP3404064B2 (ja) * | 1993-03-09 | 2003-05-06 | 株式会社日立製作所 | 半導体装置及びその製造方法 |
JPH0818011A (ja) * | 1994-04-25 | 1996-01-19 | Seiko Instr Inc | 半導体装置及びその製造方法 |
JP3719618B2 (ja) * | 1996-06-17 | 2005-11-24 | 松下電器産業株式会社 | 半導体装置及びその製造方法 |
JP3420104B2 (ja) * | 1999-04-21 | 2003-06-23 | 山形日本電気株式会社 | 抵抗素子の製造方法 |
US6700474B1 (en) * | 2001-08-24 | 2004-03-02 | Fairchild Semiconductor Corporation | High value polysilicon resistor |
-
2003
- 2003-01-31 US US10/355,317 patent/US6885280B2/en not_active Expired - Fee Related
- 2003-12-17 KR KR1020057014061A patent/KR101050867B1/ko not_active IP Right Cessation
- 2003-12-17 CN CNB2003801093855A patent/CN100399506C/zh not_active Expired - Fee Related
- 2003-12-17 DE DE10394085T patent/DE10394085T5/de not_active Withdrawn
- 2003-12-17 WO PCT/US2003/040454 patent/WO2004070777A2/en active Application Filing
- 2003-12-17 AU AU2003297987A patent/AU2003297987A1/en not_active Abandoned
- 2003-12-17 JP JP2004568037A patent/JP2006515466A/ja active Pending
-
2004
- 2004-12-21 US US11/018,041 patent/US7078305B2/en not_active Expired - Lifetime
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4785342A (en) * | 1986-01-29 | 1988-11-15 | Hitachi, Ltd. | Static random access memory having structure of first-, second- and third-level conductive films |
US5200733A (en) * | 1991-10-01 | 1993-04-06 | Harris Semiconductor Corporation | Resistor structure and method of fabrication |
US5587696A (en) * | 1995-06-28 | 1996-12-24 | Taiwan Semiconductor Manufacturing Company Ltd. | High resistance polysilicon resistor for integrated circuits and method of fabrication thereof |
US5959343A (en) * | 1997-04-21 | 1999-09-28 | Seiko Instruments R&D Center Inc. | Semiconductor device |
US6211031B1 (en) * | 1998-10-01 | 2001-04-03 | Taiwan Semiconductor Manufacturing Company | Method to produce dual polysilicon resistance in an integrated circuit |
CN1326591A (zh) * | 1998-11-13 | 2001-12-12 | 艾利森电话股份有限公司 | 多晶硅电阻器及其制造方法 |
US6054359A (en) * | 1999-06-14 | 2000-04-25 | Taiwan Semiconductor Manufacturing Company | Method for making high-sheet-resistance polysilicon resistors for integrated circuits |
Also Published As
Publication number | Publication date |
---|---|
DE10394085T5 (de) | 2005-12-22 |
AU2003297987A8 (en) | 2004-08-30 |
US7078305B2 (en) | 2006-07-18 |
WO2004070777A3 (en) | 2006-06-01 |
KR20060010715A (ko) | 2006-02-02 |
US6885280B2 (en) | 2005-04-26 |
CN1879194A (zh) | 2006-12-13 |
WO2004070777A2 (en) | 2004-08-19 |
US20040150507A1 (en) | 2004-08-05 |
AU2003297987A1 (en) | 2004-08-30 |
JP2006515466A (ja) | 2006-05-25 |
KR101050867B1 (ko) | 2011-07-20 |
US20050106805A1 (en) | 2005-05-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN100399506C (zh) | 具有低标准偏差的高值分裂多晶p电阻器 | |
JPH0834310B2 (ja) | 半導体装置の製造方法 | |
US7569448B2 (en) | Semiconductor device including bipolar junction transistor with protected emitter-base junction | |
EP0905751A3 (en) | Method for minimizing lateral and vertical dopant diffusion in gate structures | |
TWI423343B (zh) | 半導體積體電路裝置及其製造方法 | |
US6448163B1 (en) | Method for fabricating T-shaped transistor gate | |
US6798007B2 (en) | Method of fabricating a semiconductor device having a non-volatile semiconductor memory and a capacitor | |
JPH056963A (ja) | 半導体集積回路装置およびその製造方法 | |
JPH0864689A (ja) | 半導体集積回路装置 | |
US7585733B2 (en) | Method of manufacturing semiconductor device having multiple gate insulation films | |
US6180462B1 (en) | Method of fabricating an analog integrated circuit with ESD protection | |
US6700474B1 (en) | High value polysilicon resistor | |
JPH06163535A (ja) | 半導体装置およびその製造方法 | |
US5462888A (en) | Process for manufacturing semiconductor BICMOS device | |
JPH0254662B2 (zh) | ||
JPH10163430A (ja) | 半導体装置およびその製造方法 | |
WO2005043605A1 (en) | Integrated circuit with partly silicidated silicon layer | |
US7595535B2 (en) | Resistor of semiconductor device and method for fabricating the same | |
JP3104609B2 (ja) | 半導体装置およびその製造方法 | |
JP3183249B2 (ja) | 高抵抗負荷スタチック型ramの製造方法 | |
JP3483488B2 (ja) | 半導体装置の製造方法 | |
JP3527148B2 (ja) | 半導体装置の製造方法 | |
JPH05291506A (ja) | 半導体集積回路装置及びその製造方法 | |
JP2002009249A (ja) | 半導体装置及びその製造方法 | |
JP3300474B2 (ja) | 半導体装置およびその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080702 Termination date: 20161217 |