CH636216A5 - N-kanal-mos-speicher und verfahren zu dessen herstellung. - Google Patents

N-kanal-mos-speicher und verfahren zu dessen herstellung. Download PDF

Info

Publication number
CH636216A5
CH636216A5 CH1130478A CH1130478A CH636216A5 CH 636216 A5 CH636216 A5 CH 636216A5 CH 1130478 A CH1130478 A CH 1130478A CH 1130478 A CH1130478 A CH 1130478A CH 636216 A5 CH636216 A5 CH 636216A5
Authority
CH
Switzerland
Prior art keywords
epitaxial layer
layer
silicon
memory according
zone
Prior art date
Application number
CH1130478A
Other languages
German (de)
English (en)
Inventor
James Theodore Clemens
Dinesh Ashvinikumar Mehta
James Thomas Nelson
Charles Walter Pearce
Robert Ching-I Sun
Original Assignee
Western Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co filed Critical Western Electric Co
Publication of CH636216A5 publication Critical patent/CH636216A5/de

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/35Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices with charge storage in a depletion layer, e.g. charge coupled devices
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
CH1130478A 1977-11-03 1978-11-02 N-kanal-mos-speicher und verfahren zu dessen herstellung. CH636216A5 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US84800077A 1977-11-03 1977-11-03

Publications (1)

Publication Number Publication Date
CH636216A5 true CH636216A5 (de) 1983-05-13

Family

ID=25302070

Family Applications (1)

Application Number Title Priority Date Filing Date
CH1130478A CH636216A5 (de) 1977-11-03 1978-11-02 N-kanal-mos-speicher und verfahren zu dessen herstellung.

Country Status (17)

Country Link
JP (2) JPS5474684A (fr)
BE (1) BE871678A (fr)
CA (1) CA1129550A (fr)
CH (1) CH636216A5 (fr)
DE (1) DE2846872B2 (fr)
FR (1) FR2408191A1 (fr)
GB (1) GB2007430B (fr)
HK (1) HK25484A (fr)
IL (1) IL55812A (fr)
IN (1) IN151278B (fr)
IT (1) IT1100012B (fr)
MY (1) MY8400042A (fr)
NL (1) NL191768C (fr)
PL (1) PL115612B1 (fr)
SE (1) SE438217B (fr)
SG (1) SG56282G (fr)
TR (1) TR20234A (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4216489A (en) * 1979-01-22 1980-08-05 Bell Telephone Laboratories, Incorporated MOS Dynamic memory in a diffusion current limited semiconductor structure
DE3069973D1 (en) * 1979-08-25 1985-02-28 Zaidan Hojin Handotai Kenkyu Insulated-gate field-effect transistor
JPS5694732A (en) * 1979-12-28 1981-07-31 Fujitsu Ltd Semiconductor substrate
DE3177173D1 (de) * 1980-01-25 1990-05-23 Toshiba Kawasaki Kk Halbleiterspeichervorrichtung.
JPH0782753B2 (ja) * 1984-08-31 1995-09-06 三菱電機株式会社 ダイナミックメモリ装置
USD845135S1 (en) 2017-02-24 2019-04-09 S. C. Johnson & Son, Inc. Bottle neck with cap

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1544327A1 (de) * 1951-01-28 1970-02-26 Telefunken Patent Verfahren zum Herstellen einer dotierten Zone in einem begrenzten Bereich eines Halbleiterkoerpers
US3918081A (en) * 1968-04-23 1975-11-04 Philips Corp Integrated semiconductor device employing charge storage and charge transport for memory or delay line
US3852800A (en) * 1971-08-02 1974-12-03 Texas Instruments Inc One transistor dynamic memory cell
JPS5123432B2 (fr) * 1971-08-26 1976-07-16
JPS4931509U (fr) * 1972-06-17 1974-03-19
US3961355A (en) * 1972-06-30 1976-06-01 International Business Machines Corporation Semiconductor device having electrically insulating barriers for surface leakage sensitive devices and method of forming
US4012757A (en) * 1975-05-05 1977-03-15 Intel Corporation Contactless random-access memory cell and cell pair
US3997368A (en) * 1975-06-24 1976-12-14 Bell Telephone Laboratories, Incorporated Elimination of stacking faults in silicon devices: a gettering process
US4003036A (en) * 1975-10-23 1977-01-11 American Micro-Systems, Inc. Single IGFET memory cell with buried storage element
JPS5279786A (en) * 1975-12-26 1977-07-05 Fujitsu Ltd Semiconductor memory device
JPS5290279A (en) * 1976-01-23 1977-07-29 Nippon Telegr & Teleph Corp <Ntt> Mos memory device
DE2603746A1 (de) * 1976-01-31 1977-08-04 Licentia Gmbh Integrierte schaltungsanordnung
DE2619713C2 (de) * 1976-05-04 1984-12-20 Siemens AG, 1000 Berlin und 8000 München Halbleiterspeicher

Also Published As

Publication number Publication date
NL7810929A (nl) 1979-05-07
SG56282G (en) 1983-09-02
DE2846872C3 (fr) 1989-06-08
IT1100012B (it) 1985-09-28
FR2408191B1 (fr) 1982-11-19
BE871678A (fr) 1979-02-15
IL55812A0 (en) 1978-12-17
PL210682A1 (pl) 1979-07-16
SE438217B (sv) 1985-04-01
FR2408191A1 (fr) 1979-06-01
IT7829360A0 (it) 1978-11-02
HK25484A (en) 1984-03-30
GB2007430A (en) 1979-05-16
NL191768B (nl) 1996-03-01
DE2846872B2 (de) 1981-04-30
CA1129550A (fr) 1982-08-10
MY8400042A (en) 1984-12-31
JPH019174Y2 (fr) 1989-03-13
JPS59115667U (ja) 1984-08-04
PL115612B1 (en) 1981-04-30
GB2007430B (en) 1982-03-03
JPS5474684A (en) 1979-06-14
IL55812A (en) 1981-10-30
DE2846872A1 (de) 1979-05-10
TR20234A (tr) 1980-11-01
NL191768C (nl) 1996-07-02
SE7811094L (sv) 1979-05-04
IN151278B (fr) 1983-03-19

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Legal Events

Date Code Title Description
PL Patent ceased