JPS59115667U - 集積回路 - Google Patents

集積回路

Info

Publication number
JPS59115667U
JPS59115667U JP1983192222U JP19222283U JPS59115667U JP S59115667 U JPS59115667 U JP S59115667U JP 1983192222 U JP1983192222 U JP 1983192222U JP 19222283 U JP19222283 U JP 19222283U JP S59115667 U JPS59115667 U JP S59115667U
Authority
JP
Japan
Prior art keywords
integrated circuit
epitaxial layer
layer
type
paragraph
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1983192222U
Other languages
English (en)
Other versions
JPH019174Y2 (ja
Inventor
ジエ−ムス・セオドア−・クレメンズ
デイネツシユ・アツシユヴイニクマ−・メ−タ
ジエ−ムス・ト−マス・ネルソン
チヤ−ルズ・ウオルタ−・ピア−ス
ロバ−ト・チング−アイ・サン
Original Assignee
ウエスタ−ン・エレクトリツク・カムパニ−・インコ−ポレ−テツド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ウエスタ−ン・エレクトリツク・カムパニ−・インコ−ポレ−テツド filed Critical ウエスタ−ン・エレクトリツク・カムパニ−・インコ−ポレ−テツド
Publication of JPS59115667U publication Critical patent/JPS59115667U/ja
Application granted granted Critical
Publication of JPH019174Y2 publication Critical patent/JPH019174Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/35—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices with charge storage in a depletion layer, e.g. charge coupled devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は、本考案の実施例を説明するため用いられる半
導体ウェーハの一部の断面図であり、説明上、基板上の
エピタキシャル層を基板の厚さに。 比例して示した図、第２図は、第１図のエピタキシャル
部の拡大図であり、本考案に基づく低い漏洩電流特性を
有するｐｎ接合形成のためドープされた各領域を示した
図、第３図は、第２図の構造の電気的機能を示した図、
第４図は、第１図の半導体ウェーハ内の所望のホウ素濃
度分布を示した図、第５図は、所望の逆方向漏洩電流特
性を得るため本考案の適用できる他の実施例の構造を示
した図である。 〔主要部分の符号の説明〕、ｎ型領域・・・・・・２２
゜２３．２４、半導体基体・・・・・・１２、エピタキ
シャル層・・・・・・１４、グラファイトサセプタ・・
・・・・６３、シリコン層−−−−−−６６゜

Claims (1)

  1. 【実用新案登録請求の範囲】 Ｉ　Ｐ型シリコン半導体中に含まれるｎ型領域を少なく
    とも一つ含む本質的に平坦なＭＯＳトランジスタ素子を
    含む型式の多数のｎチャネルＭＯＳメモリセルを含む量
    産型集積回路におい動作時に空乏層を形成するように設
    計され、そのエピタキシャル層が接合深さを包含しそし
    て接合が十分に逆バイアスされた状態で、該エピタキシ
    ャル層内の空乏層幅を完全に囲むだけの厚さを有するも
    のであること特徴とする集積回５　実用新案登録請求の
    範囲第１項に記載された集積回路において、 半導体基体が少なくとも１０１８ｃ７７に−３のＰ型ド
    ーパント濃度を有し、エピタキシャル層が１０１４ない
    し１０１６Ｃ７Ｆ！−３の範囲のＰ型ドーハント濃度を
    有することを特徴とする集積回路。 ６　実用新案登録請求の範囲第１項、第２項または第３
    項に記載された集積回路において、前記エピタキシャル
    層は、シリコン層で被覆されたグラファイトサセプタ上
    に置かれた半導体をガス雰囲気で加熱することにより成
    長させられた層であることを特徴とする集積回路。
JP1983192222U 1977-11-03 1983-12-15 集積回路 Granted JPS59115667U (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US84800077A 1977-11-03 1977-11-03
US848000 1977-11-03

Publications (2)

Publication Number Publication Date
JPS59115667U true JPS59115667U (ja) 1984-08-04
JPH019174Y2 JPH019174Y2 (ja) 1989-03-13

Family

ID=25302070

Family Applications (2)

Application Number Title Priority Date Filing Date
JP13466978A Pending JPS5474684A (en) 1977-11-03 1978-11-02 Nnchannel mos memory
JP1983192222U Granted JPS59115667U (ja) 1977-11-03 1983-12-15 集積回路

Family Applications Before (1)

Application Number Title Priority Date Filing Date
JP13466978A Pending JPS5474684A (en) 1977-11-03 1978-11-02 Nnchannel mos memory

Country Status (17)

Country Link
JP (2) JPS5474684A (ja)
BE (1) BE871678A (ja)
CA (1) CA1129550A (ja)
CH (1) CH636216A5 (ja)
DE (1) DE2846872B2 (ja)
FR (1) FR2408191A1 (ja)
GB (1) GB2007430B (ja)
HK (1) HK25484A (ja)
IL (1) IL55812A (ja)
IN (1) IN151278B (ja)
IT (1) IT1100012B (ja)
MY (1) MY8400042A (ja)
NL (1) NL191768C (ja)
PL (1) PL115612B1 (ja)
SE (1) SE438217B (ja)
SG (1) SG56282G (ja)
TR (1) TR20234A (ja)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4216489A (en) * 1979-01-22 1980-08-05 Bell Telephone Laboratories, Incorporated MOS Dynamic memory in a diffusion current limited semiconductor structure
DE3069973D1 (en) * 1979-08-25 1985-02-28 Zaidan Hojin Handotai Kenkyu Insulated-gate field-effect transistor
JPS5694732A (en) * 1979-12-28 1981-07-31 Fujitsu Ltd Semiconductor substrate
DE3177173D1 (de) * 1980-01-25 1990-05-23 Toshiba Kawasaki Kk Halbleiterspeichervorrichtung.
JPH0782753B2 (ja) * 1984-08-31 1995-09-06 三菱電機株式会社 ダイナミックメモリ装置
USD845135S1 (en) 2017-02-24 2019-04-09 S. C. Johnson & Son, Inc. Bottle neck with cap

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1544327A1 (de) * 1951-01-28 1970-02-26 Telefunken Patent Verfahren zum Herstellen einer dotierten Zone in einem begrenzten Bereich eines Halbleiterkoerpers
US3918081A (en) * 1968-04-23 1975-11-04 Philips Corp Integrated semiconductor device employing charge storage and charge transport for memory or delay line
US3852800A (en) * 1971-08-02 1974-12-03 Texas Instruments Inc One transistor dynamic memory cell
JPS5123432B2 (ja) * 1971-08-26 1976-07-16
JPS4931509U (ja) * 1972-06-17 1974-03-19
US3961355A (en) * 1972-06-30 1976-06-01 International Business Machines Corporation Semiconductor device having electrically insulating barriers for surface leakage sensitive devices and method of forming
US4012757A (en) * 1975-05-05 1977-03-15 Intel Corporation Contactless random-access memory cell and cell pair
US3997368A (en) * 1975-06-24 1976-12-14 Bell Telephone Laboratories, Incorporated Elimination of stacking faults in silicon devices: a gettering process
US4003036A (en) * 1975-10-23 1977-01-11 American Micro-Systems, Inc. Single IGFET memory cell with buried storage element
JPS5279786A (en) * 1975-12-26 1977-07-05 Fujitsu Ltd Semiconductor memory device
JPS5290279A (en) * 1976-01-23 1977-07-29 Nippon Telegr & Teleph Corp <Ntt> Mos memory device
DE2603746A1 (de) * 1976-01-31 1977-08-04 Licentia Gmbh Integrierte schaltungsanordnung
DE2619713C2 (de) * 1976-05-04 1984-12-20 Siemens AG, 1000 Berlin und 8000 München Halbleiterspeicher

Also Published As

Publication number Publication date
NL7810929A (nl) 1979-05-07
SG56282G (en) 1983-09-02
DE2846872C3 (ja) 1989-06-08
IT1100012B (it) 1985-09-28
FR2408191B1 (ja) 1982-11-19
BE871678A (fr) 1979-02-15
IL55812A0 (en) 1978-12-17
PL210682A1 (pl) 1979-07-16
SE438217B (sv) 1985-04-01
FR2408191A1 (fr) 1979-06-01
IT7829360A0 (it) 1978-11-02
HK25484A (en) 1984-03-30
GB2007430A (en) 1979-05-16
NL191768B (nl) 1996-03-01
DE2846872B2 (de) 1981-04-30
CA1129550A (en) 1982-08-10
MY8400042A (en) 1984-12-31
JPH019174Y2 (ja) 1989-03-13
PL115612B1 (en) 1981-04-30
GB2007430B (en) 1982-03-03
JPS5474684A (en) 1979-06-14
IL55812A (en) 1981-10-30
DE2846872A1 (de) 1979-05-10
TR20234A (tr) 1980-11-01
NL191768C (nl) 1996-07-02
CH636216A5 (de) 1983-05-13
SE7811094L (sv) 1979-05-04
IN151278B (ja) 1983-03-19

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