AU2001263347A1 - Burst architecture for a flash memory - Google Patents

Burst architecture for a flash memory

Info

Publication number
AU2001263347A1
AU2001263347A1 AU2001263347A AU6334701A AU2001263347A1 AU 2001263347 A1 AU2001263347 A1 AU 2001263347A1 AU 2001263347 A AU2001263347 A AU 2001263347A AU 6334701 A AU6334701 A AU 6334701A AU 2001263347 A1 AU2001263347 A1 AU 2001263347A1
Authority
AU
Australia
Prior art keywords
data
circuit
data word
data words
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001263347A
Other languages
English (en)
Inventor
Takao Akaogi
Lee Cleveland
Kendra Nguyen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Advanced Micro Devices Inc
Original Assignee
Fujitsu Ltd
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Advanced Micro Devices Inc filed Critical Fujitsu Ltd
Publication of AU2001263347A1 publication Critical patent/AU2001263347A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Landscapes

  • Read Only Memory (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
AU2001263347A 2000-05-31 2001-05-21 Burst architecture for a flash memory Abandoned AU2001263347A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US20865200P 2000-05-31 2000-05-31
US60208652 2000-05-31
US09829518 2001-04-09
US09/829,518 US6621761B2 (en) 2000-05-31 2001-04-09 Burst architecture for a flash memory
PCT/US2001/016426 WO2001093272A2 (en) 2000-05-31 2001-05-21 Burst architecture for a flash memory

Publications (1)

Publication Number Publication Date
AU2001263347A1 true AU2001263347A1 (en) 2001-12-11

Family

ID=26903366

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001263347A Abandoned AU2001263347A1 (en) 2000-05-31 2001-05-21 Burst architecture for a flash memory

Country Status (11)

Country Link
US (1) US6621761B2 (zh)
EP (1) EP1295294B1 (zh)
JP (1) JP4737917B2 (zh)
KR (1) KR100717412B1 (zh)
CN (2) CN100552806C (zh)
AT (1) ATE287119T1 (zh)
AU (1) AU2001263347A1 (zh)
BR (1) BR0111303A (zh)
DE (1) DE60108388T2 (zh)
TW (1) TW507212B (zh)
WO (1) WO2001093272A2 (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB0122401D0 (en) * 2001-09-17 2001-11-07 Ttp Communications Ltd Interfacing processors with external memory
JP2003223792A (ja) * 2002-01-25 2003-08-08 Hitachi Ltd 不揮発性メモリ及びメモリカード
ITVA20020016A1 (it) * 2002-02-21 2003-08-21 St Microelectronics Srl Metodo di scrittura di un insieme di bytes di dati in una memoria standard e relativo dispositivo di memoria
JP4469649B2 (ja) * 2003-09-17 2010-05-26 株式会社ルネサステクノロジ 半導体フラッシュメモリ
US6973003B1 (en) 2003-10-01 2005-12-06 Advanced Micro Devices, Inc. Memory device and method
JP4708723B2 (ja) * 2004-03-30 2011-06-22 ルネサスエレクトロニクス株式会社 半導体記憶装置
KR100598114B1 (ko) * 2005-01-25 2006-07-10 삼성전자주식회사 페이지 모드 동작을 수행하는 반도체 메모리 장치
CN101458960B (zh) * 2007-12-13 2011-12-07 中芯国际集成电路制造(上海)有限公司 叠加容量存储器及控制方法
KR100915824B1 (ko) * 2008-01-07 2009-09-07 주식회사 하이닉스반도체 반도체 메모리 장치의 입력 회로 및 그 제어 방법
KR100935593B1 (ko) 2008-02-12 2010-01-07 주식회사 하이닉스반도체 페이지 버퍼를 제어하는 비휘발성 메모리 장치
US8285917B2 (en) * 2009-03-26 2012-10-09 Scaleo Chip Apparatus for enhancing flash memory access
CN113409870A (zh) * 2021-06-30 2021-09-17 芯天下技术股份有限公司 一种闪存擦除方法、扇区选择电路、装置和电子设备

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960003526B1 (ko) * 1992-10-02 1996-03-14 삼성전자주식회사 반도체 메모리장치
US5604884A (en) * 1993-03-22 1997-02-18 Compaq Computer Corporation Burst SRAMS for use with a high speed clock
US5696917A (en) * 1994-06-03 1997-12-09 Intel Corporation Method and apparatus for performing burst read operations in an asynchronous nonvolatile memory
JP2904076B2 (ja) * 1995-11-10 1999-06-14 日本電気株式会社 半導体記憶装置
KR100218734B1 (ko) * 1996-05-06 1999-09-01 김영환 싱크로노스 메모리의 내부펄스 신호발생 방법 및 그장치
JP3789173B2 (ja) 1996-07-22 2006-06-21 Ｎｅｃエレクトロニクス株式会社 半導体記憶装置及び半導体記憶装置のアクセス方法
JPH1139871A (ja) * 1997-01-10 1999-02-12 Mitsubishi Electric Corp 同期型半導体記憶装置
US5903496A (en) * 1997-06-25 1999-05-11 Intel Corporation Synchronous page-mode non-volatile memory with burst order circuitry
US5923615A (en) * 1998-04-17 1999-07-13 Motorlola Synchronous pipelined burst memory and method for operating same
US6216180B1 (en) * 1998-05-21 2001-04-10 Intel Corporation Method and apparatus for a nonvolatile memory interface for burst read operations
JP4060442B2 (ja) * 1998-05-28 2008-03-12 富士通株式会社 メモリデバイス
JP2000048586A (ja) * 1998-07-30 2000-02-18 Fujitsu Ltd 不揮発性半導体記憶装置
JP4043151B2 (ja) * 1998-08-26 2008-02-06 富士通株式会社 高速ランダムアクセス可能なメモリデバイス
KR100359157B1 (ko) * 1998-12-30 2003-01-24 주식회사 하이닉스반도체 라이트 명령어 레이턴시회로 및 그 제어방법
US6104667A (en) * 1999-07-29 2000-08-15 Fujitsu Limited Clock control circuit for generating an internal clock signal with one or more external clock cycles being blocked out and a synchronous flash memory device using the same
US6111787A (en) * 1999-10-19 2000-08-29 Advanced Micro Devices, Inc. Address transistion detect timing architecture for a simultaneous operation flash memory device
US6285585B1 (en) * 1999-10-19 2001-09-04 Advaned Micro Devices, Inc. Output switching implementation for a flash memory device
US6205084B1 (en) * 1999-12-20 2001-03-20 Fujitsu Limited Burst mode flash memory
US6314049B1 (en) * 2000-03-30 2001-11-06 Micron Technology, Inc. Elimination of precharge operation in synchronous flash memory
US6304510B1 (en) * 2000-08-31 2001-10-16 Micron Technology, Inc. Memory device address decoding

Also Published As

Publication number Publication date
CN1447972A (zh) 2003-10-08
EP1295294B1 (en) 2005-01-12
WO2001093272A2 (en) 2001-12-06
BR0111303A (pt) 2003-06-17
CN101345078B (zh) 2013-04-10
KR100717412B1 (ko) 2007-05-11
CN100552806C (zh) 2009-10-21
KR20030014255A (ko) 2003-02-15
DE60108388D1 (de) 2005-02-17
TW507212B (en) 2002-10-21
US20020012278A1 (en) 2002-01-31
JP2003535428A (ja) 2003-11-25
EP1295294A2 (en) 2003-03-26
DE60108388T2 (de) 2005-09-29
CN101345078A (zh) 2009-01-14
US6621761B2 (en) 2003-09-16
WO2001093272A3 (en) 2002-03-28
JP4737917B2 (ja) 2011-08-03
ATE287119T1 (de) 2005-01-15

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