ITVA20020016A1 - Metodo di scrittura di un insieme di bytes di dati in una memoria standard e relativo dispositivo di memoria - Google Patents

Metodo di scrittura di un insieme di bytes di dati in una memoria standard e relativo dispositivo di memoria

Info

Publication number
ITVA20020016A1
ITVA20020016A1 IT2002VA000016A ITVA20020016A ITVA20020016A1 IT VA20020016 A1 ITVA20020016 A1 IT VA20020016A1 IT 2002VA000016 A IT2002VA000016 A IT 2002VA000016A IT VA20020016 A ITVA20020016 A IT VA20020016A IT VA20020016 A1 ITVA20020016 A1 IT VA20020016A1
Authority
IT
Italy
Prior art keywords
bytes
data
writing method
memory device
standard
Prior art date
Application number
IT2002VA000016A
Other languages
English (en)
Inventor
Salvatore Polizzi
Salvatore Poli
Paolino Schillaci
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT2002VA000016A priority Critical patent/ITVA20020016A1/it
Publication of ITVA20020016A0 publication Critical patent/ITVA20020016A0/it
Priority to US10/371,221 priority patent/US6996697B2/en
Publication of ITVA20020016A1 publication Critical patent/ITVA20020016A1/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Read Only Memory (AREA)
  • Dram (AREA)
IT2002VA000016A 2002-02-21 2002-02-21 Metodo di scrittura di un insieme di bytes di dati in una memoria standard e relativo dispositivo di memoria ITVA20020016A1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT2002VA000016A ITVA20020016A1 (it) 2002-02-21 2002-02-21 Metodo di scrittura di un insieme di bytes di dati in una memoria standard e relativo dispositivo di memoria
US10/371,221 US6996697B2 (en) 2002-02-21 2003-02-21 Method of writing a group of data bytes in a memory and memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT2002VA000016A ITVA20020016A1 (it) 2002-02-21 2002-02-21 Metodo di scrittura di un insieme di bytes di dati in una memoria standard e relativo dispositivo di memoria

Publications (2)

Publication Number Publication Date
ITVA20020016A0 ITVA20020016A0 (it) 2002-02-21
ITVA20020016A1 true ITVA20020016A1 (it) 2003-08-21

Family

ID=11460906

Family Applications (1)

Application Number Title Priority Date Filing Date
IT2002VA000016A ITVA20020016A1 (it) 2002-02-21 2002-02-21 Metodo di scrittura di un insieme di bytes di dati in una memoria standard e relativo dispositivo di memoria

Country Status (2)

Country Link
US (1) US6996697B2 (it)
IT (1) ITVA20020016A1 (it)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107402714B (zh) * 2016-05-20 2020-06-02 中芯国际集成电路制造(上海)有限公司 用于串行闪存的写操作的方法和串行闪存

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55143652A (en) * 1979-04-25 1980-11-10 Hitachi Ltd Series-parallel signal converter
US6157970A (en) * 1997-09-24 2000-12-05 Intel Corporation Direct memory access system using time-multiplexing for transferring address, data, and control and a separate control line for serially transmitting encoded DMA channel number
US6131127A (en) * 1997-09-24 2000-10-10 Intel Corporation I/O transactions on a low pin count bus
US6621761B2 (en) * 2000-05-31 2003-09-16 Advanced Micro Devices, Inc. Burst architecture for a flash memory
US6469954B1 (en) * 2000-08-21 2002-10-22 Micron Technology, Inc. Device and method for reducing idle cycles in a semiconductor memory device
JP3802763B2 (ja) * 2001-01-29 2006-07-26 シャープ株式会社 不揮発性半導体メモリ装置およびその消去方法

Also Published As

Publication number Publication date
US20030182533A1 (en) 2003-09-25
ITVA20020016A0 (it) 2002-02-21
US6996697B2 (en) 2006-02-07

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