ATE526681T1 - Vergrössern der chipbelastungsfähigkeit durch ätzen während oder nach des zerteilens - Google Patents

Vergrössern der chipbelastungsfähigkeit durch ätzen während oder nach des zerteilens

Info

Publication number
ATE526681T1
ATE526681T1 AT05808203T AT05808203T ATE526681T1 AT E526681 T1 ATE526681 T1 AT E526681T1 AT 05808203 T AT05808203 T AT 05808203T AT 05808203 T AT05808203 T AT 05808203T AT E526681 T1 ATE526681 T1 AT E526681T1
Authority
AT
Austria
Prior art keywords
carrier
diving
semiconductor wafer
load capacity
etching during
Prior art date
Application number
AT05808203T
Other languages
German (de)
English (en)
Inventor
Adrian Boyle
David Gillen
Kali Dunne
Gomez Eva Fernandes
Richard Toftness
Original Assignee
Electro Scient Ind Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Electro Scient Ind Inc filed Critical Electro Scient Ind Inc
Application granted granted Critical
Publication of ATE526681T1 publication Critical patent/ATE526681T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass

Landscapes

  • Dicing (AREA)
  • Weting (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Polishing Bodies And Polishing Tools (AREA)
  • Processing Of Stones Or Stones Resemblance Materials (AREA)
AT05808203T 2004-11-01 2005-11-01 Vergrössern der chipbelastungsfähigkeit durch ätzen während oder nach des zerteilens ATE526681T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB0424195A GB2420443B (en) 2004-11-01 2004-11-01 Increasing die strength by etching during or after dicing
PCT/EP2005/011671 WO2006048230A1 (en) 2004-11-01 2005-11-01 Increasing die strength by etching during or after dicing

Publications (1)

Publication Number Publication Date
ATE526681T1 true ATE526681T1 (de) 2011-10-15

Family

ID=33515886

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05808203T ATE526681T1 (de) 2004-11-01 2005-11-01 Vergrössern der chipbelastungsfähigkeit durch ätzen während oder nach des zerteilens

Country Status (9)

Country Link
US (1) US20090191690A1 (https=)
EP (1) EP1825507B1 (https=)
JP (2) JP4690417B2 (https=)
KR (1) KR20070051360A (https=)
CN (1) CN101088157B (https=)
AT (1) ATE526681T1 (https=)
GB (1) GB2420443B (https=)
TW (1) TWI278032B (https=)
WO (1) WO2006048230A1 (https=)

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JP6282194B2 (ja) * 2014-07-30 2018-02-21 株式会社ディスコ ウェーハの加工方法
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JP6587911B2 (ja) * 2015-11-16 2019-10-09 株式会社ディスコ ウエーハの分割方法
CN108630599A (zh) * 2017-03-22 2018-10-09 东莞新科技术研究开发有限公司 芯片的形成方法
US10373869B2 (en) 2017-05-24 2019-08-06 Semiconductor Components Industries, Llc Method of separating a back layer on a substrate using exposure to reduced temperature and related apparatus
CN107579032B (zh) * 2017-07-27 2019-04-09 厦门市三安集成电路有限公司 一种化合物半导体器件的背面制程方法
JP7066263B2 (ja) * 2018-01-23 2022-05-13 株式会社ディスコ 加工方法、エッチング装置、及びレーザ加工装置
US10916474B2 (en) 2018-06-25 2021-02-09 Semiconductor Components Industries, Llc Method of reducing residual contamination in singulated semiconductor die
CN110634796A (zh) 2018-06-25 2019-12-31 半导体元件工业有限责任公司 用于处理电子管芯的方法及半导体晶圆和管芯的切单方法
JP7109862B2 (ja) * 2018-07-10 2022-08-01 株式会社ディスコ 半導体ウェーハの加工方法
US11217550B2 (en) 2018-07-24 2022-01-04 Xilinx, Inc. Chip package assembly with enhanced interconnects and method for fabricating the same
JP7296835B2 (ja) 2019-09-19 2023-06-23 株式会社ディスコ ウェーハの処理方法、及び、チップ測定装置

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Also Published As

Publication number Publication date
JP2010147488A (ja) 2010-07-01
GB2420443B (en) 2009-09-16
US20090191690A1 (en) 2009-07-30
TW200625435A (en) 2006-07-16
KR20070051360A (ko) 2007-05-17
JP2008518450A (ja) 2008-05-29
TWI278032B (en) 2007-04-01
JP4690417B2 (ja) 2011-06-01
CN101088157B (zh) 2010-06-23
CN101088157A (zh) 2007-12-12
EP1825507A1 (en) 2007-08-29
EP1825507B1 (en) 2011-09-28
WO2006048230A1 (en) 2006-05-11
GB2420443A (en) 2006-05-24
GB0424195D0 (en) 2004-12-01

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