ATE526681T1 - Vergrössern der chipbelastungsfähigkeit durch ätzen während oder nach des zerteilens - Google Patents

Vergrössern der chipbelastungsfähigkeit durch ätzen während oder nach des zerteilens

Info

Publication number
ATE526681T1
ATE526681T1 AT05808203T AT05808203T ATE526681T1 AT E526681 T1 ATE526681 T1 AT E526681T1 AT 05808203 T AT05808203 T AT 05808203T AT 05808203 T AT05808203 T AT 05808203T AT E526681 T1 ATE526681 T1 AT E526681T1
Authority
AT
Austria
Prior art keywords
carrier
diving
semiconductor wafer
load capacity
etching during
Prior art date
Application number
AT05808203T
Other languages
English (en)
Inventor
Adrian Boyle
David Gillen
Kali Dunne
Gomez Eva Fernandes
Richard Toftness
Original Assignee
Electro Scient Ind Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Electro Scient Ind Inc filed Critical Electro Scient Ind Inc
Application granted granted Critical
Publication of ATE526681T1 publication Critical patent/ATE526681T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Dicing (AREA)
  • Weting (AREA)
  • Drying Of Semiconductors (AREA)
  • Polishing Bodies And Polishing Tools (AREA)
  • Processing Of Stones Or Stones Resemblance Materials (AREA)
AT05808203T 2004-11-01 2005-11-01 Vergrössern der chipbelastungsfähigkeit durch ätzen während oder nach des zerteilens ATE526681T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB0424195A GB2420443B (en) 2004-11-01 2004-11-01 Increasing die strength by etching during or after dicing
PCT/EP2005/011671 WO2006048230A1 (en) 2004-11-01 2005-11-01 Increasing die strength by etching during or after dicing

Publications (1)

Publication Number Publication Date
ATE526681T1 true ATE526681T1 (de) 2011-10-15

Family

ID=33515886

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05808203T ATE526681T1 (de) 2004-11-01 2005-11-01 Vergrössern der chipbelastungsfähigkeit durch ätzen während oder nach des zerteilens

Country Status (9)

Country Link
US (1) US20090191690A1 (de)
EP (1) EP1825507B1 (de)
JP (2) JP4690417B2 (de)
KR (1) KR20070051360A (de)
CN (1) CN101088157B (de)
AT (1) ATE526681T1 (de)
GB (1) GB2420443B (de)
TW (1) TWI278032B (de)
WO (1) WO2006048230A1 (de)

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GB2458475B (en) * 2008-03-18 2011-10-26 Xsil Technology Ltd Processing of multilayer semiconductor wafers
GB2459302A (en) * 2008-04-18 2009-10-21 Xsil Technology Ltd A method of dicing wafers to give high die strength
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US8673741B2 (en) 2011-06-24 2014-03-18 Electro Scientific Industries, Inc Etching a laser-cut semiconductor before dicing a die attach film (DAF) or other material layer
US8361828B1 (en) * 2011-08-31 2013-01-29 Alta Devices, Inc. Aligned frontside backside laser dicing of semiconductor films
US8399281B1 (en) * 2011-08-31 2013-03-19 Alta Devices, Inc. Two beam backside laser dicing of semiconductor films
US8536025B2 (en) * 2011-12-12 2013-09-17 International Business Machines Corporation Resized wafer with a negative photoresist ring and design structures thereof
US8952413B2 (en) 2012-03-08 2015-02-10 Micron Technology, Inc. Etched trenches in bond materials for die singulation, and associated systems and methods
US8664089B1 (en) * 2012-08-20 2014-03-04 Semiconductor Components Industries, Llc Semiconductor die singulation method
US9034733B2 (en) 2012-08-20 2015-05-19 Semiconductor Components Industries, Llc Semiconductor die singulation method
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US8980726B2 (en) * 2013-01-25 2015-03-17 Applied Materials, Inc. Substrate dicing by laser ablation and plasma etch damage removal for ultra-thin wafers
US9962938B2 (en) 2013-02-13 2018-05-08 Hewlett-Packard Development Company, L.P. Fluid feed slot for fluid ejection device
US9472458B2 (en) 2014-06-04 2016-10-18 Semiconductor Components Industries, Llc Method of reducing residual contamination in singulated semiconductor die
JP6282194B2 (ja) * 2014-07-30 2018-02-21 株式会社ディスコ ウェーハの加工方法
US9601437B2 (en) 2014-09-09 2017-03-21 Nxp B.V. Plasma etching and stealth dicing laser process
US9337098B1 (en) 2015-08-14 2016-05-10 Semiconductor Components Industries, Llc Semiconductor die back layer separation method
JP6587911B2 (ja) * 2015-11-16 2019-10-09 株式会社ディスコ ウエーハの分割方法
CN108630599A (zh) * 2017-03-22 2018-10-09 东莞新科技术研究开发有限公司 芯片的形成方法
US10373869B2 (en) 2017-05-24 2019-08-06 Semiconductor Components Industries, Llc Method of separating a back layer on a substrate using exposure to reduced temperature and related apparatus
CN107579032B (zh) * 2017-07-27 2019-04-09 厦门市三安集成电路有限公司 一种化合物半导体器件的背面制程方法
JP7066263B2 (ja) * 2018-01-23 2022-05-13 株式会社ディスコ 加工方法、エッチング装置、及びレーザ加工装置
US10916474B2 (en) 2018-06-25 2021-02-09 Semiconductor Components Industries, Llc Method of reducing residual contamination in singulated semiconductor die
JP7109862B2 (ja) * 2018-07-10 2022-08-01 株式会社ディスコ 半導体ウェーハの加工方法
US11217550B2 (en) 2018-07-24 2022-01-04 Xilinx, Inc. Chip package assembly with enhanced interconnects and method for fabricating the same
JP7296835B2 (ja) 2019-09-19 2023-06-23 株式会社ディスコ ウェーハの処理方法、及び、チップ測定装置

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Also Published As

Publication number Publication date
EP1825507B1 (de) 2011-09-28
GB0424195D0 (en) 2004-12-01
GB2420443B (en) 2009-09-16
WO2006048230A1 (en) 2006-05-11
CN101088157B (zh) 2010-06-23
US20090191690A1 (en) 2009-07-30
JP2008518450A (ja) 2008-05-29
CN101088157A (zh) 2007-12-12
EP1825507A1 (de) 2007-08-29
KR20070051360A (ko) 2007-05-17
TW200625435A (en) 2006-07-16
JP2010147488A (ja) 2010-07-01
GB2420443A (en) 2006-05-24
JP4690417B2 (ja) 2011-06-01
TWI278032B (en) 2007-04-01

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